2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/config.h>
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #include <asm/arch/debug-macro.S>
24 #if defined(CONFIG_DEBUG_ICEDCC)
28 mcr p14, 0, \ch, c0, c1, 0
35 #if defined(CONFIG_FOOTBRIDGE) || \
36 defined(CONFIG_ARCH_RPC) || \
37 defined(CONFIG_ARCH_INTEGRATOR) || \
38 defined(CONFIG_ARCH_PXA) || \
39 defined(CONFIG_ARCH_IXP4XX) || \
40 defined(CONFIG_ARCH_IXP2000) || \
41 defined(CONFIG_ARCH_LH7A40X) || \
42 defined(CONFIG_ARCH_OMAP) || \
43 defined(CONFIG_MACH_MP1000)
47 #elif defined(CONFIG_ARCH_SA1100)
49 mov \rb, #0x80000000 @ physical base address
50 # if defined(CONFIG_DEBUG_LL_SER3)
51 add \rb, \rb, #0x00050000 @ Ser3
53 add \rb, \rb, #0x00010000 @ Ser1
56 #elif defined(CONFIG_ARCH_IOP331)
59 orr \rb, \rb, #0x00ff0000
60 orr \rb, \rb, #0x0000f700 @ location of the UART
62 #elif defined(CONFIG_ARCH_S3C2410)
65 add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
68 #error no serial architecture defined
84 .macro debug_reloc_start
87 kphex r6, 8 /* processor id */
89 kphex r7, 8 /* architecture id */
91 mrc p15, 0, r0, c1, c0
92 kphex r0, 8 /* control reg */
94 kphex r5, 8 /* decompressed kernel start */
96 kphex r8, 8 /* decompressed kernel end */
98 kphex r4, 8 /* kernel execution address */
103 .macro debug_reloc_end
105 kphex r5, 8 /* end of kernel */
108 bl memdump /* dump 256 bytes at start of kernel */
112 .section ".start", #alloc, #execinstr
114 * sort out different calling conventions
118 .type start,#function
124 .word 0x016f2818 @ Magic numbers to help the loader
125 .word start @ absolute load/run zImage address
126 .word _edata @ zImage end address
127 1: mov r7, r1 @ save architecture ID
130 #ifndef __ARM_ARCH_2__
132 * Booting from Angel - need to enter SVC mode and disable
133 * FIQs/IRQs (numeric definitions from angel arm.h source).
134 * We only do this if we were in user mode on entry.
136 mrs r2, cpsr @ get current mode
137 tst r2, #3 @ not user?
139 mov r0, #0x17 @ angel_SWIreason_EnterSVC
140 swi 0x123456 @ angel_SWI_ARM
142 mrs r2, cpsr @ turn off interrupts to
143 orr r2, r2, #0xc0 @ prevent angel from running
146 teqp pc, #0x0c000003 @ turn off interrupts
150 * Note that some cache flushing and other stuff may
151 * be needed here - is there an Angel SWI call for this?
155 * some architecture specific code can be inserted
156 * by the linker here, but it should preserve r7 and r8.
161 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
162 subs r0, r0, r1 @ calculate the delta offset
164 @ if delta is zero, we are
165 beq not_relocated @ running at the address we
169 * We're running at a different address. We need to fix
170 * up various pointers:
171 * r5 - zImage base address
179 #ifndef CONFIG_ZBOOT_ROM
181 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
182 * we need to fix up pointers into the BSS region.
192 * Relocate all entries in the GOT table.
194 1: ldr r1, [r6, #0] @ relocate entries in the GOT
195 add r1, r1, r0 @ table. This fixes up the
196 str r1, [r6], #4 @ C references.
202 * Relocate entries in the GOT table. We only relocate
203 * the entries that are outside the (relocated) BSS region.
205 1: ldr r1, [r6, #0] @ relocate entries in the GOT
206 cmp r1, r2 @ entry < bss_start ||
207 cmphs r3, r1 @ _end < entry
208 addlo r1, r1, r0 @ table. This fixes up the
209 str r1, [r6], #4 @ C references.
214 not_relocated: mov r0, #0
215 1: str r0, [r2], #4 @ clear bss
223 * The C runtime environment should now be setup
224 * sufficiently. Turn the cache on, set up some
225 * pointers, and start decompressing.
229 mov r1, sp @ malloc space above stack
230 add r2, sp, #0x10000 @ 64k max
233 * Check to see if we will overwrite ourselves.
234 * r4 = final kernel address
235 * r5 = start of this image
236 * r2 = end of malloc space (and therefore this image)
239 * r4 + image length <= r5 -> OK
243 add r0, r4, #4096*1024 @ 4MB largest kernel size
247 mov r5, r2 @ decompress after malloc space
253 bic r0, r0, #127 @ align the kernel length
255 * r0 = decompressed kernel length
257 * r4 = kernel execution address
258 * r5 = decompressed kernel start
260 * r7 = architecture ID
263 add r1, r5, r0 @ end of decompressed kernel
267 1: ldmia r2!, {r8 - r13} @ copy relocation code
268 stmia r1!, {r8 - r13}
269 ldmia r2!, {r8 - r13}
270 stmia r1!, {r8 - r13}
275 add pc, r5, r0 @ call relocation code
278 * We're not in danger of overwriting ourselves. Do this the simple way.
280 * r4 = kernel execution address
281 * r7 = architecture ID
283 wont_overwrite: mov r0, r4
290 .word __bss_start @ r2
294 .word _got_start @ r6
296 .word user_stack+4096 @ sp
297 LC1: .word reloc_end - reloc_start
300 #ifdef CONFIG_ARCH_RPC
302 params: ldr r0, =params_phys
309 * Turn on the cache. We need to setup some page tables so that we
310 * can have both the I and D caches on.
312 * We place the page tables 16k down from the kernel execution address,
313 * and we hope that nothing else is using it. If we're using it, we
317 * r4 = kernel execution address
319 * r7 = architecture number
320 * r8 = run-time address of "start"
322 * r1, r2, r3, r8, r9, r12 corrupted
323 * This routine must preserve:
327 cache_on: mov r3, #8 @ cache_on function
330 __setup_mmu: sub r3, r4, #16384 @ Page directory size
331 bic r3, r3, #0xff @ Align the pointer
334 * Initialise the page tables, turning on the cacheable and bufferable
335 * bits for the RAM area only.
339 mov r8, r8, lsl #18 @ start of RAM
340 add r9, r8, #0x10000000 @ a reasonable RAM size
344 1: cmp r1, r8 @ if virt > start of RAM
345 orrhs r1, r1, #0x0c @ set cacheable, bufferable
346 cmp r1, r9 @ if virt > end of RAM
347 bichs r1, r1, #0x0c @ clear cacheable, bufferable
348 str r1, [r0], #4 @ 1:1 mapping
353 * If ever we are running from Flash, then we surely want the cache
354 * to be enabled also for our execution instance... We map 2MB of it
355 * so there is no map overlap problem for up to 1 MB compressed kernel.
356 * If the execution is in RAM then we would only be duplicating the above.
361 orr r1, r1, r2, lsl #20
362 add r0, r3, r2, lsl #2
372 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
373 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
374 mrc p15, 0, r0, c1, c0, 0 @ read control reg
375 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
379 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
386 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
387 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
391 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
396 orr r0, r0, #0x000d @ Write buffer, mmu
399 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
400 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
401 mcr p15, 0, r0, c1, c0, 0 @ load control register
405 * All code following this line is relocatable. It is relocated by
406 * the above code to the end of the decompressed kernel image and
407 * executed there. During this time, we have no stacks.
409 * r0 = decompressed kernel length
411 * r4 = kernel execution address
412 * r5 = decompressed kernel start
414 * r7 = architecture ID
418 reloc_start: add r8, r5, r0
423 ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
424 stmia r1!, {r0, r2, r3, r9 - r13}
431 call_kernel: bl cache_clean_flush
434 mov r1, r7 @ restore architecture number
435 mov pc, r4 @ call kernel
438 * Here follow the relocatable cache support functions for the
439 * various processors. This is a generic hook for locating an
440 * entry and jumping to an instruction at the specified offset
441 * from the start of the block. Please note this is all position
451 call_cache_fn: adr r12, proc_types
452 mrc p15, 0, r6, c0, c0 @ get processor ID
453 1: ldr r1, [r12, #0] @ get value
454 ldr r2, [r12, #4] @ get mask
455 eor r1, r1, r6 @ (real ^ match)
457 addeq pc, r12, r3 @ call cache function
462 * Table for cache operations. This is basically:
465 * - 'cache on' method instruction
466 * - 'cache off' method instruction
467 * - 'cache flush' method instruction
469 * We match an entry using: ((real_id ^ match) & mask) == 0
471 * Writethrough caches generally only need 'on' and 'off'
472 * methods. Writeback caches _must_ have the flush method
475 .type proc_types,#object
477 .word 0x41560600 @ ARM6/610
479 b __arm6_cache_off @ works, but slow
482 @ b __arm6_cache_on @ untested
484 @ b __armv3_cache_flush
486 .word 0x00000000 @ old ARM ID
492 .word 0x41007000 @ ARM7/710
498 .word 0x41807200 @ ARM720T (writethrough)
504 .word 0x00007000 @ ARM7 IDs
510 @ Everything from here on will be the new ID system.
512 .word 0x4401a100 @ sa110 / sa1100
516 b __armv4_cache_flush
518 .word 0x6901b110 @ sa1110
522 b __armv4_cache_flush
524 @ These match on the architecture ID
526 .word 0x00020000 @ ARMv4T
530 b __armv4_cache_flush
532 .word 0x00050000 @ ARMv5TE
536 b __armv4_cache_flush
538 .word 0x00060000 @ ARMv5TEJ
542 b __armv4_cache_flush
544 .word 0x00070000 @ ARMv6
548 b __armv6_cache_flush
550 .word 0 @ unrecognised type
556 .size proc_types, . - proc_types
559 * Turn off the Cache and MMU. ARMv3 does not support
560 * reading the control register, but ARMv4 does.
562 * On entry, r6 = processor ID
563 * On exit, r0, r1, r2, r3, r12 corrupted
564 * This routine must preserve: r4, r6, r7
567 cache_off: mov r3, #12 @ cache_off function
571 mrc p15, 0, r0, c1, c0
573 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
575 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
576 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
580 mov r0, #0x00000030 @ ARM6 control reg.
584 mov r0, #0x00000070 @ ARM7 control reg.
588 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
590 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
591 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
595 * Clean and flush the cache to maintain consistency.
600 * r1, r2, r3, r11, r12 corrupted
601 * This routine must preserve:
611 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
612 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
613 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
614 mcr p15, 0, r1, c7, c10, 4 @ drain WB
618 mov r2, #64*1024 @ default: 32K dcache size (*2)
619 mov r11, #32 @ default: 32 byte line size
620 mrc p15, 0, r3, c0, c0, 1 @ read cache type
621 teq r3, r6 @ cache ID register present?
626 mov r2, r2, lsl r1 @ base dcache size *2
627 tst r3, #1 << 14 @ test M bit
628 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
632 mov r11, r11, lsl r3 @ cache line size in bytes
634 bic r1, pc, #63 @ align to longest cache line
636 1: ldr r3, [r1], r11 @ s/w flush D cache
640 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
641 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
642 mcr p15, 0, r1, c7, c10, 4 @ drain WB
647 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
651 * Various debugging routines for printing hex characters and
652 * memory, which again must be relocatable.
655 .type phexbuf,#object
657 .size phexbuf, . - phexbuf
659 phex: adr r3, phexbuf
696 2: mov r0, r11, lsl #2
704 ldr r0, [r12, r11, lsl #2]
725 .section ".stack", "w"
726 user_stack: .space 4096