arch/arm/mach-omap1/board-h3.c

   1 /*
   2  * linux/arch/arm/mach-omap1/board-h3.c
   3  *
   4  * This file contains OMAP1710 H3 specific code.
   5  *
   6  * Copyright (C) 2004 Texas Instruments, Inc.
   7  * Copyright (C) 2002 MontaVista Software, Inc.
   8  * Copyright (C) 2001 RidgeRun, Inc.
   9  * Author: RidgeRun, Inc.
  10  *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/init.h>
  19 #include <linux/major.h>
  20 #include <linux/kernel.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/errno.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/input.h>
  28 #include <linux/clk.h>
  29 #include <linux/i2c.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/spi/tsc210x.h>
  32
  33 #include <asm/setup.h>
  34 #include <asm/page.h>
  35 #include <asm/hardware.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/flash.h>
  39 #include <asm/mach/map.h>
  40
  41 #include <media/v4l2-int-device.h>
  42
  43 #include <asm/arch/gpio.h>
  44 #include <asm/arch/gpio-switch.h>
  45 #include <asm/arch/gpioexpander.h>
  46 #include <asm/arch/irqs.h>
  47 #include <asm/arch/mux.h>
  48 #include <asm/arch/tc.h>
  49 #include <asm/arch/nand.h>
  50 #include <asm/arch/irda.h>
  51 #include <asm/arch/usb.h>
  52 #include <asm/arch/keypad.h>
  53 #include <asm/arch/dma.h>
  54 #include <asm/arch/common.h>
  55 #include <asm/arch/mcbsp.h>
  56 #include <asm/arch/omap-alsa.h>
  57
  58 #include <../drivers/media/video/ov9640.h>
  59
  60 #define H3_TS_GPIO      48
  61
  62 static int h3_keymap[] = {
  63         KEY(0, 0, KEY_LEFT),
  64         KEY(0, 1, KEY_RIGHT),
  65         KEY(0, 2, KEY_3),
  66         KEY(0, 3, KEY_F10),
  67         KEY(0, 4, KEY_F5),
  68         KEY(0, 5, KEY_9),
  69         KEY(1, 0, KEY_DOWN),
  70         KEY(1, 1, KEY_UP),
  71         KEY(1, 2, KEY_2),
  72         KEY(1, 3, KEY_F9),
  73         KEY(1, 4, KEY_F7),
  74         KEY(1, 5, KEY_0),
  75         KEY(2, 0, KEY_ENTER),
  76         KEY(2, 1, KEY_6),
  77         KEY(2, 2, KEY_1),
  78         KEY(2, 3, KEY_F2),
  79         KEY(2, 4, KEY_F6),
  80         KEY(2, 5, KEY_HOME),
  81         KEY(3, 0, KEY_8),
  82         KEY(3, 1, KEY_5),
  83         KEY(3, 2, KEY_F12),
  84         KEY(3, 3, KEY_F3),
  85         KEY(3, 4, KEY_F8),
  86         KEY(3, 5, KEY_END),
  87         KEY(4, 0, KEY_7),
  88         KEY(4, 1, KEY_4),
  89         KEY(4, 2, KEY_F11),
  90         KEY(4, 3, KEY_F1),
  91         KEY(4, 4, KEY_F4),
  92         KEY(4, 5, KEY_ESC),
  93         KEY(5, 0, KEY_F13),
  94         KEY(5, 1, KEY_F14),
  95         KEY(5, 2, KEY_F15),
  96         KEY(5, 3, KEY_F16),
  97         KEY(5, 4, KEY_SLEEP),
  98         0
  99 };
 100
 101
 102 static struct mtd_partition nor_partitions[] = {
 103         /* bootloader (U-Boot, etc) in first sector */
 104         {
 105               .name             = "bootloader",
 106               .offset           = 0,
 107               .size             = SZ_128K,
 108               .mask_flags       = MTD_WRITEABLE, /* force read-only */
 109         },
 110         /* bootloader params in the next sector */
 111         {
 112               .name             = "params",
 113               .offset           = MTDPART_OFS_APPEND,
 114               .size             = SZ_128K,
 115               .mask_flags       = 0,
 116         },
 117         /* kernel */
 118         {
 119               .name             = "kernel",
 120               .offset           = MTDPART_OFS_APPEND,
 121               .size             = SZ_2M,
 122               .mask_flags       = 0
 123         },
 124         /* file system */
 125         {
 126               .name             = "filesystem",
 127               .offset           = MTDPART_OFS_APPEND,
 128               .size             = MTDPART_SIZ_FULL,
 129               .mask_flags       = 0
 130         }
 131 };
 132
 133 static struct flash_platform_data nor_data = {
 134         .map_name       = "cfi_probe",
 135         .width          = 2,
 136         .parts          = nor_partitions,
 137         .nr_parts       = ARRAY_SIZE(nor_partitions),
 138 };
 139
 140 static struct resource nor_resource = {
 141         /* This is on CS3, wherever it's mapped */
 142         .flags          = IORESOURCE_MEM,
 143 };
 144
 145 static struct platform_device nor_device = {
 146         .name           = "omapflash",
 147         .id             = 0,
 148         .dev            = {
 149                 .platform_data  = &nor_data,
 150         },
 151         .num_resources  = 1,
 152         .resource       = &nor_resource,
 153 };
 154
 155 static struct mtd_partition nand_partitions[] = {
 156 #if 0
 157         /* REVISIT: enable these partitions if you make NAND BOOT work */
 158         {
 159                 .name           = "xloader",
 160                 .offset         = 0,
 161                 .size           = 64 * 1024,
 162                 .mask_flags     = MTD_WRITEABLE,        /* force read-only */
 163         },
 164         {
 165                 .name           = "bootloader",
 166                 .offset         = MTDPART_OFS_APPEND,
 167                 .size           = 256 * 1024,
 168                 .mask_flags     = MTD_WRITEABLE,        /* force read-only */
 169         },
 170         {
 171                 .name           = "params",
 172                 .offset         = MTDPART_OFS_APPEND,
 173                 .size           = 192 * 1024,
 174         },
 175         {
 176                 .name           = "kernel",
 177                 .offset         = MTDPART_OFS_APPEND,
 178                 .size           = 2 * SZ_1M,
 179         },
 180 #endif
 181         {
 182                 .name           = "filesystem",
 183                 .size           = MTDPART_SIZ_FULL,
 184                 .offset         = MTDPART_OFS_APPEND,
 185         },
 186 };
 187
 188 /* dip switches control NAND chip access:  8 bit, 16 bit, or neither */
 189 static struct omap_nand_platform_data nand_data = {
 190         .options        = NAND_SAMSUNG_LP_OPTIONS,
 191         .parts          = nand_partitions,
 192         .nr_parts       = ARRAY_SIZE(nand_partitions),
 193 };
 194
 195 static struct resource nand_resource = {
 196         .flags          = IORESOURCE_MEM,
 197 };
 198
 199 static struct platform_device nand_device = {
 200         .name           = "omapnand",
 201         .id             = 0,
 202         .dev            = {
 203                 .platform_data  = &nand_data,
 204         },
 205         .num_resources  = 1,
 206         .resource       = &nand_resource,
 207 };
 208
 209 static struct resource smc91x_resources[] = {
 210         [0] = {
 211                 .start  = OMAP1710_ETHR_START,          /* Physical */
 212                 .end    = OMAP1710_ETHR_START + 0xf,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         [1] = {
 216                 .start  = OMAP_GPIO_IRQ(40),
 217                 .end    = OMAP_GPIO_IRQ(40),
 218                 .flags  = IORESOURCE_IRQ,
 219         },
 220 };
 221
 222 static struct platform_device smc91x_device = {
 223         .name           = "smc91x",
 224         .id             = 0,
 225         .num_resources  = ARRAY_SIZE(smc91x_resources),
 226         .resource       = smc91x_resources,
 227 };
 228
 229 #define GPTIMER_BASE            0xFFFB1400
 230 #define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800))
 231 #define GPTIMER_REGS_SIZE       0x46
 232
 233 static struct resource intlat_resources[] = {
 234         [0] = {
 235                 .start  = GPTIMER_REGS(0),            /* Physical */
 236                 .end    = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE,
 237                 .flags  = IORESOURCE_MEM,
 238         },
 239         [1] = {
 240                 .start  = INT_1610_GPTIMER1,
 241                 .end    = INT_1610_GPTIMER1,
 242                 .flags  = IORESOURCE_IRQ,
 243         },
 244 };
 245
 246 static struct platform_device intlat_device = {
 247         .name      = "omap_intlat",
 248         .id          = 0,
 249         .num_resources  = ARRAY_SIZE(intlat_resources),
 250         .resource       = intlat_resources,
 251 };
 252
 253 static struct resource h3_kp_resources[] = {
 254         [0] = {
 255                 .start  = INT_KEYBOARD,
 256                 .end    = INT_KEYBOARD,
 257                 .flags  = IORESOURCE_IRQ,
 258         },
 259 };
 260
 261 static struct omap_kp_platform_data h3_kp_data = {
 262         .rows           = 8,
 263         .cols           = 8,
 264         .keymap         = h3_keymap,
 265         .keymapsize     = ARRAY_SIZE(h3_keymap),
 266         .rep            = 1,
 267         .delay          = 9,
 268         .dbounce        = 1,
 269 };
 270
 271 static struct platform_device h3_kp_device = {
 272         .name           = "omap-keypad",
 273         .id             = -1,
 274         .dev            = {
 275                 .platform_data = &h3_kp_data,
 276         },
 277         .num_resources  = ARRAY_SIZE(h3_kp_resources),
 278         .resource       = h3_kp_resources,
 279 };
 280
 281
 282 /* Select between the IrDA and aGPS module
 283  */
 284 static int h3_select_irda(struct device *dev, int state)
 285 {
 286         unsigned char expa;
 287         int err = 0;
 288
 289         if ((err = read_gpio_expa(&expa, 0x26))) {
 290                 printk(KERN_ERR "Error reading from I/O EXPANDER \n");
 291                 return err;
 292         }
 293
 294         /* 'P6' enable/disable IRDA_TX and IRDA_RX */
 295         if (state & IR_SEL) { /* IrDA */
 296                 if ((err = write_gpio_expa(expa | 0x40, 0x26))) {
 297                         printk(KERN_ERR "Error writing to I/O EXPANDER \n");
 298                         return err;
 299                 }
 300         } else {
 301                 if ((err = write_gpio_expa(expa & ~0x40, 0x26))) {
 302                         printk(KERN_ERR "Error writing to I/O EXPANDER \n");
 303                         return err;
 304                 }
 305         }
 306         return err;
 307 }
 308
 309 static void set_trans_mode(struct work_struct *work)
 310 {
 311         struct omap_irda_config *irda_config =
 312                 container_of(work, struct omap_irda_config, gpio_expa.work);
 313         int mode = irda_config->mode;
 314         unsigned char expa;
 315         int err = 0;
 316
 317         if ((err = read_gpio_expa(&expa, 0x27)) != 0) {
 318                 printk(KERN_ERR "Error reading from I/O expander\n");
 319         }
 320
 321         expa &= ~0x03;
 322
 323         if (mode & IR_SIRMODE) {
 324                 expa |= 0x01;
 325         } else { /* MIR/FIR */
 326                 expa |= 0x03;
 327         }
 328
 329         if ((err = write_gpio_expa(expa, 0x27)) != 0) {
 330                 printk(KERN_ERR "Error writing to I/O expander\n");
 331         }
 332 }
 333
 334 static int h3_transceiver_mode(struct device *dev, int mode)
 335 {
 336         struct omap_irda_config *irda_config = dev->platform_data;
 337
 338         irda_config->mode = mode;
 339         cancel_delayed_work(&irda_config->gpio_expa);
 340         PREPARE_DELAYED_WORK(&irda_config->gpio_expa, set_trans_mode);
 341         schedule_delayed_work(&irda_config->gpio_expa, 0);
 342
 343         return 0;
 344 }
 345
 346 static struct omap_irda_config h3_irda_data = {
 347         .transceiver_cap        = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
 348         .transceiver_mode       = h3_transceiver_mode,
 349         .select_irda            = h3_select_irda,
 350         .rx_channel             = OMAP_DMA_UART3_RX,
 351         .tx_channel             = OMAP_DMA_UART3_TX,
 352         .dest_start             = UART3_THR,
 353         .src_start              = UART3_RHR,
 354         .tx_trigger             = 0,
 355         .rx_trigger             = 0,
 356 };
 357
 358 static struct resource h3_irda_resources[] = {
 359         [0] = {
 360                 .start  = INT_UART3,
 361                 .end    = INT_UART3,
 362                 .flags  = IORESOURCE_IRQ,
 363         },
 364 };
 365
 366 static u64 irda_dmamask = 0xffffffff;
 367
 368 static struct platform_device h3_irda_device = {
 369         .name           = "omapirda",
 370         .id             = 0,
 371         .dev            = {
 372                 .platform_data  = &h3_irda_data,
 373                 .dma_mask       = &irda_dmamask,
 374         },
 375         .num_resources  = ARRAY_SIZE(h3_irda_resources),
 376         .resource       = h3_irda_resources,
 377 };
 378
 379 static struct platform_device h3_lcd_device = {
 380         .name           = "lcd_h3",
 381         .id             = -1,
 382 };
 383
 384 static struct tsc210x_config tsc_platform_data = {
 385         .use_internal           = 1,
 386         .monitor                = TSC_VBAT | TSC_TEMP,
 387         .mclk                   = "mclk",
 388 };
 389
 390 static struct spi_board_info h3_spi_board_info[] __initdata = {
 391         [0] = {
 392                 .modalias       = "tsc2101",
 393                 .bus_num        = 2,
 394                 .chip_select    = 0,
 395                 .irq            = OMAP_GPIO_IRQ(H3_TS_GPIO),
 396                 .max_speed_hz   = 16000000,
 397                 .platform_data  = &tsc_platform_data,
 398         },
 399 };
 400
 401 static struct omap_mcbsp_reg_cfg mcbsp_regs = {
 402         .spcr2 = FREE | FRST | GRST | XRST | XINTM(3),
 403         .spcr1 = RINTM(3) | RRST,
 404         .rcr2  = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) |
 405                 RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(1),
 406         .rcr1  = RFRLEN1(OMAP_MCBSP_WORD_8) | RWDLEN1(OMAP_MCBSP_WORD_16),
 407         .xcr2  = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) |
 408                 XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
 409         .xcr1  = XFRLEN1(OMAP_MCBSP_WORD_8) | XWDLEN1(OMAP_MCBSP_WORD_16),
 410         .srgr1 = FWID(15),
 411         .srgr2 = GSYNC | CLKSP | FSGM | FPER(31),
 412
 413         .pcr0  = CLKRM | SCLKME | FSXP | FSRP | CLKXP | CLKRP,
 414         /*.pcr0 = CLKXP | CLKRP,*/        /* mcbsp: slave */
 415 };
 416
 417 static struct omap_alsa_codec_config alsa_config = {
 418         .name                   = "H3 TSC2101",
 419         .mcbsp_regs_alsa        = &mcbsp_regs,
 420         .codec_configure_dev    = NULL, /* tsc2101_configure, */
 421         .codec_set_samplerate   = NULL, /* tsc2101_set_samplerate, */
 422         .codec_clock_setup      = NULL, /* tsc2101_clock_setup, */
 423         .codec_clock_on         = NULL, /* tsc2101_clock_on, */
 424         .codec_clock_off        = NULL, /* tsc2101_clock_off, */
 425         .get_default_samplerate = NULL, /* tsc2101_get_default_samplerate, */
 426 };
 427
 428 static struct platform_device h3_mcbsp1_device = {
 429         .name   = "omap_alsa_mcbsp",
 430         .id     = 1,
 431         .dev = {
 432                 .platform_data  = &alsa_config,
 433         },
 434 };
 435
 436 static struct platform_device *devices[] __initdata = {
 437         &nor_device,
 438         &nand_device,
 439         &smc91x_device,
 440         &intlat_device,
 441         &h3_irda_device,
 442         &h3_kp_device,
 443         &h3_lcd_device,
 444         &h3_mcbsp1_device,
 445 };
 446
 447 static struct omap_usb_config h3_usb_config __initdata = {
 448         /* usb1 has a Mini-AB port and external isp1301 transceiver */
 449         .otg        = 2,
 450
 451 #ifdef CONFIG_USB_GADGET_OMAP
 452         .hmc_mode       = 19,   /* 0:host(off) 1:dev|otg 2:disabled */
 453 #elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 454         /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
 455         .hmc_mode       = 20,   /* 1:dev|otg(off) 1:host 2:disabled */
 456 #endif
 457
 458         .pins[1]        = 3,
 459 };
 460
 461 static struct omap_mmc_config h3_mmc_config __initdata = {
 462         .mmc[0] = {
 463                 .enabled        = 1,
 464                 .wire4          = 1,
 465        },
 466 };
 467
 468 extern struct omap_mmc_platform_data h3_mmc_data;
 469
 470 static struct omap_uart_config h3_uart_config __initdata = {
 471         .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
 472 };
 473
 474 static struct omap_lcd_config h3_lcd_config __initdata = {
 475         .ctrl_name      = "internal",
 476 };
 477
 478 static struct omap_board_config_kernel h3_config[] __initdata = {
 479         { OMAP_TAG_USB,         &h3_usb_config },
 480         { OMAP_TAG_MMC,         &h3_mmc_config },
 481         { OMAP_TAG_UART,        &h3_uart_config },
 482         { OMAP_TAG_LCD,         &h3_lcd_config },
 483 };
 484
 485 static struct omap_gpio_switch h3_gpio_switches[] __initdata = {
 486         {
 487                 .name                   = "mmc_slot",
 488                 .gpio                   = OMAP_MPUIO(1),
 489                 .type                   = OMAP_GPIO_SWITCH_TYPE_COVER,
 490                 .debounce_rising        = 100,
 491                 .debounce_falling       = 0,
 492                 .notify                 = h3_mmc_slot_cover_handler,
 493                 .notify_data            = NULL,
 494         },
 495 };
 496
 497 #define H3_NAND_RB_GPIO_PIN     10
 498
 499 static int nand_dev_ready(struct omap_nand_platform_data *data)
 500 {
 501         return omap_get_gpio_datain(H3_NAND_RB_GPIO_PIN);
 502 }
 503
 504 #if defined(CONFIG_VIDEO_OV9640) || defined(CONFIG_VIDEO_OV9640_MODULE)
 505 /*
 506  * Common OV9640 register initialization for all image sizes, pixel formats,
 507  * and frame rates
 508  */
 509 const static struct ov9640_reg ov9640_common[] = {
 510
 511         { 0x12, 0x80 }, { 0x11, 0x80 }, { 0x13, 0x88 }, /* COM7, CLKRC, COM8 */
 512         { 0x01, 0x58 }, { 0x02, 0x24 }, { 0x04, 0x00 }, /* BLUE, RED, COM1 */
 513         { 0x0E, 0x81 }, { 0x0F, 0x4F }, { 0x14, 0xcA }, /* COM5, COM6, COM9 */
 514         { 0x16, 0x02 }, { 0x1B, 0x01 }, { 0x24, 0x70 }, /* ?, PSHFT, AEW */
 515         { 0x25, 0x68 }, { 0x26, 0xD3 }, { 0x27, 0x90 }, /* AEB, VPT, BBIAS */
 516         { 0x2A, 0x00 }, { 0x2B, 0x00 }, { 0x32, 0x24 }, /* EXHCH, EXHCL, HREF */
 517         { 0x33, 0x02 }, { 0x37, 0x02 }, { 0x38, 0x13 }, /* CHLF, ADC, ACOM */
 518         { 0x39, 0xF0 }, { 0x3A, 0x00 }, { 0x3B, 0x01 }, /* OFON, TSLB, COM11 */
 519         { 0x3D, 0x90 }, { 0x3E, 0x02 }, { 0x3F, 0xF2 }, /* COM13, COM14, EDGE */
 520         { 0x41, 0x02 }, { 0x42, 0xC8 },         /* COM16, COM17 */
 521         { 0x43, 0xF0 }, { 0x44, 0x10 }, { 0x45, 0x6C }, /* ?, ?, ? */
 522         { 0x46, 0x6C }, { 0x47, 0x44 }, { 0x48, 0x44 }, /* ?, ?, ? */
 523         { 0x49, 0x03 }, { 0x59, 0x49 }, { 0x5A, 0x94 }, /* ?, ?, ? */
 524         { 0x5B, 0x46 }, { 0x5C, 0x84 }, { 0x5D, 0x5C }, /* ?, ?, ? */
 525         { 0x5E, 0x08 }, { 0x5F, 0x00 }, { 0x60, 0x14 }, /* ?, ?, ? */
 526         { 0x61, 0xCE },                                 /* ? */
 527         { 0x62, 0x70 }, { 0x63, 0x00 }, { 0x64, 0x04 }, /* LCC1, LCC2, LCC3 */
 528         { 0x65, 0x00 }, { 0x66, 0x00 },                 /* LCC4, LCC5 */
 529         { 0x69, 0x00 }, { 0x6A, 0x3E }, { 0x6B, 0x3F }, /* HV, MBD, DBLV */
 530         { 0x6C, 0x40 }, { 0x6D, 0x30 }, { 0x6E, 0x4B }, /* GSP1, GSP2, GSP3 */
 531         { 0x6F, 0x60 }, { 0x70, 0x70 }, { 0x71, 0x70 }, /* GSP4, GSP5, GSP6 */
 532         { 0x72, 0x70 }, { 0x73, 0x70 }, { 0x74, 0x60 }, /* GSP7, GSP8, GSP9 */
 533         { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 }, /* GSP10,GSP11,GSP12 */
 534         { 0x78, 0x3A }, { 0x79, 0x2E }, { 0x7A, 0x28 }, /* GSP13,GSP14,GSP15 */
 535         { 0x7B, 0x22 }, { 0x7C, 0x04 }, { 0x7D, 0x07 }, /* GSP16,GST1, GST2 */
 536         { 0x7E, 0x10 }, { 0x7F, 0x28 }, { 0x80, 0x36 }, /* GST3, GST4, GST5 */
 537         { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 }, /* GST6, GST7, GST8 */
 538         { 0x84, 0x6C }, { 0x85, 0x78 }, { 0x86, 0x8C }, /* GST9, GST10,GST11 */
 539         { 0x87, 0x9E }, { 0x88, 0xBB }, { 0x89, 0xD2 }, /* GST12,GST13,GST14 */
 540         { 0x8A, 0xE6 }, { 0x13, 0xaF }, { 0x15, 0x02 }, /* GST15, COM8 */
 541         { 0x22, 0x8a }, /* GROS */
 542         { OV9640_REG_TERM, OV9640_VAL_TERM }
 543 };
 544
 545 static int ov9640_sensor_power_set(int power)
 546 {
 547         unsigned char expa;
 548         int err;
 549
 550         /* read current state of GPIO EXPA outputs */
 551         err = read_gpio_expa(&expa, 0x27);
 552         if (err) {
 553                 printk(KERN_ERR "Error reading GPIO EXPA\n");
 554                 return err;
 555         }
 556         /* Clear GPIO EXPA P3 (CAMERA_MODULE_EN) to power-up/down sensor */
 557         if (power)
 558                 expa |= 0x08;
 559         else
 560                 expa &= ~0x08;
 561
 562         err = write_gpio_expa(expa, 0x27);
 563         if (err) {
 564                 printk(KERN_ERR "Error writing to GPIO EXPA\n");
 565                 return err;
 566         }
 567
 568         return err;
 569 }
 570
 571 static struct v4l2_ifparm ifparm = {
 572         .if_type = V4L2_IF_TYPE_BT656,
 573         .u = {
 574                 .bt656 = {
 575                          .frame_start_on_rising_vs = 1,
 576                          .nobt_vs_inv = 1,
 577                          .mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT,
 578                          .clock_min = OV9640_XCLK_MIN,
 579                          .clock_max = OV9640_XCLK_MAX,
 580                  },
 581         },
 582 };
 583
 584 static int ov9640_ifparm(struct v4l2_ifparm *p)
 585 {
 586         *p = ifparm;
 587
 588         return 0;
 589 }
 590
 591 static struct ov9640_platform_data h3_ov9640_platform_data = {
 592         .power_set      = ov9640_sensor_power_set,
 593         .default_regs   = ov9640_common,
 594         .ifparm         = ov9640_ifparm,
 595 };
 596 #endif
 597
 598 static struct i2c_board_info __initdata h3_i2c_board_info[] = {
 599 #if defined(CONFIG_VIDEO_OV9640) || defined(CONFIG_VIDEO_OV9640_MODULE)
 600         {
 601                 I2C_BOARD_INFO("ov9640", 0x30),
 602                 .platform_data = &h3_ov9640_platform_data,
 603         },
 604 #endif
 605         {
 606                 I2C_BOARD_INFO("isp1301_omap", 0x2d),
 607                 .type           = "isp1301_omap",
 608                 .irq            = OMAP_GPIO_IRQ(14),
 609         },
 610 };
 611
 612 static void __init h3_init(void)
 613 {
 614         /* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
 615          * to address 0 by a dip switch), NAND on CS2B.  The NAND driver will
 616          * notice whether a NAND chip is enabled at probe time.
 617          *
 618          * H3 support NAND-boot, with a dip switch to put NOR on CS2B and NAND
 619          * (which on H2 may be 16bit) on CS3.  Try detecting that in code here,
 620          * to avoid probing every possible flash configuration...
 621          */
 622         nor_resource.end = nor_resource.start = omap_cs3_phys();
 623         nor_resource.end += SZ_32M - 1;
 624
 625         nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS;
 626         nand_resource.end += SZ_4K - 1;
 627         if (!(omap_request_gpio(H3_NAND_RB_GPIO_PIN)))
 628                 nand_data.dev_ready = nand_dev_ready;
 629
 630         /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
 631         /* GPIO10 pullup/down register, Enable pullup on GPIO10 */
 632         omap_cfg_reg(V2_1710_GPIO10);
 633
 634         /* TSC2101 */
 635         omap_cfg_reg(W19_1610_GPIO48);
 636         gpio_request(H3_TS_GPIO, "tsc_irq");
 637         gpio_direction_input(H3_TS_GPIO);
 638         omap_cfg_reg(N14_1610_UWIRE_CS0);
 639
 640         platform_add_devices(devices, ARRAY_SIZE(devices));
 641         spi_register_board_info(h3_spi_board_info,
 642                                 ARRAY_SIZE(h3_spi_board_info));
 643         omap_board_config = h3_config;
 644         omap_board_config_size = ARRAY_SIZE(h3_config);
 645         omap_serial_init();
 646         omap_register_i2c_bus(1, 100, h3_i2c_board_info,
 647                               ARRAY_SIZE(h3_i2c_board_info));
 648         h3_mmc_init();
 649         omap_register_gpio_switches(h3_gpio_switches,
 650                                     ARRAY_SIZE(h3_gpio_switches));
 651 }
 652
 653 static void __init h3_init_smc91x(void)
 654 {
 655         omap_cfg_reg(W15_1710_GPIO40);
 656         if (omap_request_gpio(40) < 0) {
 657                 printk("Error requesting gpio 40 for smc91x irq\n");
 658                 return;
 659         }
 660 }
 661
 662 static void __init h3_init_irq(void)
 663 {
 664         omap1_init_common_hw();
 665         omap_init_irq();
 666         omap_gpio_init();
 667         h3_init_smc91x();
 668 }
 669
 670 static void __init h3_map_io(void)
 671 {
 672         omap1_map_common_io();
 673 }
 674
 675 MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
 676         /* Maintainer: Texas Instruments, Inc. */
 677         .phys_io        = 0xfff00000,
 678         .io_pg_offst    = ((0xfef00000) >> 18) & 0xfffc,
 679         .boot_params    = 0x10000100,
 680         .map_io         = h3_map_io,
 681         .init_irq       = h3_init_irq,
 682         .init_machine   = h3_init,
 683         .timer          = &omap_timer,
 684 MACHINE_END