2 * linux/arch/arm/mach-omap1/clock.h
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
16 static void omap1_ckctl_recalc(struct clk * clk);
17 static void omap1_watchdog_recalc(struct clk * clk);
18 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
19 static void omap1_sossi_recalc(struct clk *clk);
20 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
21 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
22 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
23 static void omap1_uart_recalc(struct clk * clk);
24 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
25 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
26 static void omap1_init_ext_clk(struct clk * clk);
27 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
28 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
33 unsigned long pll_rate;
40 unsigned long sysc_addr;
43 /* Provide a method for preventing idling some ARM IDLECT clocks */
44 struct arm_idlect1_clk {
46 unsigned long no_idle_count;
50 /* ARM_CKCTL bit shifts */
51 #define CKCTL_PERDIV_OFFSET 0
52 #define CKCTL_LCDDIV_OFFSET 2
53 #define CKCTL_ARMDIV_OFFSET 4
54 #define CKCTL_DSPDIV_OFFSET 6
55 #define CKCTL_TCDIV_OFFSET 8
56 #define CKCTL_DSPMMUDIV_OFFSET 10
57 /*#define ARM_TIMXO 12*/
59 /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
60 /* DSP_CKCTL bit shifts */
61 #define CKCTL_DSPPERDIV_OFFSET 0
63 /* ARM_IDLECT2 bit shifts */
68 #define EN_LBCK 4 /* Not on 1610/1710 */
69 /*#define EN_HSABCK 5*/
73 #define EN_GPIOCK 9 /* Not on 1610/1710 */
74 /*#define EN_LBFREECK 10*/
75 #define EN_CKOUT_ARM 11
77 /* ARM_IDLECT3 bit shifts */
82 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
85 /* Various register defines for clock controls scattered around OMAP chip */
86 #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
87 #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
88 #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
89 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
90 #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
91 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
92 #define COM_CLK_DIV_CTRL_SEL 0xfffe0878
93 #define SOFT_REQ_REG 0xfffe0834
94 #define SOFT_REQ_REG2 0xfffe0880
96 /*-------------------------------------------------------------------------
97 * Omap1 MPU rate table
98 *-------------------------------------------------------------------------*/
99 static struct mpu_rate rate_table[] = {
100 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
101 * NOTE: Comment order here is different from bits in CKCTL value:
102 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
104 #if defined(CONFIG_OMAP_ARM_216MHZ)
105 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
107 #if defined(CONFIG_OMAP_ARM_195MHZ)
108 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
110 #if defined(CONFIG_OMAP_ARM_192MHZ)
111 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
112 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
113 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
114 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
115 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
117 #if defined(CONFIG_OMAP_ARM_182MHZ)
118 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
120 #if defined(CONFIG_OMAP_ARM_168MHZ)
121 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
123 #if defined(CONFIG_OMAP_ARM_150MHZ)
124 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
126 #if defined(CONFIG_OMAP_ARM_120MHZ)
127 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
129 #if defined(CONFIG_OMAP_ARM_96MHZ)
130 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
132 #if defined(CONFIG_OMAP_ARM_60MHZ)
133 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
135 #if defined(CONFIG_OMAP_ARM_30MHZ)
136 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
141 /*-------------------------------------------------------------------------
143 *-------------------------------------------------------------------------*/
145 static struct clk ck_ref = {
147 .ops = &clkops_generic,
149 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
150 CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
153 static struct clk ck_dpll1 = {
155 .ops = &clkops_generic,
157 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
158 CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
161 static struct arm_idlect1_clk ck_dpll1out = {
163 .name = "ck_dpll1out",
164 .ops = &clkops_generic,
166 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
167 ENABLE_REG_32BIT | RATE_PROPAGATES,
168 .enable_reg = (void __iomem *)ARM_IDLECT2,
169 .enable_bit = EN_CKOUT_ARM,
170 .recalc = &followparent_recalc,
175 static struct clk sossi_ck = {
177 .ops = &clkops_generic,
178 .parent = &ck_dpll1out.clk,
179 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
181 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
183 .recalc = &omap1_sossi_recalc,
184 .set_rate = &omap1_set_sossi_rate,
187 static struct clk arm_ck = {
189 .ops = &clkops_generic,
191 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
192 CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
194 .rate_offset = CKCTL_ARMDIV_OFFSET,
195 .recalc = &omap1_ckctl_recalc,
198 static struct arm_idlect1_clk armper_ck = {
201 .ops = &clkops_generic,
203 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
204 CLOCK_IN_OMAP310 | RATE_CKCTL |
206 .enable_reg = (void __iomem *)ARM_IDLECT2,
207 .enable_bit = EN_PERCK,
208 .rate_offset = CKCTL_PERDIV_OFFSET,
209 .recalc = &omap1_ckctl_recalc,
214 static struct clk arm_gpio_ck = {
215 .name = "arm_gpio_ck",
216 .ops = &clkops_generic,
218 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
219 .enable_reg = (void __iomem *)ARM_IDLECT2,
220 .enable_bit = EN_GPIOCK,
221 .recalc = &followparent_recalc,
224 static struct arm_idlect1_clk armxor_ck = {
227 .ops = &clkops_generic,
229 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
230 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
231 .enable_reg = (void __iomem *)ARM_IDLECT2,
232 .enable_bit = EN_XORPCK,
233 .recalc = &followparent_recalc,
238 static struct arm_idlect1_clk armtim_ck = {
241 .ops = &clkops_generic,
243 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
244 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
245 .enable_reg = (void __iomem *)ARM_IDLECT2,
246 .enable_bit = EN_TIMCK,
247 .recalc = &followparent_recalc,
252 static struct arm_idlect1_clk armwdt_ck = {
255 .ops = &clkops_generic,
257 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
258 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
259 .enable_reg = (void __iomem *)ARM_IDLECT2,
260 .enable_bit = EN_WDTCK,
261 .recalc = &omap1_watchdog_recalc,
266 static struct clk arminth_ck16xx = {
267 .name = "arminth_ck",
268 .ops = &clkops_generic,
270 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
271 .recalc = &followparent_recalc,
272 /* Note: On 16xx the frequency can be divided by 2 by programming
273 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
275 * 1510 version is in TC clocks.
279 static struct clk dsp_ck = {
281 .ops = &clkops_generic,
283 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
285 .enable_reg = (void __iomem *)ARM_CKCTL,
286 .enable_bit = EN_DSPCK,
287 .rate_offset = CKCTL_DSPDIV_OFFSET,
288 .recalc = &omap1_ckctl_recalc,
291 static struct clk dspmmu_ck = {
293 .ops = &clkops_generic,
295 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
296 RATE_CKCTL | ALWAYS_ENABLED,
297 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
298 .recalc = &omap1_ckctl_recalc,
301 static struct clk dspper_ck = {
303 .ops = &clkops_dspck,
305 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
306 RATE_CKCTL | VIRTUAL_IO_ADDRESS,
307 .enable_reg = DSP_IDLECT2,
308 .enable_bit = EN_PERCK,
309 .rate_offset = CKCTL_PERDIV_OFFSET,
310 .recalc = &omap1_ckctl_recalc_dsp_domain,
311 .set_rate = &omap1_clk_set_rate_dsp_domain,
314 static struct clk dspxor_ck = {
316 .ops = &clkops_dspck,
318 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
320 .enable_reg = DSP_IDLECT2,
321 .enable_bit = EN_XORPCK,
322 .recalc = &followparent_recalc,
325 static struct clk dsptim_ck = {
327 .ops = &clkops_dspck,
329 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
331 .enable_reg = DSP_IDLECT2,
332 .enable_bit = EN_DSPTIMCK,
333 .recalc = &followparent_recalc,
336 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
337 static struct arm_idlect1_clk tc_ck = {
340 .ops = &clkops_generic,
342 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
343 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
344 RATE_CKCTL | RATE_PROPAGATES |
345 ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
346 .rate_offset = CKCTL_TCDIV_OFFSET,
347 .recalc = &omap1_ckctl_recalc,
352 static struct clk arminth_ck1510 = {
353 .name = "arminth_ck",
354 .ops = &clkops_generic,
355 .parent = &tc_ck.clk,
356 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
358 .recalc = &followparent_recalc,
359 /* Note: On 1510 the frequency follows TC_CK
361 * 16xx version is in MPU clocks.
365 static struct clk tipb_ck = {
366 /* No-idle controlled by "tc_ck" */
368 .ops = &clkops_generic,
369 .parent = &tc_ck.clk,
370 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
372 .recalc = &followparent_recalc,
375 static struct clk l3_ocpi_ck = {
376 /* No-idle controlled by "tc_ck" */
377 .name = "l3_ocpi_ck",
378 .ops = &clkops_generic,
379 .parent = &tc_ck.clk,
380 .flags = CLOCK_IN_OMAP16XX,
381 .enable_reg = (void __iomem *)ARM_IDLECT3,
382 .enable_bit = EN_OCPI_CK,
383 .recalc = &followparent_recalc,
386 static struct clk tc1_ck = {
388 .ops = &clkops_generic,
389 .parent = &tc_ck.clk,
390 .flags = CLOCK_IN_OMAP16XX,
391 .enable_reg = (void __iomem *)ARM_IDLECT3,
392 .enable_bit = EN_TC1_CK,
393 .recalc = &followparent_recalc,
396 static struct clk tc2_ck = {
398 .ops = &clkops_generic,
399 .parent = &tc_ck.clk,
400 .flags = CLOCK_IN_OMAP16XX,
401 .enable_reg = (void __iomem *)ARM_IDLECT3,
402 .enable_bit = EN_TC2_CK,
403 .recalc = &followparent_recalc,
406 static struct clk dma_ck = {
407 /* No-idle controlled by "tc_ck" */
409 .ops = &clkops_generic,
410 .parent = &tc_ck.clk,
411 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
412 CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
413 .recalc = &followparent_recalc,
416 static struct clk dma_lcdfree_ck = {
417 .name = "dma_lcdfree_ck",
418 .ops = &clkops_generic,
419 .parent = &tc_ck.clk,
420 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
421 .recalc = &followparent_recalc,
424 static struct arm_idlect1_clk api_ck = {
427 .ops = &clkops_generic,
428 .parent = &tc_ck.clk,
429 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
430 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
431 .enable_reg = (void __iomem *)ARM_IDLECT2,
432 .enable_bit = EN_APICK,
433 .recalc = &followparent_recalc,
438 static struct arm_idlect1_clk lb_ck = {
441 .ops = &clkops_generic,
442 .parent = &tc_ck.clk,
443 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
445 .enable_reg = (void __iomem *)ARM_IDLECT2,
446 .enable_bit = EN_LBCK,
447 .recalc = &followparent_recalc,
452 static struct clk rhea1_ck = {
454 .ops = &clkops_generic,
455 .parent = &tc_ck.clk,
456 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
457 .recalc = &followparent_recalc,
460 static struct clk rhea2_ck = {
462 .ops = &clkops_generic,
463 .parent = &tc_ck.clk,
464 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
465 .recalc = &followparent_recalc,
468 static struct clk lcd_ck_16xx = {
470 .ops = &clkops_generic,
472 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
473 .enable_reg = (void __iomem *)ARM_IDLECT2,
474 .enable_bit = EN_LCDCK,
475 .rate_offset = CKCTL_LCDDIV_OFFSET,
476 .recalc = &omap1_ckctl_recalc,
479 static struct arm_idlect1_clk lcd_ck_1510 = {
482 .ops = &clkops_generic,
484 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
485 RATE_CKCTL | CLOCK_IDLE_CONTROL,
486 .enable_reg = (void __iomem *)ARM_IDLECT2,
487 .enable_bit = EN_LCDCK,
488 .rate_offset = CKCTL_LCDDIV_OFFSET,
489 .recalc = &omap1_ckctl_recalc,
494 static struct clk uart1_1510 = {
496 .ops = &clkops_generic,
497 /* Direct from ULPD, no real parent */
498 .parent = &armper_ck.clk,
500 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
501 ENABLE_REG_32BIT | ALWAYS_ENABLED |
502 CLOCK_NO_IDLE_PARENT,
503 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
504 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
505 .set_rate = &omap1_set_uart_rate,
506 .recalc = &omap1_uart_recalc,
509 static struct uart_clk uart1_16xx = {
513 /* Direct from ULPD, no real parent */
514 .parent = &armper_ck.clk,
516 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
517 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
518 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
521 .sysc_addr = 0xfffb0054,
524 static struct clk uart2_ck = {
526 .ops = &clkops_generic,
527 /* Direct from ULPD, no real parent */
528 .parent = &armper_ck.clk,
530 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
531 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
532 ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
533 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
534 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
535 .set_rate = &omap1_set_uart_rate,
536 .recalc = &omap1_uart_recalc,
539 static struct clk uart3_1510 = {
541 .ops = &clkops_generic,
542 /* Direct from ULPD, no real parent */
543 .parent = &armper_ck.clk,
545 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
546 ENABLE_REG_32BIT | ALWAYS_ENABLED |
547 CLOCK_NO_IDLE_PARENT,
548 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
549 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
550 .set_rate = &omap1_set_uart_rate,
551 .recalc = &omap1_uart_recalc,
554 static struct uart_clk uart3_16xx = {
558 /* Direct from ULPD, no real parent */
559 .parent = &armper_ck.clk,
561 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
562 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
563 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
566 .sysc_addr = 0xfffb9854,
569 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
571 .ops = &clkops_generic,
572 /* Direct from ULPD, no parent */
574 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
575 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
576 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
577 .enable_bit = USB_MCLK_EN_BIT,
580 static struct clk usb_hhc_ck1510 = {
581 .name = "usb_hhc_ck",
582 .ops = &clkops_generic,
583 /* Direct from ULPD, no parent */
584 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
585 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
586 RATE_FIXED | ENABLE_REG_32BIT,
587 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
588 .enable_bit = USB_HOST_HHC_UHOST_EN,
591 static struct clk usb_hhc_ck16xx = {
592 .name = "usb_hhc_ck",
593 .ops = &clkops_generic,
594 /* Direct from ULPD, no parent */
596 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
597 .flags = CLOCK_IN_OMAP16XX |
598 RATE_FIXED | ENABLE_REG_32BIT,
599 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
600 .enable_bit = 8 /* UHOST_EN */,
603 static struct clk usb_dc_ck = {
605 .ops = &clkops_generic,
606 /* Direct from ULPD, no parent */
608 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
609 .enable_reg = (void __iomem *)SOFT_REQ_REG,
613 static struct clk mclk_1510 = {
615 .ops = &clkops_generic,
616 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
618 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
619 .enable_reg = (void __iomem *)SOFT_REQ_REG,
623 static struct clk mclk_16xx = {
625 .ops = &clkops_generic,
626 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
627 .flags = CLOCK_IN_OMAP16XX,
628 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
629 .enable_bit = COM_ULPD_PLL_CLK_REQ,
630 .set_rate = &omap1_set_ext_clk_rate,
631 .round_rate = &omap1_round_ext_clk_rate,
632 .init = &omap1_init_ext_clk,
635 static struct clk bclk_1510 = {
637 .ops = &clkops_generic,
638 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
640 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
643 static struct clk bclk_16xx = {
645 .ops = &clkops_generic,
646 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
647 .flags = CLOCK_IN_OMAP16XX,
648 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
649 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
650 .set_rate = &omap1_set_ext_clk_rate,
651 .round_rate = &omap1_round_ext_clk_rate,
652 .init = &omap1_init_ext_clk,
655 static struct clk mmc1_ck = {
657 .ops = &clkops_generic,
658 /* Functional clock is direct from ULPD, interface clock is ARMPER */
659 .parent = &armper_ck.clk,
661 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
662 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
663 CLOCK_NO_IDLE_PARENT,
664 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
668 static struct clk mmc2_ck = {
671 .ops = &clkops_generic,
672 /* Functional clock is direct from ULPD, interface clock is ARMPER */
673 .parent = &armper_ck.clk,
675 .flags = CLOCK_IN_OMAP16XX |
676 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
677 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
681 static struct clk virtual_ck_mpu = {
683 .ops = &clkops_generic,
684 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
685 CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
686 .parent = &arm_ck, /* Is smarter alias for */
687 .recalc = &followparent_recalc,
688 .set_rate = &omap1_select_table_rate,
689 .round_rate = &omap1_round_to_table_rate,
692 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
693 remains active during MPU idle whenever this is enabled */
694 static struct clk i2c_fck = {
697 .ops = &clkops_generic,
698 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
699 CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED,
700 .parent = &armxor_ck.clk,
701 .recalc = &followparent_recalc,
704 static struct clk i2c_ick = {
707 .ops = &clkops_generic,
708 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
710 .parent = &armper_ck.clk,
711 .recalc = &followparent_recalc,
714 static struct clk * onchip_clks[] = {
715 /* non-ULPD clocks */
727 &arminth_ck1510, &arminth_ck16xx,
755 &usb_hhc_ck1510, &usb_hhc_ck16xx,
757 &mclk_1510, &mclk_16xx,
758 &bclk_1510, &bclk_16xx,