arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/plat-omap/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/pm.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/pm.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/sysfs.h>
  44 #include <linux/module.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48 #include <asm/atomic.h>
  49 #include <asm/mach/time.h>
  50 #include <asm/mach/irq.h>
  51 #include <asm/mach-types.h>
  52
  53 #include <asm/arch/irqs.h>
  54 #include <asm/arch/clock.h>
  55 #include <asm/arch/sram.h>
  56 #include <asm/arch/tc.h>
  57 #include <asm/arch/pm.h>
  58 #include <asm/arch/mux.h>
  59 #include <asm/arch/tps65010.h>
  60 #include <asm/arch/dma.h>
  61 #include <asm/arch/dsp_common.h>
  62 #include <asm/arch/dmtimer.h>
  63
  64 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  65 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  66 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
  67 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  68 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  69
  70 static unsigned short enable_dyn_sleep = 1;
  71
  72 static ssize_t omap_pm_sleep_while_idle_show(struct subsystem * subsys, char *buf)
  73 {
  74         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  75 }
  76
  77 static ssize_t omap_pm_sleep_while_idle_store(struct subsystem * subsys,
  78                                               const char * buf,
  79                                               size_t n)
  80 {
  81         unsigned short value;
  82         if (sscanf(buf, "%hu", &value) != 1 ||
  83             (value != 0 && value != 1)) {
  84                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  85                 return -EINVAL;
  86         }
  87         enable_dyn_sleep = value;
  88         return n;
  89 }
  90
  91 static struct subsys_attribute sleep_while_idle_attr = {
  92         .attr   = {
  93                 .name = __stringify(sleep_while_idle),
  94                 .mode = 0644,
  95         },
  96         .show   = omap_pm_sleep_while_idle_show,
  97         .store  = omap_pm_sleep_while_idle_store,
  98 };
  99
 100 extern struct subsystem power_subsys;
 101 static void (*omap_sram_idle)(void) = NULL;
 102 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 103
 104 /*
 105  * Let's power down on idle, but only if we are really
 106  * idle, because once we start down the path of
 107  * going idle we continue to do idle even if we get
 108  * a clock tick interrupt . .
 109  */
 110 void omap_pm_idle(void)
 111 {
 112         extern __u32 arm_idlect1_mask;
 113         __u32 use_idlect1 = arm_idlect1_mask;
 114 #ifndef CONFIG_OMAP_MPU_TIMER
 115         int do_sleep;
 116 #endif
 117
 118         local_irq_disable();
 119         local_fiq_disable();
 120         if (need_resched()) {
 121                 local_fiq_enable();
 122                 local_irq_enable();
 123                 return;
 124         }
 125
 126         /*
 127          * Since an interrupt may set up a timer, we don't want to
 128          * reprogram the hardware timer with interrupts enabled.
 129          * Re-enable interrupts only after returning from idle.
 130          */
 131         timer_dyn_reprogram();
 132
 133 #ifdef CONFIG_OMAP_MPU_TIMER
 134 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 135         use_idlect1 = use_idlect1 & ~(1 << 9);
 136 #else
 137
 138         do_sleep = 0;
 139         while (enable_dyn_sleep) {
 140                 extern int vbus_active;
 141
 142 #ifdef CONFIG_CBUS_TAHVO_USB
 143                 /* Clock requirements? */
 144                 if (vbus_active)
 145                         break;
 146 #endif
 147                 do_sleep = 1;
 148                 break;
 149         }
 150
 151 #ifdef CONFIG_OMAP_DM_TIMER
 152         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 153 #endif
 154
 155         if (omap_dma_running()) {
 156                 use_idlect1 &= ~(1 << 6);
 157                 if (omap_lcd_dma_ext_running())
 158                         use_idlect1 &= ~(1 << 12);
 159         }
 160
 161         /* We should be able to remove the do_sleep variable and multiple
 162          * tests above as soon as drivers, timer and DMA code have been fixed.
 163          * Even the sleep block count should become obsolete. */
 164         if ((use_idlect1 != ~0) || !do_sleep) {
 165
 166                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 167                 if (cpu_is_omap1510())
 168                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 169                 else
 170                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 171                 omap_writel(use_idlect1, ARM_IDLECT1);
 172                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 173                 omap_writel(saved_idlect1, ARM_IDLECT1);
 174
 175                 local_fiq_enable();
 176                 local_irq_enable();
 177                 return;
 178         }
 179         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 180                           omap_readl(ARM_IDLECT2));
 181 #endif
 182
 183         local_fiq_enable();
 184         local_irq_enable();
 185 }
 186
 187 /*
 188  * Configuration of the wakeup event is board specific. For the
 189  * moment we put it into this helper function. Later it may move
 190  * to board specific files.
 191  */
 192 static void omap_pm_wakeup_setup(void)
 193 {
 194         u32 level1_wake = 0;
 195         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 196
 197         /*
 198          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 199          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 200          * drivers must still separately call omap_set_gpio_wakeup() to
 201          * wake up to a GPIO interrupt.
 202          */
 203         if (cpu_is_omap730())
 204                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 205                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 206         else if (cpu_is_omap1510())
 207                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 208                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 209         else if (cpu_is_omap16xx())
 210                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 211                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 212
 213         omap_writel(~level1_wake, OMAP_IH1_MIR);
 214
 215         if (cpu_is_omap730()) {
 216                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 217                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 218                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 219                                 OMAP_IH2_1_MIR);
 220         } else if (cpu_is_omap1510()) {
 221                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 222                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 223         } else if (cpu_is_omap16xx()) {
 224                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 225                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 226
 227                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 228                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 229                             OMAP_IH2_1_MIR);
 230                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 231                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 232         }
 233
 234         /*  New IRQ agreement, recalculate in cascade order */
 235         omap_writel(1, OMAP_IH2_CONTROL);
 236         omap_writel(1, OMAP_IH1_CONTROL);
 237 }
 238
 239 void omap_pm_suspend(void)
 240 {
 241         unsigned long arg0 = 0, arg1 = 0;
 242
 243         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
 244
 245         omap_serial_wake_trigger(1);
 246
 247         if (machine_is_omap_osk()) {
 248                 /* Stop LED1 (D9) blink */
 249                 tps65010_set_led(LED1, OFF);
 250         }
 251
 252         omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 253
 254         /*
 255          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 256          */
 257
 258         local_irq_disable();
 259         local_fiq_disable();
 260
 261         /*
 262          * Step 2: save registers
 263          *
 264          * The omap is a strange/beautiful device. The caches, memory
 265          * and register state are preserved across power saves.
 266          * We have to save and restore very little register state to
 267          * idle the omap.
 268          *
 269          * Save interrupt, MPUI, ARM and UPLD control registers.
 270          */
 271
 272         if (cpu_is_omap730()) {
 273                 MPUI730_SAVE(OMAP_IH1_MIR);
 274                 MPUI730_SAVE(OMAP_IH2_0_MIR);
 275                 MPUI730_SAVE(OMAP_IH2_1_MIR);
 276                 MPUI730_SAVE(MPUI_CTRL);
 277                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 278                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 279                 MPUI730_SAVE(EMIFS_CONFIG);
 280                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 281
 282         } else if (cpu_is_omap1510()) {
 283                 MPUI1510_SAVE(OMAP_IH1_MIR);
 284                 MPUI1510_SAVE(OMAP_IH2_MIR);
 285                 MPUI1510_SAVE(MPUI_CTRL);
 286                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 287                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 288                 MPUI1510_SAVE(EMIFS_CONFIG);
 289                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 290         } else if (cpu_is_omap16xx()) {
 291                 MPUI1610_SAVE(OMAP_IH1_MIR);
 292                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 293                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 294                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 295                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 296                 MPUI1610_SAVE(MPUI_CTRL);
 297                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 298                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 299                 MPUI1610_SAVE(EMIFS_CONFIG);
 300                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 301         }
 302
 303         ARM_SAVE(ARM_CKCTL);
 304         ARM_SAVE(ARM_IDLECT1);
 305         ARM_SAVE(ARM_IDLECT2);
 306         if (!(cpu_is_omap1510()))
 307                 ARM_SAVE(ARM_IDLECT3);
 308         ARM_SAVE(ARM_EWUPCT);
 309         ARM_SAVE(ARM_RSTCT1);
 310         ARM_SAVE(ARM_RSTCT2);
 311         ARM_SAVE(ARM_SYSST);
 312         ULPD_SAVE(ULPD_CLOCK_CTRL);
 313         ULPD_SAVE(ULPD_STATUS_REQ);
 314
 315         /* (Step 3 removed - we now allow deep sleep by default) */
 316
 317         /*
 318          * Step 4: OMAP DSP Shutdown
 319          */
 320
 321         omap_dsp_pm_suspend();
 322
 323         /*
 324          * Step 5: Wakeup Event Setup
 325          */
 326
 327         omap_pm_wakeup_setup();
 328
 329         /*
 330          * Step 6: ARM and Traffic controller shutdown
 331          */
 332
 333         /* disable ARM watchdog */
 334         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 335         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 336
 337         /*
 338          * Step 6b: ARM and Traffic controller shutdown
 339          *
 340          * Step 6 continues here. Prepare jump to power management
 341          * assembly code in internal SRAM.
 342          *
 343          * Since the omap_cpu_suspend routine has been copied to
 344          * SRAM, we'll do an indirect procedure call to it and pass the
 345          * contents of arm_idlect1 and arm_idlect2 so it can restore
 346          * them when it wakes up and it will return.
 347          */
 348
 349         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 350         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 351
 352         /*
 353          * Step 6c: ARM and Traffic controller shutdown
 354          *
 355          * Jump to assembly code. The processor will stay there
 356          * until wake up.
 357          */
 358         omap_sram_suspend(arg0, arg1);
 359
 360         /*
 361          * If we are here, processor is woken up!
 362          */
 363
 364         /* Restore DSP clocks */
 365         omap_dsp_pm_resume();
 366
 367         /*
 368          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 369          */
 370
 371         if (!(cpu_is_omap1510()))
 372                 ARM_RESTORE(ARM_IDLECT3);
 373         ARM_RESTORE(ARM_CKCTL);
 374         ARM_RESTORE(ARM_EWUPCT);
 375         ARM_RESTORE(ARM_RSTCT1);
 376         ARM_RESTORE(ARM_RSTCT2);
 377         ARM_RESTORE(ARM_SYSST);
 378         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 379         ULPD_RESTORE(ULPD_STATUS_REQ);
 380
 381         if (cpu_is_omap730()) {
 382                 MPUI730_RESTORE(EMIFS_CONFIG);
 383                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 384                 MPUI730_RESTORE(OMAP_IH1_MIR);
 385                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
 386                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
 387         } else if (cpu_is_omap1510()) {
 388                 MPUI1510_RESTORE(MPUI_CTRL);
 389                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 390                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 391                 MPUI1510_RESTORE(EMIFS_CONFIG);
 392                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 393                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 394                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 395         } else if (cpu_is_omap16xx()) {
 396                 MPUI1610_RESTORE(MPUI_CTRL);
 397                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 398                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 399                 MPUI1610_RESTORE(EMIFS_CONFIG);
 400                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 401
 402                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 403                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 404                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 405                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 406                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 407         }
 408
 409         omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 410
 411         /*
 412          * Reenable interrupts
 413          */
 414
 415         local_irq_enable();
 416         local_fiq_enable();
 417
 418         omap_serial_wake_trigger(0);
 419
 420         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
 421
 422         if (machine_is_omap_osk()) {
 423                 /* Let LED1 (D9) blink again */
 424                 tps65010_set_led(LED1, BLINK);
 425         }
 426 }
 427
 428 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 429 static int g_read_completed;
 430
 431 /*
 432  * Read system PM registers for debugging
 433  */
 434 static int omap_pm_read_proc(
 435         char *page_buffer,
 436         char **my_first_byte,
 437         off_t virtual_start,
 438         int length,
 439         int *eof,
 440         void *data)
 441 {
 442         int my_buffer_offset = 0;
 443         char * const my_base = page_buffer;
 444
 445         ARM_SAVE(ARM_CKCTL);
 446         ARM_SAVE(ARM_IDLECT1);
 447         ARM_SAVE(ARM_IDLECT2);
 448         if (!(cpu_is_omap1510()))
 449                 ARM_SAVE(ARM_IDLECT3);
 450         ARM_SAVE(ARM_EWUPCT);
 451         ARM_SAVE(ARM_RSTCT1);
 452         ARM_SAVE(ARM_RSTCT2);
 453         ARM_SAVE(ARM_SYSST);
 454
 455         ULPD_SAVE(ULPD_IT_STATUS);
 456         ULPD_SAVE(ULPD_CLOCK_CTRL);
 457         ULPD_SAVE(ULPD_SOFT_REQ);
 458         ULPD_SAVE(ULPD_STATUS_REQ);
 459         ULPD_SAVE(ULPD_DPLL_CTRL);
 460         ULPD_SAVE(ULPD_POWER_CTRL);
 461
 462         if (cpu_is_omap730()) {
 463                 MPUI730_SAVE(MPUI_CTRL);
 464                 MPUI730_SAVE(MPUI_DSP_STATUS);
 465                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 466                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 467                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 468                 MPUI730_SAVE(EMIFS_CONFIG);
 469         } else if (cpu_is_omap1510()) {
 470                 MPUI1510_SAVE(MPUI_CTRL);
 471                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 472                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 473                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 474                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 475                 MPUI1510_SAVE(EMIFS_CONFIG);
 476         } else if (cpu_is_omap16xx()) {
 477                 MPUI1610_SAVE(MPUI_CTRL);
 478                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 479                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 480                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 481                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 482                 MPUI1610_SAVE(EMIFS_CONFIG);
 483         }
 484
 485         if (virtual_start == 0) {
 486                 g_read_completed = 0;
 487
 488                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 489                    "ARM_CKCTL_REG:            0x%-8x     \n"
 490                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 491                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 492                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 493                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 494                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 495                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 496                    "ARM_SYSST_REG:            0x%-8x     \n"
 497                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 498                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 499                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 500                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 501                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 502                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 503                    ARM_SHOW(ARM_CKCTL),
 504                    ARM_SHOW(ARM_IDLECT1),
 505                    ARM_SHOW(ARM_IDLECT2),
 506                    ARM_SHOW(ARM_IDLECT3),
 507                    ARM_SHOW(ARM_EWUPCT),
 508                    ARM_SHOW(ARM_RSTCT1),
 509                    ARM_SHOW(ARM_RSTCT2),
 510                    ARM_SHOW(ARM_SYSST),
 511                    ULPD_SHOW(ULPD_IT_STATUS),
 512                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 513                    ULPD_SHOW(ULPD_SOFT_REQ),
 514                    ULPD_SHOW(ULPD_DPLL_CTRL),
 515                    ULPD_SHOW(ULPD_STATUS_REQ),
 516                    ULPD_SHOW(ULPD_POWER_CTRL));
 517
 518                 if (cpu_is_omap730()) {
 519                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 520                            "MPUI730_CTRL_REG         0x%-8x \n"
 521                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 522                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 523                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 524                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 525                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 526                            MPUI730_SHOW(MPUI_CTRL),
 527                            MPUI730_SHOW(MPUI_DSP_STATUS),
 528                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 529                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 530                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 531                            MPUI730_SHOW(EMIFS_CONFIG));
 532                 } else if (cpu_is_omap1510()) {
 533                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 534                            "MPUI1510_CTRL_REG             0x%-8x \n"
 535                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 536                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 537                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 538                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 539                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 540                            MPUI1510_SHOW(MPUI_CTRL),
 541                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 542                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 543                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 544                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 545                            MPUI1510_SHOW(EMIFS_CONFIG));
 546                 } else if (cpu_is_omap16xx()) {
 547                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 548                            "MPUI1610_CTRL_REG             0x%-8x \n"
 549                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 550                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 551                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 552                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 553                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 554                            MPUI1610_SHOW(MPUI_CTRL),
 555                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 556                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 557                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 558                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 559                            MPUI1610_SHOW(EMIFS_CONFIG));
 560                 }
 561
 562                 g_read_completed++;
 563         } else if (g_read_completed >= 1) {
 564                  *eof = 1;
 565                  return 0;
 566         }
 567         g_read_completed++;
 568
 569         *my_first_byte = page_buffer;
 570         return  my_buffer_offset;
 571 }
 572
 573 static void omap_pm_init_proc(void)
 574 {
 575         struct proc_dir_entry *entry;
 576
 577         entry = create_proc_read_entry("driver/omap_pm",
 578                                        S_IWUSR | S_IRUGO, NULL,
 579                                        omap_pm_read_proc, NULL);
 580 }
 581
 582 #endif /* DEBUG && CONFIG_PROC_FS */
 583
 584 static void (*saved_idle)(void) = NULL;
 585
 586 /*
 587  *      omap_pm_prepare - Do preliminary suspend work.
 588  *      @state:         suspend state we're entering.
 589  *
 590  */
 591 static int omap_pm_prepare(suspend_state_t state)
 592 {
 593         int error = 0;
 594
 595         /* We cannot sleep in idle until we have resumed */
 596         saved_idle = pm_idle;
 597         pm_idle = NULL;
 598
 599         switch (state)
 600         {
 601         case PM_SUSPEND_STANDBY:
 602         case PM_SUSPEND_MEM:
 603                 break;
 604
 605         case PM_SUSPEND_DISK:
 606                 return -ENOTSUPP;
 607
 608         default:
 609                 return -EINVAL;
 610         }
 611
 612         return error;
 613 }
 614
 615
 616 /*
 617  *      omap_pm_enter - Actually enter a sleep state.
 618  *      @state:         State we're entering.
 619  *
 620  */
 621
 622 static int omap_pm_enter(suspend_state_t state)
 623 {
 624         switch (state)
 625         {
 626         case PM_SUSPEND_STANDBY:
 627         case PM_SUSPEND_MEM:
 628                 omap_pm_suspend();
 629                 break;
 630
 631         case PM_SUSPEND_DISK:
 632                 return -ENOTSUPP;
 633
 634         default:
 635                 return -EINVAL;
 636         }
 637
 638         return 0;
 639 }
 640
 641
 642 /**
 643  *      omap_pm_finish - Finish up suspend sequence.
 644  *      @state:         State we're coming out of.
 645  *
 646  *      This is called after we wake back up (or if entering the sleep state
 647  *      failed).
 648  */
 649
 650 static int omap_pm_finish(suspend_state_t state)
 651 {
 652         pm_idle = saved_idle;
 653         return 0;
 654 }
 655
 656
 657 static irqreturn_t  omap_wakeup_interrupt(int  irq, void *  dev,
 658                                      struct pt_regs *  regs)
 659 {
 660         return IRQ_HANDLED;
 661 }
 662
 663 static struct irqaction omap_wakeup_irq = {
 664         .name           = "peripheral wakeup",
 665         .flags          = SA_INTERRUPT,
 666         .handler        = omap_wakeup_interrupt
 667 };
 668
 669
 670
 671 static struct pm_ops omap_pm_ops ={
 672         .pm_disk_mode = 0,
 673         .prepare        = omap_pm_prepare,
 674         .enter          = omap_pm_enter,
 675         .finish         = omap_pm_finish,
 676 };
 677
 678 static int __init omap_pm_init(void)
 679 {
 680         printk("Power Management for TI OMAP.\n");
 681
 682         /*
 683          * We copy the assembler sleep/wakeup routines to SRAM.
 684          * These routines need to be in SRAM as that's the only
 685          * memory the MPU can see when it wakes up.
 686          */
 687         if (cpu_is_omap730()) {
 688                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
 689                                                 omap730_idle_loop_suspend_sz);
 690                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 691                                                    omap730_cpu_suspend_sz);
 692         } else if (cpu_is_omap1510()) {
 693                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
 694                                                 omap1510_idle_loop_suspend_sz);
 695                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 696                                                    omap1510_cpu_suspend_sz);
 697         } else if (cpu_is_omap16xx()) {
 698                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
 699                                                 omap1610_idle_loop_suspend_sz);
 700                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 701                                                    omap1610_cpu_suspend_sz);
 702         }
 703
 704         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
 705                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 706                 return -ENODEV;
 707         }
 708
 709         pm_idle = omap_pm_idle;
 710
 711         if (cpu_is_omap730())
 712                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 713         else if (cpu_is_omap16xx())
 714                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 715
 716 #if 0
 717         /* --- BEGIN BOARD-DEPENDENT CODE --- */
 718         /* Sleepx mask direction */
 719         omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
 720         /* Unmask sleepx signal */
 721         omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 722         /* --- END BOARD-DEPENDENT CODE --- */
 723 #endif
 724
 725         /* Program new power ramp-up time
 726          * (0 for most boards since we don't lower voltage when in deep sleep)
 727          */
 728         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 729
 730         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 731         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 732
 733         /* Configure IDLECT3 */
 734         if (cpu_is_omap730())
 735                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 736         else if (cpu_is_omap16xx())
 737                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 738
 739         pm_set_ops(&omap_pm_ops);
 740
 741 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 742         omap_pm_init_proc();
 743 #endif
 744
 745         subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 746
 747         if (cpu_is_omap16xx()) {
 748                 /* configure LOW_PWR pin */
 749                 omap_cfg_reg(T20_1610_LOW_PWR);
 750         }
 751
 752         return 0;
 753 }
 754 __initcall(omap_pm_init);