2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Cleaned up and modified to use omap shared clock framework by
9 * Tony Lindgren <tony@atomide.com>
11 * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
12 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/device.h>
21 #include <linux/list.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sram.h>
31 #include "prcm-regs.h"
35 //#define DOWN_VARIABLE_DPLL 1 /* Experimental */
37 static struct prcm_config *curr_prcm_set;
38 static u32 curr_perf_level = PRCM_FULL_SPEED;
39 static struct clk *vclk;
40 static struct clk *sclk;
42 /*-------------------------------------------------------------------------
43 * Omap2 specific clock functions
44 *-------------------------------------------------------------------------*/
46 /* Recalculate SYST_CLK */
47 static void omap2_sys_clk_recalc(struct clk * clk)
49 u32 div = PRCM_CLKSRC_CTRL;
50 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
51 div >>= clk->rate_offset;
52 clk->rate = (clk->parent->rate / div);
56 static u32 omap2_get_dpll_rate(struct clk * tclk)
59 int dpll_mult, dpll_div, amult;
61 dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
62 dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
63 dpll_clk = (long long)tclk->parent->rate * dpll_mult;
64 do_div(dpll_clk, dpll_div + 1);
65 amult = CM_CLKSEL2_PLL & 0x3;
71 static void omap2_followparent_recalc(struct clk *clk)
73 followparent_recalc(clk);
76 static void omap2_propagate_rate(struct clk * clk)
78 if (!(clk->flags & RATE_FIXED))
79 clk->rate = clk->parent->rate;
84 static void omap2_set_osc_ck(int enable)
87 PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
89 PRCM_CLKSRC_CTRL |= 0x3 << 3;
92 /* Enable an APLL if off */
93 static void omap2_clk_fixed_enable(struct clk *clk)
97 if (clk->enable_bit == 0xff) /* Parent will do it */
102 if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
105 cval &= ~(0x3 << clk->enable_bit);
106 cval |= (0x3 << clk->enable_bit);
109 if (clk == &apll96_ck)
111 else if (clk == &apll54_ck)
114 while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */
122 /* Enables clock without considering parent dependencies or use count
123 * REVISIT: Maybe change this to use clk->enable like on omap1?
125 static int _omap2_clk_enable(struct clk * clk)
129 if (clk->flags & ALWAYS_ENABLED)
132 if (unlikely(clk == &osc_ck)) {
137 if (unlikely(clk->enable_reg == 0)) {
138 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
143 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
144 omap2_clk_fixed_enable(clk);
148 regval32 = __raw_readl(clk->enable_reg);
149 regval32 |= (1 << clk->enable_bit);
150 __raw_writel(regval32, clk->enable_reg);
157 static void omap2_clk_fixed_disable(struct clk *clk)
161 if(clk->enable_bit == 0xff) /* let parent off do it */
165 cval &= ~(0x3 << clk->enable_bit);
169 /* Disables clock without considering parent dependencies or use count */
170 static void _omap2_clk_disable(struct clk *clk)
174 if (unlikely(clk == &osc_ck)) {
179 if (clk->enable_reg == 0)
182 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
183 omap2_clk_fixed_disable(clk);
187 regval32 = __raw_readl(clk->enable_reg);
188 regval32 &= ~(1 << clk->enable_bit);
189 __raw_writel(regval32, clk->enable_reg);
193 static int omap2_clk_enable(struct clk *clk)
197 if (clk->usecount++ == 0) {
198 if (likely((u32)clk->parent))
199 ret = omap2_clk_enable(clk->parent);
201 if (unlikely(ret != 0)) {
206 ret = _omap2_clk_enable(clk);
208 if (unlikely(ret != 0) && clk->parent) {
209 omap2_clk_disable(clk->parent);
217 static void omap2_clk_disable(struct clk *clk)
219 if (clk->usecount > 0 && !(--clk->usecount)) {
220 _omap2_clk_disable(clk);
221 if (likely((u32)clk->parent))
222 omap2_clk_disable(clk->parent);
227 * Uses the current prcm set to tell if a rate is valid.
228 * You can go slower, but not faster within a given rate set.
230 static u32 omap2_dpll_round_rate(unsigned long target_rate)
234 if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */
235 high = curr_prcm_set->dpll_speed * 2;
236 low = curr_prcm_set->dpll_speed;
237 } else { /* DPLL clockout x 2 */
238 high = curr_prcm_set->dpll_speed;
239 low = curr_prcm_set->dpll_speed / 2;
242 #ifdef DOWN_VARIABLE_DPLL
243 if (target_rate > high)
248 if (target_rate > low)
257 * Used for clocks that are part of CLKSEL_xyz governed clocks.
258 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
260 static void omap2_clksel_recalc(struct clk * clk)
262 u32 fixed = 0, div = 0;
264 if (clk == &dpll_ck) {
265 clk->rate = omap2_get_dpll_rate(clk);
270 if (clk == &iva1_mpu_int_ifck) {
275 if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
276 clk->rate = sys_ck.rate;
281 div = omap2_clksel_get_divisor(clk);
287 if (unlikely(clk->rate == clk->parent->rate / div))
289 clk->rate = clk->parent->rate / div;
292 if (unlikely(clk->flags & RATE_PROPAGATES))
297 * Finds best divider value in an array based on the source and target
298 * rates. The divider array must be sorted with smallest divider first.
300 static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
301 u32 src_rate, u32 tgt_rate)
305 if (div_array == NULL)
308 for (i=0; i < size; i++) {
309 test_rate = src_rate / *div_array;
310 if (test_rate <= tgt_rate)
315 return ~0; /* No acceptable divider */
319 * Find divisor for the given clock and target rate.
321 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
322 * they are only settable as part of virtual_prcm set.
324 static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
327 u32 gfx_div[] = {2, 3, 4};
328 u32 sysclkout_div[] = {1, 2, 4, 8, 16};
329 u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
330 u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
331 u32 best_div = ~0, asize = 0;
332 u32 *div_array = NULL;
334 switch (tclk->flags & SRC_RATE_SEL_MASK) {
340 return omap2_dpll_round_rate(target_rate);
341 case CM_SYSCLKOUT_SEL1:
343 div_array = sysclkout_div;
346 if(tclk == &dss1_fck){
347 if(tclk->parent == &core_ck){
349 div_array = dss1_div;
351 *new_div = 0; /* fixed clk */
352 return(tclk->parent->rate);
354 } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
355 if(tclk->parent == &core_ck){
357 div_array = vylnq_div;
359 *new_div = 0; /* fixed clk */
360 return(tclk->parent->rate);
366 best_div = omap2_divider_from_table(asize, div_array,
367 tclk->parent->rate, target_rate);
370 return best_div; /* signal error */
374 return (tclk->parent->rate / best_div);
377 /* Given a clock and a rate apply a clock specific rounding function */
378 static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
383 if (clk->flags & RATE_FIXED)
386 if (clk->flags & RATE_CKCTL) {
387 valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
391 if (clk->round_rate != 0)
392 return clk->round_rate(clk, rate);
398 * Check the DLL lock state, and return tue if running in unlock mode.
399 * This is needed to compenste for the shifted DLL value in unlock mode.
401 static u32 omap2_dll_force_needed(void)
403 u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */
405 if ((dll_state & (1 << 2)) == (1 << 2))
411 static u32 omap2_reprogram_sdrc(u32 level, u32 force)
413 u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
414 u32 prev = curr_perf_level, flags;
416 if ((curr_perf_level == level) && !force)
419 m_type = omap2_memory_get_type();
420 slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
421 fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
423 if (level == PRCM_HALF_SPEED) {
424 local_irq_save(flags);
425 PRCM_VOLTSETUP = 0xffff;
426 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
427 slow_dll_ctrl, m_type);
428 curr_perf_level = PRCM_HALF_SPEED;
429 local_irq_restore(flags);
431 if (level == PRCM_FULL_SPEED) {
432 local_irq_save(flags);
433 PRCM_VOLTSETUP = 0xffff;
434 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
435 fast_dll_ctrl, m_type);
436 curr_perf_level = PRCM_FULL_SPEED;
437 local_irq_restore(flags);
443 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
445 u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
447 struct prcm_config tmpset;
450 local_irq_save(flags);
451 cur_rate = omap2_get_dpll_rate(&dpll_ck);
452 mult = CM_CLKSEL2_PLL & 0x3;
454 if ((rate == (cur_rate / 2)) && (mult == 2)) {
455 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
456 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
457 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
458 } else if (rate != cur_rate) {
459 valid_rate = omap2_dpll_round_rate(rate);
460 if (valid_rate != rate)
463 if ((CM_CLKSEL2_PLL & 0x3) == 1)
464 low = curr_prcm_set->dpll_speed;
466 low = curr_prcm_set->dpll_speed / 2;
468 tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
469 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
470 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
471 tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
472 tmpset.cm_clksel2_pll &= ~0x3;
474 tmpset.cm_clksel2_pll |= 0x2;
475 mult = ((rate / 2) / 1000000);
476 done_rate = PRCM_FULL_SPEED;
478 tmpset.cm_clksel2_pll |= 0x1;
479 mult = (rate / 1000000);
480 done_rate = PRCM_HALF_SPEED;
482 tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
485 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
487 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
490 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
492 /* Force dll lock mode */
493 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
496 /* Errata: ret dll entry state */
497 omap2_init_memory_params(omap2_dll_force_needed());
498 omap2_reprogram_sdrc(done_rate, 0);
500 omap2_clksel_recalc(&dpll_ck);
504 local_irq_restore(flags);
508 /* Just return the MPU speed */
509 static void omap2_mpu_recalc(struct clk * clk)
511 clk->rate = curr_prcm_set->mpu_speed;
515 * Look for a rate equal or less than the target rate given a configuration set.
517 * What's not entirely clear is "which" field represents the key field.
518 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
519 * just uses the ARM rates.
521 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
523 struct prcm_config * ptr;
526 if (clk != &virt_prcm_set)
529 highest_rate = -EINVAL;
531 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
532 if (ptr->xtal_speed != sys_ck.rate)
535 highest_rate = ptr->mpu_speed;
537 /* Can check only after xtal frequency check */
538 if (ptr->mpu_speed <= rate)
545 * omap2_convert_field_to_div() - turn field value into integer divider
547 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
550 u32 clkout_array[] = {1, 2, 4, 8, 16};
552 if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
553 for (i = 0; i < 5; i++) {
555 return clkout_array[i];
563 * Returns the CLKSEL divider register value
564 * REVISIT: This should be cleaned up to work nicely with void __iomem *
566 static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
570 u32 reg_val, div_off;
574 div_off = clk->rate_offset;
576 switch ((*div_sel & SRC_RATE_SEL_MASK)) {
578 div_addr = (u32)&CM_CLKSEL_MPU;
582 div_addr = (u32)&CM_CLKSEL_DSP;
583 if (cpu_is_omap2420()) {
584 if ((div_off == 0) || (div_off == 8))
586 else if (div_off == 5)
588 } else if (cpu_is_omap2430()) {
591 else if (div_off == 5)
596 div_addr = (u32)&CM_CLKSEL_GFX;
601 div_addr = (u32)&CM_CLKSEL_MDM;
605 case CM_SYSCLKOUT_SEL1:
606 div_addr = (u32)&PRCM_CLKOUT_CTRL;
607 if ((div_off == 3) || (div_off = 11))
611 div_addr = (u32)&CM_CLKSEL1_CORE;
615 case 15: /* vylnc-2420 */
629 if (unlikely(mask == ~0))
634 if (unlikely(div_addr == 0))
638 reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
640 /* Normalize back to divider value */
647 * Return divider to be applied to parent clock.
650 static u32 omap2_clksel_get_divisor(struct clk *clk)
653 u32 div, div_sel, div_off, field_mask, field_val;
655 /* isolate control register */
656 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
658 div_off = clk->rate_offset;
659 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
663 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
664 div = omap2_clksel_to_divisor(div_sel, field_val);
669 /* Set the clock rate for a clock source */
670 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
675 u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
678 if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
680 return omap2_reprogram_dpll(clk, rate);
682 /* Isolate control register */
683 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
684 div_off = clk->rate_offset;
686 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
687 if (validrate != rate)
690 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
694 if (clk->flags & CM_SYSCLKOUT_SEL1) {
715 reg = (void __iomem *)div_sel;
717 reg_val = __raw_readl(reg);
718 reg_val &= ~(field_mask << div_off);
719 reg_val |= (field_val << div_off);
720 __raw_writel(reg_val, reg);
722 clk->rate = clk->parent->rate / field_val;
724 if (clk->flags & DELAYED_APP) {
725 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
729 } else if (clk->set_rate != 0)
730 ret = clk->set_rate(clk, rate);
732 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
738 /* Converts encoded control register address into a full address */
739 static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
740 struct clk *src_clk, u32 *field_mask)
742 u32 val = ~0, src_reg_addr = 0, mask = 0;
744 /* Find target control register.*/
745 switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
747 src_reg_addr = (u32)&CM_CLKSEL1_CORE;
748 if (reg_offset == 13) { /* DSS2_fclk */
750 if (src_clk == &sys_ck)
752 if (src_clk == &func_48m_ck)
754 } else if (reg_offset == 8) { /* DSS1_fclk */
756 if (src_clk == &sys_ck)
758 else if (src_clk == &core_ck) /* divided clock */
759 val = 0x10; /* rate needs fixing */
760 } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
762 if(src_clk == &func_96m_ck)
764 else if (src_clk == &core_ck)
769 src_reg_addr = (u32)&CM_CLKSEL2_CORE;
771 if (src_clk == &func_32k_ck)
773 if (src_clk == &sys_ck)
775 if (src_clk == &alt_ck)
779 src_reg_addr = (u32)&CM_CLKSEL_WKUP;
781 if (src_clk == &func_32k_ck)
783 if (src_clk == &sys_ck)
785 if (src_clk == &alt_ck)
789 src_reg_addr = (u32)&CM_CLKSEL1_PLL;
791 if (reg_offset == 0x3) {
792 if (src_clk == &apll96_ck)
794 if (src_clk == &alt_ck)
797 else if (reg_offset == 0x5) {
798 if (src_clk == &apll54_ck)
800 if (src_clk == &alt_ck)
805 src_reg_addr = (u32)&CM_CLKSEL2_PLL;
807 if (src_clk == &func_32k_ck)
809 if (src_clk == &dpll_ck)
812 case CM_SYSCLKOUT_SEL1:
813 src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
815 if (src_clk == &dpll_ck)
817 if (src_clk == &sys_ck)
819 if (src_clk == &func_96m_ck)
821 if (src_clk == &func_54m_ck)
826 if (val == ~0) /* Catch errors in offset */
829 *type_to_addr = src_reg_addr;
835 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
838 u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
841 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
844 if (clk->flags & SRC_SEL_MASK) { /* On-chip SEL collection */
845 src_sel = (SRC_RATE_SEL_MASK & clk->flags);
846 src_off = clk->src_offset;
849 goto set_parent_error;
851 field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
854 reg = (void __iomem *)src_sel;
856 if (clk->usecount > 0)
857 _omap2_clk_disable(clk);
859 /* Set new source value (previous dividers if any in effect) */
860 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
861 reg_val |= (field_val << src_off);
862 __raw_writel(reg_val, reg);
865 if (clk->flags & DELAYED_APP) {
866 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
869 if (clk->usecount > 0)
870 _omap2_clk_enable(clk);
872 clk->parent = new_parent;
874 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
875 if ((new_parent == &core_ck) && (clk == &dss1_fck))
876 clk->rate = new_parent->rate / 0x10;
878 clk->rate = new_parent->rate;
880 if (unlikely(clk->flags & RATE_PROPAGATES))
885 clk->parent = new_parent;
886 rate = new_parent->rate;
887 omap2_clk_set_rate(clk, rate);
895 /* Sets basic clocks based on the specified rate */
896 static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
898 u32 flags, cur_rate, done_rate, bypass = 0;
900 struct prcm_config *prcm;
901 unsigned long found_speed = 0;
903 if (clk != &virt_prcm_set)
906 /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */
907 if (cpu_is_omap2420())
908 cpu_mask = RATE_IN_242X;
909 else if (cpu_is_omap2430())
910 cpu_mask = RATE_IN_243X;
912 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
913 if (!(prcm->flags & cpu_mask))
916 if (prcm->xtal_speed != sys_ck.rate)
919 if (prcm->mpu_speed <= rate) {
920 found_speed = prcm->mpu_speed;
926 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
931 curr_prcm_set = prcm;
932 cur_rate = omap2_get_dpll_rate(&dpll_ck);
934 if (prcm->dpll_speed == cur_rate / 2) {
935 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
936 } else if (prcm->dpll_speed == cur_rate * 2) {
937 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
938 } else if (prcm->dpll_speed != cur_rate) {
939 local_irq_save(flags);
941 if (prcm->dpll_speed == prcm->xtal_speed)
944 if ((prcm->cm_clksel2_pll & 0x3) == 2)
945 done_rate = PRCM_FULL_SPEED;
947 done_rate = PRCM_HALF_SPEED;
950 CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
952 /* dsp + iva1 div(2420), iva2.1(2430) */
953 CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
955 CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
957 /* Major subsystem dividers */
958 CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
959 if (cpu_is_omap2430())
960 CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
962 /* x2 to enter init_mem */
963 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
965 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
968 omap2_init_memory_params(omap2_dll_force_needed());
969 omap2_reprogram_sdrc(done_rate, 0);
971 local_irq_restore(flags);
973 omap2_clksel_recalc(&dpll_ck);
978 /*-------------------------------------------------------------------------
979 * Omap2 clock reset and init functions
980 *-------------------------------------------------------------------------*/
982 #ifdef CONFIG_OMAP_RESET_CLOCKS
983 static void __init omap2_clk_disable_unused(struct clk *clk)
987 regval32 = __raw_readl(clk->enable_reg);
988 if ((regval32 & (1 << clk->enable_bit)) == 0)
991 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
992 _omap2_clk_disable(clk);
995 #define omap2_clk_disable_unused NULL
998 static struct clk_functions omap2_clk_functions = {
999 .clk_enable = omap2_clk_enable,
1000 .clk_disable = omap2_clk_disable,
1001 .clk_round_rate = omap2_clk_round_rate,
1002 .clk_set_rate = omap2_clk_set_rate,
1003 .clk_set_parent = omap2_clk_set_parent,
1004 .clk_disable_unused = omap2_clk_disable_unused,
1007 static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
1009 u32 div, aplls, sclk = 13000000;
1011 aplls = CM_CLKSEL1_PLL;
1012 aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
1013 aplls >>= 23; /* Isolate field, 0,2,3 */
1017 else if (aplls == 2)
1019 else if (aplls == 3)
1022 div = PRCM_CLKSRC_CTRL;
1023 div &= ((1 << 7) | (1 << 6));
1024 div >>= sys->rate_offset;
1026 osc->rate = sclk * div;
1031 * Set clocks for bypass mode for reboot to work.
1033 void omap2_clk_prepare_for_reboot(void)
1037 if (vclk == NULL || sclk == NULL)
1040 rate = clk_get_rate(sclk);
1041 clk_set_rate(vclk, rate);
1045 * Switch the MPU rate if specified on cmdline.
1046 * We cannot do this early until cmdline is parsed.
1048 static int __init omap2_clk_arch_init(void)
1053 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
1054 printk(KERN_ERR "Could not find matching MPU rate\n");
1056 propagate_rate(&osc_ck); /* update main root fast */
1057 propagate_rate(&func_32k_ck); /* update main root slow */
1059 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
1060 "%ld.%01ld/%ld/%ld MHz\n",
1061 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1062 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1066 arch_initcall(omap2_clk_arch_init);
1068 int __init omap2_clk_init(void)
1070 struct prcm_config *prcm;
1074 clk_init(&omap2_clk_functions);
1075 omap2_get_crystal_rate(&osc_ck, &sys_ck);
1077 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
1080 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
1081 clk_register(*clkp);
1085 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
1086 clk_register(*clkp);
1091 /* Check the MPU rate set by bootloader */
1092 clkrate = omap2_get_dpll_rate(&dpll_ck);
1093 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1094 if (prcm->xtal_speed != sys_ck.rate)
1096 if (prcm->dpll_speed <= clkrate)
1099 curr_prcm_set = prcm;
1101 propagate_rate(&osc_ck); /* update main root fast */
1102 propagate_rate(&func_32k_ck); /* update main root slow */
1104 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
1105 "%ld.%01ld/%ld/%ld MHz\n",
1106 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1107 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1110 * Only enable those clocks we will need, let the drivers
1111 * enable other clocks as necessary
1113 clk_enable(&sync_32k_ick);
1114 clk_enable(&omapctrl_ick);
1115 if (cpu_is_omap2430())
1116 clk_enable(&sdrc_ick);
1118 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1119 vclk = clk_get(NULL, "virt_prcm_set");
1120 sclk = clk_get(NULL, "sys_ck");