2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Cleaned up and modified to use omap shared clock framework by
9 * Tony Lindgren <tony@atomide.com>
11 * Copyright (C) 2007 Texas Instruments, Inc.
12 * Copyright (C) 2007 Nokia Corporation
15 * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
16 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/device.h>
27 #include <linux/list.h>
28 #include <linux/errno.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/sram.h>
36 #include <asm/arch/cpu.h>
37 #include <asm/div64.h>
43 #include "prm_regbits_24xx.h"
45 #include "cm-regbits-24xx.h"
46 #include "cm_regbits_34xx.h"
48 #define MAX_CLOCK_ENABLE_WAIT 100000
52 /*-------------------------------------------------------------------------
53 * Omap2 specific clock functions
54 *-------------------------------------------------------------------------*/
56 u8 mask_to_shift(u32 mask)
62 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
63 * @clk: OMAP clock struct ptr to use
65 * Given a pointer to a source-selectable struct clk, read the hardware
66 * register and determine what its parent is currently set to. Update the
67 * clk->parent field with the appropriate clk ptr.
69 void omap2_init_clksel_parent(struct clk *clk)
71 const struct clksel *clks;
72 const struct clksel_rate *clkr;
78 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
79 r >>= mask_to_shift(clk->clksel_mask);
81 for (clks = clk->clksel; clks->parent && !found; clks++) {
82 for (clkr = clks->rates; clkr->div && !found; clkr++) {
83 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
84 if (clk->parent != clks->parent) {
85 pr_debug("clock: inited %s parent "
87 clk->name, clks->parent->name,
89 clk->parent->name : "NULL"));
90 clk->parent = clks->parent;
98 printk(KERN_ERR "clock: init parent: could not find "
99 "regval %0x for clock %s\n", r, clk->name);
104 /* Returns the DPLL rate */
105 u32 omap2_get_dpll_rate(struct clk *clk)
108 u32 dpll_mult, dpll_div, dpll;
109 const struct dpll_data *dd;
112 /* REVISIT: What do we return on error? */
116 dpll = cm_read_reg(dd->mult_div1_reg);
117 dpll_mult = dpll & dd->mult_mask;
118 dpll_mult >>= mask_to_shift(dd->mult_mask);
119 dpll_div = dpll & dd->div1_mask;
120 dpll_div >>= mask_to_shift(dd->div1_mask);
122 dpll_clk = (long long)clk->parent->rate * dpll_mult;
123 do_div(dpll_clk, dpll_div + 1);
127 dpll = cm_read_reg(dd->div2_reg);
128 dpll_div = dpll & dd->div2_mask;
129 dpll_div >>= mask_to_shift(dd->div2_mask);
130 do_div(dpll_clk, dpll_div + 1);
137 * Used for clocks that have the same value as the parent clock,
138 * divided by some factor
140 void omap2_fixed_divisor_recalc(struct clk *clk)
142 WARN_ON(!clk->fixed_div);
144 clk->rate = clk->parent->rate / clk->fixed_div;
146 if (clk->flags & RATE_PROPAGATES)
151 * omap2_wait_clock_ready - wait for clock to enable
152 * @reg: physical address of clock IDLEST register
153 * @mask: value to mask against to determine if the clock is active
154 * @name: name of the clock (for printk)
156 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
157 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
159 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
165 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
166 * 34xx reverses this, just to keep us on our toes
168 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
170 } else if (cpu_mask & RATE_IN_343X) {
175 while (((cm_read_reg(reg) & mask) != ena) &&
176 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
180 if (i < MAX_CLOCK_ENABLE_WAIT)
181 pr_debug("Clock %s stable after %d loops\n", name, i);
183 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
184 name, MAX_CLOCK_ENABLE_WAIT);
187 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
192 * Note: We don't need special code here for INVERT_ENABLE
193 * for the time being since INVERT_ENABLE only applies to clocks enabled by
196 static void omap2_clk_wait_ready(struct clk *clk)
198 void __iomem *reg, *other_reg, *st_reg;
202 * REVISIT: This code is pretty ugly. It would be nice to generalize
203 * it and pull it into struct clk itself somehow.
205 reg = clk->enable_reg;
206 if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
207 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
208 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
209 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
210 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
211 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
215 /* REVISIT: What are the appropriate exclusions for 34XX? */
216 /* No check for DSS or cam clocks */
217 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
218 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
219 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
220 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
224 /* REVISIT: What are the appropriate exclusions for 34XX? */
225 /* OMAP3: ignore DSS-mod clocks */
226 if (cpu_is_omap34xx() &&
227 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
230 /* Check if both functional and interface clocks
232 bit = 1 << clk->enable_bit;
233 if (!(cm_read_reg(other_reg) & bit))
235 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
237 omap2_wait_clock_ready(st_reg, bit, clk->name);
240 /* Enables clock without considering parent dependencies or use count
241 * REVISIT: Maybe change this to use clk->enable like on omap1?
243 int _omap2_clk_enable(struct clk *clk)
247 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
251 return clk->enable(clk);
253 if (unlikely(clk->enable_reg == 0)) {
254 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
256 return 0; /* REVISIT: -EINVAL */
259 regval32 = cm_read_reg(clk->enable_reg);
260 if (clk->flags & INVERT_ENABLE)
261 regval32 &= ~(1 << clk->enable_bit);
263 regval32 |= (1 << clk->enable_bit);
264 cm_write_reg(regval32, clk->enable_reg);
267 omap2_clk_wait_ready(clk);
272 /* Disables clock without considering parent dependencies or use count */
273 void _omap2_clk_disable(struct clk *clk)
277 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
285 if (clk->enable_reg == 0) {
287 * 'Independent' here refers to a clock which is not
288 * controlled by its parent.
290 printk(KERN_ERR "clock: clk_disable called on independent "
291 "clock %s which has no enable_reg\n", clk->name);
295 regval32 = cm_read_reg(clk->enable_reg);
296 if (clk->flags & INVERT_ENABLE)
297 regval32 |= (1 << clk->enable_bit);
299 regval32 &= ~(1 << clk->enable_bit);
300 cm_write_reg(regval32, clk->enable_reg);
304 void omap2_clk_disable(struct clk *clk)
306 if (clk->usecount > 0 && !(--clk->usecount)) {
307 _omap2_clk_disable(clk);
308 if (likely((u32)clk->parent))
309 omap2_clk_disable(clk->parent);
313 int omap2_clk_enable(struct clk *clk)
317 if (clk->usecount++ == 0) {
318 if (likely((u32)clk->parent))
319 ret = omap2_clk_enable(clk->parent);
321 if (unlikely(ret != 0)) {
326 ret = _omap2_clk_enable(clk);
328 if (unlikely(ret != 0) && clk->parent) {
329 omap2_clk_disable(clk->parent);
338 * Used for clocks that are part of CLKSEL_xyz governed clocks.
339 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
341 void omap2_clksel_recalc(struct clk *clk)
345 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
347 div = omap2_clksel_get_divisor(clk);
351 if (unlikely(clk->rate == clk->parent->rate / div))
353 clk->rate = clk->parent->rate / div;
355 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
357 if (unlikely(clk->flags & RATE_PROPAGATES))
362 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
363 * @clk: OMAP struct clk ptr to inspect
364 * @src_clk: OMAP struct clk ptr of the parent clk to search for
366 * Scan the struct clksel array associated with the clock to find
367 * the element associated with the supplied parent clock address.
368 * Returns a pointer to the struct clksel on success or NULL on error.
370 const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
373 const struct clksel *clks;
378 for (clks = clk->clksel; clks->parent; clks++) {
379 if (clks->parent == src_clk)
380 break; /* Found the requested parent */
384 printk(KERN_ERR "clock: Could not find parent clock %s in "
385 "clksel array of clock %s\n", src_clk->name,
394 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
395 * @clk: OMAP struct clk to use
396 * @target_rate: desired clock rate
397 * @new_div: ptr to where we should store the divisor
399 * Finds 'best' divider value in an array based on the source and target
400 * rates. The divider array must be sorted with smallest divider first.
401 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
402 * they are only settable as part of virtual_prcm set.
404 * Returns the rounded clock rate or returns 0xffffffff on error.
406 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
409 unsigned long test_rate;
410 const struct clksel *clks;
411 const struct clksel_rate *clkr;
414 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
415 clk->name, target_rate);
419 clks = omap2_get_clksel_by_parent(clk, clk->parent);
423 for (clkr = clks->rates; clkr->div; clkr++) {
424 if (!(clkr->flags & cpu_mask))
428 if (clkr->div <= last_div)
429 printk(KERN_ERR "clock: clksel_rate table not sorted "
430 "for clock %s", clk->name);
432 last_div = clkr->div;
434 test_rate = clk->parent->rate / clkr->div;
436 if (test_rate <= target_rate)
437 break; /* found it */
441 printk(KERN_ERR "clock: Could not find divisor for target "
442 "rate %ld for clock %s parent %s\n", target_rate,
443 clk->name, clk->parent->name);
447 *new_div = clkr->div;
449 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
450 (clk->parent->rate / clkr->div));
452 return (clk->parent->rate / clkr->div);
456 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
457 * @clk: OMAP struct clk to use
458 * @target_rate: desired clock rate
460 * Compatibility wrapper for OMAP clock framework
461 * Finds best target rate based on the source clock and possible dividers.
462 * rates. The divider array must be sorted with smallest divider first.
463 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
464 * they are only settable as part of virtual_prcm set.
466 * Returns the rounded clock rate or returns 0xffffffff on error.
468 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
472 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
476 /* Given a clock and a rate apply a clock specific rounding function */
477 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
479 if (clk->round_rate != 0)
480 return clk->round_rate(clk, rate);
482 if (clk->flags & RATE_FIXED)
483 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
484 "on fixed-rate clock %s\n", clk->name);
490 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
491 * @clk: OMAP struct clk to use
492 * @field_val: register field value to find
494 * Given a struct clk of a rate-selectable clksel clock, and a register field
495 * value to search for, find the corresponding clock divisor. The register
496 * field value should be pre-masked and shifted down so the LSB is at bit 0
497 * before calling. Returns 0 on error
499 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
501 const struct clksel *clks;
502 const struct clksel_rate *clkr;
504 clks = omap2_get_clksel_by_parent(clk, clk->parent);
508 for (clkr = clks->rates; clkr->div; clkr++) {
509 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
514 printk(KERN_ERR "clock: Could not find fieldval %d for "
515 "clock %s parent %s\n", field_val, clk->name,
524 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
525 * @clk: OMAP struct clk to use
526 * @div: integer divisor to search for
528 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
529 * find the corresponding register field value. The return register value is
530 * the value before left-shifting. Returns 0xffffffff on error
532 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
534 const struct clksel *clks;
535 const struct clksel_rate *clkr;
537 /* should never happen */
540 clks = omap2_get_clksel_by_parent(clk, clk->parent);
544 for (clkr = clks->rates; clkr->div; clkr++) {
545 if ((clkr->flags & cpu_mask) && (clkr->div == div))
550 printk(KERN_ERR "clock: Could not find divisor %d for "
551 "clock %s parent %s\n", div, clk->name,
560 * omap2_get_clksel - find clksel register addr & field mask for a clk
561 * @clk: struct clk to use
562 * @field_mask: ptr to u32 to store the register field mask
564 * Returns the address of the clksel register upon success or NULL on error.
566 void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
568 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
571 *field_mask = clk->clksel_mask;
573 return clk->clksel_reg;
577 * omap2_clksel_get_divisor - get current divider applied to parent clock.
578 * @clk: OMAP struct clk to use.
580 * Returns the integer divisor upon success or 0 on error.
582 u32 omap2_clksel_get_divisor(struct clk *clk)
584 u32 field_mask, field_val;
585 void __iomem *div_addr;
587 div_addr = omap2_get_clksel(clk, &field_mask);
591 field_val = cm_read_reg(div_addr) & field_mask;
592 field_val >>= mask_to_shift(field_mask);
594 return omap2_clksel_to_divisor(clk, field_val);
597 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
599 u32 field_mask, field_val, reg_val, validrate, new_div = 0;
600 void __iomem *div_addr;
602 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
603 if (validrate != rate)
606 div_addr = omap2_get_clksel(clk, &field_mask);
610 field_val = omap2_divisor_to_clksel(clk, new_div);
614 reg_val = cm_read_reg(div_addr);
615 reg_val &= ~field_mask;
616 reg_val |= (field_val << mask_to_shift(field_mask));
617 cm_write_reg(reg_val, div_addr);
620 clk->rate = clk->parent->rate / new_div;
622 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
623 prm_write_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
631 /* Set the clock rate for a clock source */
632 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
636 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
638 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
639 rate table mechanism, driven by mpu_speed */
640 if (clk->flags & CONFIG_PARTICIPANT)
643 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
644 if (clk->set_rate != 0)
645 ret = clk->set_rate(clk, rate);
647 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
654 * Converts encoded control register address into a full address
655 * On error, *src_addr will be returned as 0.
657 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
658 struct clk *src_clk, u32 *field_mask,
659 struct clk *clk, u32 *parent_div)
661 const struct clksel *clks;
662 const struct clksel_rate *clkr;
667 clks = omap2_get_clksel_by_parent(clk, src_clk);
671 for (clkr = clks->rates; clkr->div; clkr++) {
672 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
673 break; /* Found the default rate for this platform */
677 printk(KERN_ERR "clock: Could not find default rate for "
678 "clock %s parent %s\n", clk->name,
679 src_clk->parent->name);
683 /* Should never happen. Add a clksel mask to the struct clk. */
684 WARN_ON(clk->clksel_mask == 0);
686 *field_mask = clk->clksel_mask;
687 *src_addr = clk->clksel_reg;
688 *parent_div = clkr->div;
693 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
695 void __iomem *src_addr;
696 u32 field_val, field_mask, reg_val, parent_div;
698 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
704 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
705 &field_mask, clk, &parent_div);
709 if (clk->usecount > 0)
710 _omap2_clk_disable(clk);
712 /* Set new source value (previous dividers if any in effect) */
713 reg_val = __raw_readl(src_addr) & ~field_mask;
714 reg_val |= (field_val << mask_to_shift(field_mask));
715 __raw_writel(reg_val, src_addr);
718 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
719 prm_write_reg(OMAP24XX_VALID_CONFIG,
720 OMAP24XX_PRCM_CLKCFG_CTRL);
724 if (clk->usecount > 0)
725 _omap2_clk_enable(clk);
727 clk->parent = new_parent;
729 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
730 clk->rate = new_parent->rate;
733 clk->rate /= parent_div;
735 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
736 clk->name, clk->parent->name, clk->rate);
738 if (unlikely(clk->flags & RATE_PROPAGATES))
744 /*-------------------------------------------------------------------------
745 * Omap2 clock reset and init functions
746 *-------------------------------------------------------------------------*/
748 #ifdef CONFIG_OMAP_RESET_CLOCKS
749 void omap2_clk_disable_unused(struct clk *clk)
753 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
755 regval32 = cm_read_reg(clk->enable_reg);
756 if ((regval32 & (1 << clk->enable_bit)) == v)
759 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
760 _omap2_clk_disable(clk);