arch/arm/mach-omap2/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Cleaned up and modified to use omap shared clock framework by
   9  *  Tony Lindgren <tony@atomide.com>
  10  *
  11  *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
  12  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/device.h>
  21 #include <linux/list.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <asm/io.h>
  27
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/sram.h>
  30 #include <asm/div64.h>
  31
  32 #include "memory.h"
  33 #include "clock.h"
  34 #include "prm.h"
  35 #include "prm_regbits_24xx.h"
  36 #include "cm.h"
  37 #include "cm_regbits_24xx.h"
  38 #include "sdrc.h"
  39
  40 #undef DEBUG
  41
  42 /* SET_PERFORMANCE_LEVEL PARAMETERS */
  43 #define PRCM_HALF_SPEED         1
  44 #define PRCM_FULL_SPEED         2
  45
  46 //#define DOWN_VARIABLE_DPLL 1                  /* Experimental */
  47
  48 static struct prcm_config *curr_prcm_set;
  49 static u32 curr_perf_level = PRCM_FULL_SPEED;
  50 static struct clk *vclk;
  51 static struct clk *sclk;
  52
  53 /*-------------------------------------------------------------------------
  54  * Omap2 specific clock functions
  55  *-------------------------------------------------------------------------*/
  56
  57 /* Recalculate SYST_CLK */
  58 static void omap2_sys_clk_recalc(struct clk * clk)
  59 {
  60         u32 div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
  61         /* Test if ext clk divided by 1 or 2 */
  62         div &= (0x3 << OMAP_SYSCLKDIV_SHIFT);
  63         div >>= clk->rate_offset;
  64         clk->rate = (clk->parent->rate / div);
  65         propagate_rate(clk);
  66 }
  67
  68 static u32 omap2_get_dpll_rate(struct clk * tclk)
  69 {
  70         long long dpll_clk;
  71         int dpll_mult, dpll_div, amult;
  72         u32 dpll;
  73
  74         dpll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
  75
  76         dpll_mult = dpll & OMAP24XX_DPLL_MULT_MASK;
  77         dpll_mult >>= OMAP24XX_DPLL_MULT_SHIFT;         /* 10 bits */
  78         dpll_div = dpll & OMAP24XX_DPLL_DIV_MASK;
  79         dpll_div >>= OMAP24XX_DPLL_DIV_SHIFT;           /* 4 bits */
  80         dpll_clk = (long long)tclk->parent->rate * dpll_mult;
  81         do_div(dpll_clk, dpll_div + 1);
  82         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
  83         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
  84         dpll_clk *= amult;
  85
  86         return dpll_clk;
  87 }
  88
  89 static void omap2_followparent_recalc(struct clk *clk)
  90 {
  91         followparent_recalc(clk);
  92 }
  93
  94 static void omap2_propagate_rate(struct clk * clk)
  95 {
  96         if (!(clk->flags & RATE_FIXED))
  97                 clk->rate = clk->parent->rate;
  98
  99         propagate_rate(clk);
 100 }
 101
 102 static void omap2_set_osc_ck(int enable)
 103 {
 104         u32 pcc;
 105
 106         pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
 107
 108         if (enable)
 109                 prm_write_reg(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
 110                               OMAP24XX_PRCM_CLKSRC_CTRL);
 111         else
 112                 prm_write_reg(pcc | OMAP_AUTOEXTCLKMODE_MASK,
 113                               OMAP24XX_PRCM_CLKSRC_CTRL);
 114 }
 115
 116 /* Enable an APLL if off */
 117 static void omap2_clk_fixed_enable(struct clk *clk)
 118 {
 119         u32 cval, i=0;
 120
 121         if (clk->enable_bit == PARENT_CONTROLS_CLOCK)   /* Parent will do it */
 122                 return;
 123
 124         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 125
 126         if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
 127                 return;
 128
 129         cval &= ~(0x3 << clk->enable_bit);
 130         cval |= (0x3 << clk->enable_bit);
 131         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 132
 133         if (clk == &apll96_ck)
 134                 cval = OMAP24XX_ST_96M_APLL;
 135         else if (clk == &apll54_ck)
 136                 cval = OMAP24XX_ST_54M_CLK;
 137
 138         /* Wait for lock */
 139         while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST) & cval)) {
 140                 ++i;
 141                 udelay(1);
 142                 if (i == 100000) {
 143                         printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
 144                         break;
 145                 }
 146         }
 147 }
 148
 149 static void omap2_clk_wait_ready(struct clk *clk)
 150 {
 151         unsigned long reg, other_reg, st_reg;
 152         u32 bit;
 153         int i;
 154
 155         reg = (unsigned long) clk->enable_reg;
 156         if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1) ||
 157             reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2))
 158                 other_reg = (reg & ~0xf0) | 0x10; /* CM_ICLKEN* */
 159         else if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1) ||
 160                  reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2))
 161                 other_reg = (reg & ~0xf0) | 0x00; /* CM_FCLKEN* */
 162         else
 163                 return;
 164
 165         /* No check for DSS or cam clocks */
 166         if ((reg & 0x0f) == 0) {
 167                 if (clk->enable_bit <= 1 || clk->enable_bit == 31)
 168                         return;
 169         }
 170
 171         /* Check if both functional and interface clocks
 172          * are running. */
 173         bit = 1 << clk->enable_bit;
 174         if (!(cm_read_reg((void __iomem *)other_reg) & bit))
 175                 return;
 176         st_reg = (other_reg & ~0xf0) | 0x20; /* CM_IDLEST* */
 177         i = 0;
 178         while (!(cm_read_reg((void __iomem *)st_reg) & bit)) {
 179                 i++;
 180                 if (i == 100000) {
 181                         printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
 182                         break;
 183                 }
 184         }
 185         if (i)
 186                 pr_debug("Clock %s stable after %d loops\n", clk->name, i);
 187 }
 188
 189 /* Enables clock without considering parent dependencies or use count
 190  * REVISIT: Maybe change this to use clk->enable like on omap1?
 191  */
 192 static int _omap2_clk_enable(struct clk * clk)
 193 {
 194         u32 regval32;
 195
 196         if (clk->flags & ALWAYS_ENABLED)
 197                 return 0;
 198
 199         if (unlikely(clk == &osc_ck)) {
 200                 omap2_set_osc_ck(1);
 201                 return 0;
 202         }
 203
 204         if (unlikely(clk->enable_reg == 0)) {
 205                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 206                        clk->name);
 207                 return 0;
 208         }
 209
 210         if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 211                 omap2_clk_fixed_enable(clk);
 212                 return 0;
 213         }
 214
 215         regval32 = cm_read_reg(clk->enable_reg);
 216         regval32 |= (1 << clk->enable_bit);
 217         cm_write_reg(regval32, clk->enable_reg);
 218         wmb();
 219
 220         omap2_clk_wait_ready(clk);
 221
 222         return 0;
 223 }
 224
 225 /* Stop APLL */
 226 static void omap2_clk_fixed_disable(struct clk *clk)
 227 {
 228         u32 cval;
 229
 230         if (clk->enable_bit == PARENT_CONTROLS_CLOCK)
 231                 return;         /* let parent off do it */
 232
 233         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 234         cval &= ~(0x3 << clk->enable_bit);
 235         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 236 }
 237
 238 /* Disables clock without considering parent dependencies or use count */
 239 static void _omap2_clk_disable(struct clk *clk)
 240 {
 241         u32 regval32;
 242
 243         if (unlikely(clk == &osc_ck)) {
 244                 omap2_set_osc_ck(0);
 245                 return;
 246         }
 247
 248         if (clk->enable_reg == 0)
 249                 return;
 250
 251         if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 252                 omap2_clk_fixed_disable(clk);
 253                 return;
 254         }
 255
 256         regval32 = cm_read_reg(clk->enable_reg);
 257         regval32 &= ~(1 << clk->enable_bit);
 258         cm_write_reg(regval32, clk->enable_reg);
 259         wmb();
 260 }
 261
 262 static int omap2_clk_enable(struct clk *clk)
 263 {
 264         int ret = 0;
 265
 266         if (clk->usecount++ == 0) {
 267                 if (likely((u32)clk->parent))
 268                         ret = omap2_clk_enable(clk->parent);
 269
 270                 if (unlikely(ret != 0)) {
 271                         clk->usecount--;
 272                         return ret;
 273                 }
 274
 275                 ret = _omap2_clk_enable(clk);
 276
 277                 if (unlikely(ret != 0) && clk->parent) {
 278                         omap2_clk_disable(clk->parent);
 279                         clk->usecount--;
 280                 }
 281         }
 282
 283         return ret;
 284 }
 285
 286 static void omap2_clk_disable(struct clk *clk)
 287 {
 288         if (clk->usecount > 0 && !(--clk->usecount)) {
 289                 _omap2_clk_disable(clk);
 290                 if (likely((u32)clk->parent))
 291                         omap2_clk_disable(clk->parent);
 292         }
 293 }
 294
 295 /*
 296  * Uses the current prcm set to tell if a rate is valid.
 297  * You can go slower, but not faster within a given rate set.
 298  */
 299 static u32 omap2_dpll_round_rate(unsigned long target_rate)
 300 {
 301         u32 high, low, core_clk_src;
 302
 303         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 304         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 305
 306         if (core_clk_src == 1) {        /* DPLL clockout */
 307                 high = curr_prcm_set->dpll_speed * 2;
 308                 low = curr_prcm_set->dpll_speed;
 309         } else {                                /* DPLL clockout x 2 */
 310                 high = curr_prcm_set->dpll_speed;
 311                 low = curr_prcm_set->dpll_speed / 2;
 312         }
 313
 314 #ifdef DOWN_VARIABLE_DPLL
 315         if (target_rate > high)
 316                 return high;
 317         else
 318                 return target_rate;
 319 #else
 320         if (target_rate > low)
 321                 return high;
 322         else
 323                 return low;
 324 #endif
 325
 326 }
 327
 328 /*
 329  * Used for clocks that are part of CLKSEL_xyz governed clocks.
 330  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
 331  */
 332 static void omap2_clksel_recalc(struct clk * clk)
 333 {
 334         u32 fixed = 0, div = 0;
 335         u32 clksel1_core;
 336
 337         if (clk == &dpll_ck) {
 338                 clk->rate = omap2_get_dpll_rate(clk);
 339                 fixed = 1;
 340                 div = 0;
 341         }
 342
 343         if (clk == &iva1_mpu_int_ifck) {
 344                 div = 2;
 345                 fixed = 1;
 346         }
 347
 348         clksel1_core = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1);
 349
 350         if ((clk == &dss1_fck) &&
 351             (clksel1_core & OMAP24XX_CLKSEL_DSS1_MASK) == 0) {
 352                 clk->rate = sys_ck.rate;
 353                 return;
 354         }
 355
 356         if (!fixed) {
 357                 div = omap2_clksel_get_divisor(clk);
 358                 if (div == 0)
 359                         return;
 360         }
 361
 362         if (div != 0) {
 363                 if (unlikely(clk->rate == clk->parent->rate / div))
 364                         return;
 365                 clk->rate = clk->parent->rate / div;
 366         }
 367
 368         if (unlikely(clk->flags & RATE_PROPAGATES))
 369                 propagate_rate(clk);
 370 }
 371
 372 /*
 373  * Finds best divider value in an array based on the source and target
 374  * rates. The divider array must be sorted with smallest divider first.
 375  */
 376 static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
 377                                            u32 src_rate, u32 tgt_rate)
 378 {
 379         int i, test_rate;
 380
 381         if (div_array == NULL)
 382                 return ~1;
 383
 384         for (i=0; i < size; i++) {
 385                 test_rate = src_rate / *div_array;
 386                 if (test_rate <= tgt_rate)
 387                         return *div_array;
 388                 ++div_array;
 389         }
 390
 391         return ~0;      /* No acceptable divider */
 392 }
 393
 394 /*
 395  * Find divisor for the given clock and target rate.
 396  *
 397  * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
 398  * they are only settable as part of virtual_prcm set.
 399  */
 400 static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
 401         u32 *new_div)
 402 {
 403         u32 gfx_div[] = {2, 3, 4};
 404         u32 sysclkout_div[] = {1, 2, 4, 8, 16};
 405         u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
 406         u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
 407         u32 best_div = ~0, asize = 0;
 408         u32 *div_array = NULL;
 409
 410         switch (tclk->flags & SRC_RATE_SEL_MASK) {
 411         case CM_GFX_SEL1:
 412                 asize = 3;
 413                 div_array = gfx_div;
 414                 break;
 415         case CM_PLL_SEL1:
 416                 return omap2_dpll_round_rate(target_rate);
 417         case CM_SYSCLKOUT_SEL1:
 418                 asize = 5;
 419                 div_array = sysclkout_div;
 420                 break;
 421         case CM_CORE_SEL1:
 422                 if(tclk == &dss1_fck){
 423                         if(tclk->parent == &core_ck){
 424                                 asize = 10;
 425                                 div_array = dss1_div;
 426                         } else {
 427                                 *new_div = 0; /* fixed clk */
 428                                 return(tclk->parent->rate);
 429                         }
 430                 } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
 431                         if(tclk->parent == &core_ck){
 432                                 asize = 10;
 433                                 div_array = vylnq_div;
 434                         } else {
 435                                 *new_div = 0; /* fixed clk */
 436                                 return(tclk->parent->rate);
 437                         }
 438                 }
 439                 break;
 440         }
 441
 442         best_div = omap2_divider_from_table(asize, div_array,
 443          tclk->parent->rate, target_rate);
 444         if (best_div == ~0){
 445                 *new_div = 1;
 446                 return best_div; /* signal error */
 447         }
 448
 449         *new_div = best_div;
 450         return (tclk->parent->rate / best_div);
 451 }
 452
 453 /* Given a clock and a rate apply a clock specific rounding function */
 454 static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
 455 {
 456         u32 new_div = 0;
 457         int valid_rate;
 458
 459         if (clk->flags & RATE_FIXED)
 460                 return clk->rate;
 461
 462         if (clk->flags & RATE_CKCTL) {
 463                 valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
 464                 return valid_rate;
 465         }
 466
 467         if (clk->round_rate != 0)
 468                 return clk->round_rate(clk, rate);
 469
 470         return clk->rate;
 471 }
 472
 473 /*
 474  * Check the DLL lock state, and return tue if running in unlock mode.
 475  * This is needed to compensate for the shifted DLL value in unlock mode.
 476  */
 477 static u32 omap2_dll_force_needed(void)
 478 {
 479         /* dlla and dllb are a set */
 480         u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
 481
 482         if ((dll_state & (1 << 2)) == (1 << 2))
 483                 return 1;
 484         else
 485                 return 0;
 486 }
 487
 488 static u32 omap2_reprogram_sdrc(u32 level, u32 force)
 489 {
 490         u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
 491         u32 prev = curr_perf_level, flags;
 492
 493         if ((curr_perf_level == level) && !force)
 494                 return prev;
 495
 496         m_type = omap2_memory_get_type();
 497         slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
 498         fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
 499
 500         if (level == PRCM_HALF_SPEED) {
 501                 local_irq_save(flags);
 502                 prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP);
 503                 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
 504                                           slow_dll_ctrl, m_type);
 505                 curr_perf_level = PRCM_HALF_SPEED;
 506                 local_irq_restore(flags);
 507         }
 508         if (level == PRCM_FULL_SPEED) {
 509                 local_irq_save(flags);
 510                 prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP);
 511                 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
 512                                           fast_dll_ctrl, m_type);
 513                 curr_perf_level = PRCM_FULL_SPEED;
 514                 local_irq_restore(flags);
 515         }
 516
 517         return prev;
 518 }
 519
 520 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
 521 {
 522         u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
 523         u32 bypass = 0;
 524         struct prcm_config tmpset;
 525         int ret = -EINVAL;
 526
 527         local_irq_save(flags);
 528         cur_rate = omap2_get_dpll_rate(&dpll_ck);
 529         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 530         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 531
 532         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 533                 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
 534         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 535                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
 536         } else if (rate != cur_rate) {
 537                 valid_rate = omap2_dpll_round_rate(rate);
 538                 if (valid_rate != rate)
 539                         goto dpll_exit;
 540
 541                 if (mult == 1)
 542                         low = curr_prcm_set->dpll_speed;
 543                 else
 544                         low = curr_prcm_set->dpll_speed / 2;
 545
 546                 /* REVISIT: This sets several reserved bits? */
 547                 tmpset.cm_clksel1_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 548                 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
 549                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 550                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 551                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 552                 if (rate > low) {
 553                         tmpset.cm_clksel2_pll |= 0x2;
 554                         mult = ((rate / 2) / 1000000);
 555                         done_rate = PRCM_FULL_SPEED;
 556                 } else {
 557                         tmpset.cm_clksel2_pll |= 0x1;
 558                         mult = (rate / 1000000);
 559                         done_rate = PRCM_HALF_SPEED;
 560                 }
 561                 tmpset.cm_clksel1_pll |= (div << OMAP24XX_DPLL_DIV_SHIFT);
 562                 tmpset.cm_clksel1_pll |= (mult << OMAP24XX_DPLL_MULT_SHIFT);
 563
 564                 /* Worst case */
 565                 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
 566
 567                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 568                         bypass = 1;
 569
 570                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
 571
 572                 /* Force dll lock mode */
 573                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 574                                bypass);
 575
 576                 /* Errata: ret dll entry state */
 577                 omap2_init_memory_params(omap2_dll_force_needed());
 578                 omap2_reprogram_sdrc(done_rate, 0);
 579         }
 580         omap2_clksel_recalc(&dpll_ck);
 581         ret = 0;
 582
 583 dpll_exit:
 584         local_irq_restore(flags);
 585         return(ret);
 586 }
 587
 588 /* Just return the MPU speed */
 589 static void omap2_mpu_recalc(struct clk * clk)
 590 {
 591         clk->rate = curr_prcm_set->mpu_speed;
 592 }
 593
 594 /*
 595  * Look for a rate equal or less than the target rate given a configuration set.
 596  *
 597  * What's not entirely clear is "which" field represents the key field.
 598  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 599  * just uses the ARM rates.
 600  */
 601 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
 602 {
 603         struct prcm_config * ptr;
 604         long highest_rate;
 605
 606         if (clk != &virt_prcm_set)
 607                 return -EINVAL;
 608
 609         highest_rate = -EINVAL;
 610
 611         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 612                 if (ptr->xtal_speed != sys_ck.rate)
 613                         continue;
 614
 615                 highest_rate = ptr->mpu_speed;
 616
 617                 /* Can check only after xtal frequency check */
 618                 if (ptr->mpu_speed <= rate)
 619                         break;
 620         }
 621         return highest_rate;
 622 }
 623
 624 /*
 625  * omap2_convert_field_to_div() - turn field value into integer divider
 626  */
 627 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
 628 {
 629         u32 i;
 630         u32 clkout_array[] = {1, 2, 4, 8, 16};
 631
 632         if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
 633                 for (i = 0; i < 5; i++) {
 634                         if (field_val == i)
 635                                 return clkout_array[i];
 636                 }
 637                 return ~0;
 638         } else
 639                 return field_val;
 640 }
 641
 642 /*
 643  * Returns the CLKSEL divider register value
 644  * REVISIT: This should be cleaned up to work nicely with void __iomem *
 645  */
 646 static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
 647                             struct clk *clk)
 648 {
 649         int ret = ~0;
 650         u32 reg_val, div_off;
 651         void __iomem *div_addr = 0;
 652         u32 mask = ~0;
 653
 654         div_off = clk->rate_offset;
 655
 656         switch ((*div_sel & SRC_RATE_SEL_MASK)) {
 657         case CM_MPU_SEL1:
 658                 div_addr = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL);
 659                 mask = OMAP24XX_CLKSEL_MPU_MASK;
 660                 break;
 661         case CM_DSP_SEL1:
 662                 div_addr = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL);
 663                 if (cpu_is_omap2420()) {
 664                         if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
 665                                 mask = OMAP24XX_CLKSEL_DSP_MASK;
 666                         else if (div_off == OMAP2420_CLKSEL_IVA_SHIFT)
 667                                 mask = OMAP2420_CLKSEL_IVA_MASK;
 668                         else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
 669                                 mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 670                 } else if (cpu_is_omap2430()) {
 671                         if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
 672                                 mask = OMAP24XX_CLKSEL_DSP_MASK;
 673                         else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
 674                                 mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 675                 }
 676         case CM_GFX_SEL1:
 677                 div_addr = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL);
 678                 if (div_off == OMAP_CLKSEL_GFX_SHIFT)
 679                         mask = OMAP_CLKSEL_GFX_MASK;
 680                 break;
 681         case CM_MODEM_SEL1:
 682                 div_addr = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL);
 683                 if (div_off == OMAP2430_CLKSEL_MDM_SHIFT)
 684                         mask = OMAP2430_CLKSEL_MDM_MASK;
 685                 break;
 686         case CM_SYSCLKOUT_SEL1:
 687                 div_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
 688                 if (div_off == OMAP24XX_CLKOUT_DIV_SHIFT)
 689                         mask = OMAP24XX_CLKOUT_DIV_MASK;
 690                 else if (div_off == OMAP2420_CLKOUT2_DIV_SHIFT)
 691                         mask = OMAP2420_CLKOUT2_DIV_MASK;
 692                 break;
 693         case CM_CORE_SEL1:
 694                 div_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 695                 switch (div_off) {
 696                 case OMAP24XX_CLKSEL_L3_SHIFT:
 697                         mask = OMAP24XX_CLKSEL_L3_MASK;
 698                         break;
 699                 case OMAP24XX_CLKSEL_L4_SHIFT:
 700                         mask = OMAP24XX_CLKSEL_L4_MASK;
 701                         break;
 702                 case OMAP24XX_CLKSEL_DSS1_SHIFT:
 703                         mask = OMAP24XX_CLKSEL_DSS1_MASK;
 704                         break;
 705                 case OMAP24XX_CLKSEL_DSS2_SHIFT:
 706                         mask = OMAP24XX_CLKSEL_DSS2_MASK;
 707                         break;
 708                 case OMAP2420_CLKSEL_VLYNQ_SHIFT:
 709                         mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 710                         break;
 711                 case OMAP24XX_CLKSEL_SSI_SHIFT:
 712                         mask = OMAP24XX_CLKSEL_SSI_MASK;
 713                         break;
 714                 case OMAP24XX_CLKSEL_USB_SHIFT:
 715                         mask = OMAP24XX_CLKSEL_USB_MASK;
 716                         break;
 717                 }
 718         }
 719
 720         *field_mask = (mask >> div_off);
 721
 722         if (unlikely(mask == ~0))
 723                 div_addr = 0;
 724
 725         *div_sel = (u32)div_addr;
 726
 727         if (unlikely(div_addr == 0))
 728                 return ret;
 729
 730         /* Isolate field */
 731         reg_val = cm_read_reg(div_addr) & mask;
 732
 733         /* Normalize back to divider value */
 734         reg_val >>= div_off;
 735
 736         return reg_val;
 737 }
 738
 739 /*
 740  * Return divider to be applied to parent clock.
 741  * Return 0 on error.
 742  */
 743 static u32 omap2_clksel_get_divisor(struct clk *clk)
 744 {
 745         int ret = 0;
 746         u32 div, div_sel, div_off, field_mask, field_val;
 747
 748         /* isolate control register */
 749         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 750
 751         div_off = clk->rate_offset;
 752         field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 753         if (div_sel == 0)
 754                 return ret;
 755
 756         div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 757         div = omap2_clksel_to_divisor(div_sel, field_val);
 758
 759         return div;
 760 }
 761
 762 /* Set the clock rate for a clock source */
 763 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 764
 765 {
 766         int ret = -EINVAL;
 767         void __iomem * reg;
 768         u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
 769         u32 new_div = 0;
 770
 771         if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
 772                 if (clk == &dpll_ck)
 773                         return omap2_reprogram_dpll(clk, rate);
 774
 775                 /* Isolate control register */
 776                 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
 777                 div_off = clk->rate_offset;
 778
 779                 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
 780                 if (validrate != rate)
 781                         return(ret);
 782
 783                 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
 784                 if (div_sel == 0)
 785                         return ret;
 786
 787                 if (clk->flags & CM_SYSCLKOUT_SEL1) {
 788                         switch (new_div) {
 789                         case 16:
 790                                 field_val = 4;
 791                                 break;
 792                         case 8:
 793                                 field_val = 3;
 794                                 break;
 795                         case 4:
 796                                 field_val = 2;
 797                                 break;
 798                         case 2:
 799                                 field_val = 1;
 800                                 break;
 801                         case 1:
 802                                 field_val = 0;
 803                                 break;
 804                         }
 805                 } else
 806                         field_val = new_div;
 807
 808                 reg = (void __iomem *)div_sel;
 809
 810                 reg_val = cm_read_reg(reg);
 811                 reg_val &= ~(field_mask << div_off);
 812                 reg_val |= (field_val << div_off);
 813                 cm_write_reg(reg_val, reg);
 814                 wmb();
 815                 clk->rate = clk->parent->rate / field_val;
 816
 817                 if (clk->flags & DELAYED_APP) {
 818                         prm_write_reg(OMAP24XX_VALID_CONFIG,
 819                                       OMAP24XX_PRCM_CLKCFG_CTRL);
 820                         wmb();
 821                 }
 822                 ret = 0;
 823         } else if (clk->set_rate != 0)
 824                 ret = clk->set_rate(clk, rate);
 825
 826         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
 827                 propagate_rate(clk);
 828
 829         return ret;
 830 }
 831
 832 /* Converts encoded control register address into a full address */
 833 static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 834                                struct clk *src_clk, u32 *field_mask)
 835 {
 836         u32 val = ~0, mask = 0;
 837         void __iomem *src_reg_addr = 0;
 838
 839         /* Find target control register.*/
 840         switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
 841         case CM_CORE_SEL1:
 842                 src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 843                 if (reg_offset == OMAP24XX_CLKSEL_DSS2_SHIFT) {
 844                         mask = OMAP24XX_CLKSEL_DSS2_MASK;
 845                         mask >>= OMAP24XX_CLKSEL_DSS2_SHIFT;
 846                         if (src_clk == &sys_ck)
 847                                 val = 0;
 848                         if (src_clk == &func_48m_ck)
 849                                 val = 1;
 850                 } else if (reg_offset == OMAP24XX_CLKSEL_DSS1_SHIFT) {
 851                         mask = OMAP24XX_CLKSEL_DSS1_MASK;
 852                         mask >>= OMAP24XX_CLKSEL_DSS1_SHIFT;
 853                         if (src_clk == &sys_ck)
 854                                 val = 0;
 855                         else if (src_clk == &core_ck)   /* divided clock */
 856                                 val = 0x10;             /* rate needs fixing */
 857                 } else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
 858                            cpu_is_omap2420()){
 859                         mask = OMAP2420_CLKSEL_VLYNQ_MASK;
 860                         mask >>= OMAP2420_CLKSEL_VLYNQ_SHIFT;
 861                         if(src_clk == &func_96m_ck)
 862                                 val = 0;
 863                         else if (src_clk == &core_ck)
 864                                 val = 0x10;
 865                 }
 866                 break;
 867         case CM_CORE_SEL2:
 868                 src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2);
 869                 mask = 0x3;
 870                 if (src_clk == &func_32k_ck)
 871                         val = 0x0;
 872                 if (src_clk == &sys_ck)
 873                         val = 0x1;
 874                 if (src_clk == &alt_ck)
 875                         val = 0x2;
 876                 break;
 877         case CM_WKUP_SEL1:
 878                 src_reg_addr = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL);
 879                 mask = 0x3;
 880                 if (src_clk == &func_32k_ck)
 881                         val = 0x0;
 882                 if (src_clk == &sys_ck)
 883                         val = 0x1;
 884                 if (src_clk == &alt_ck)
 885                         val = 0x2;
 886                 break;
 887         case CM_PLL_SEL1:
 888                 src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1);
 889                 mask = 0x1;
 890                 if (reg_offset == 0x3) {
 891                         if (src_clk == &apll96_ck)
 892                                 val = 0;
 893                         if (src_clk == &alt_ck)
 894                                 val = 1;
 895                 }
 896                 else if (reg_offset == 0x5) {
 897                         if (src_clk == &apll54_ck)
 898                                 val = 0;
 899                         if (src_clk == &alt_ck)
 900                                 val = 1;
 901                 }
 902                 break;
 903         case CM_PLL_SEL2:
 904                 src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2);
 905                 mask = 0x3;
 906                 if (src_clk == &func_32k_ck)
 907                         val = 0x0;
 908                 if (src_clk == &dpll_ck)
 909                         val = 0x2;
 910                 break;
 911         case CM_SYSCLKOUT_SEL1:
 912                 src_reg_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
 913                 mask = 0x3;
 914                 if (src_clk == &dpll_ck)
 915                         val = 0;
 916                 if (src_clk == &sys_ck)
 917                         val = 1;
 918                 if (src_clk == &func_96m_ck)
 919                         val = 2;
 920                 if (src_clk == &func_54m_ck)
 921                         val = 3;
 922                 break;
 923         }
 924
 925         if (val == ~0)                  /* Catch errors in offset */
 926                 *type_to_addr = 0;
 927         else
 928                 *type_to_addr = (u32)src_reg_addr;
 929         *field_mask = mask;
 930
 931         return val;
 932 }
 933
 934 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 935 {
 936         void __iomem * reg;
 937         u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
 938         int ret = -EINVAL;
 939
 940         if (unlikely(clk->flags & CONFIG_PARTICIPANT))
 941                 return ret;
 942
 943         if (clk->flags & SRC_SEL_MASK) {        /* On-chip SEL collection */
 944                 src_sel = (SRC_RATE_SEL_MASK & clk->flags);
 945                 src_off = clk->src_offset;
 946
 947                 if (src_sel == 0)
 948                         goto set_parent_error;
 949
 950                 field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
 951                                                 &field_mask);
 952
 953                 reg = (void __iomem *)src_sel;
 954
 955                 if (clk->usecount > 0)
 956                         _omap2_clk_disable(clk);
 957
 958                 /* Set new source value (previous dividers if any in effect) */
 959                 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
 960                 reg_val |= (field_val << src_off);
 961                 __raw_writel(reg_val, reg);
 962                 wmb();
 963
 964                 if (clk->flags & DELAYED_APP) {
 965                         prm_write_reg(OMAP24XX_VALID_CONFIG,
 966                                       OMAP24XX_PRCM_CLKCFG_CTRL);
 967                         wmb();
 968                 }
 969                 if (clk->usecount > 0)
 970                         _omap2_clk_enable(clk);
 971
 972                 clk->parent = new_parent;
 973
 974                 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
 975                 if ((new_parent == &core_ck) && (clk == &dss1_fck))
 976                         clk->rate = new_parent->rate / 0x10;
 977                 else
 978                         clk->rate = new_parent->rate;
 979
 980                 if (unlikely(clk->flags & RATE_PROPAGATES))
 981                         propagate_rate(clk);
 982
 983                 return 0;
 984         } else {
 985                 clk->parent = new_parent;
 986                 rate = new_parent->rate;
 987                 omap2_clk_set_rate(clk, rate);
 988                 ret = 0;
 989         }
 990
 991  set_parent_error:
 992         return ret;
 993 }
 994
 995 /* Sets basic clocks based on the specified rate */
 996 static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
 997 {
 998         u32 flags, cur_rate, done_rate, bypass = 0;
 999         u8 cpu_mask = 0;
1000         struct prcm_config *prcm;
1001         unsigned long found_speed = 0;
1002
1003         if (clk != &virt_prcm_set)
1004                 return -EINVAL;
1005
1006         /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */
1007         if (cpu_is_omap2420())
1008                 cpu_mask = RATE_IN_242X;
1009         else if (cpu_is_omap2430())
1010                 cpu_mask = RATE_IN_243X;
1011
1012         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1013                 if (!(prcm->flags & cpu_mask))
1014                         continue;
1015
1016                 if (prcm->xtal_speed != sys_ck.rate)
1017                         continue;
1018
1019                 if (prcm->mpu_speed <= rate) {
1020                         found_speed = prcm->mpu_speed;
1021                         break;
1022                 }
1023         }
1024
1025         if (!found_speed) {
1026                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
1027          rate / 1000000);
1028                 return -EINVAL;
1029         }
1030
1031         curr_prcm_set = prcm;
1032         cur_rate = omap2_get_dpll_rate(&dpll_ck);
1033
1034         if (prcm->dpll_speed == cur_rate / 2) {
1035                 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
1036         } else if (prcm->dpll_speed == cur_rate * 2) {
1037                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
1038         } else if (prcm->dpll_speed != cur_rate) {
1039                 local_irq_save(flags);
1040
1041                 if (prcm->dpll_speed == prcm->xtal_speed)
1042                         bypass = 1;
1043
1044                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == 2)
1045                         done_rate = PRCM_FULL_SPEED;
1046                 else
1047                         done_rate = PRCM_HALF_SPEED;
1048
1049                 /* MPU divider */
1050                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
1051
1052                 /* dsp + iva1 div(2420), iva2.1(2430) */
1053                 cm_write_mod_reg(prcm->cm_clksel_dsp,
1054                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
1055
1056                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
1057
1058                 /* Major subsystem dividers */
1059                 cm_write_mod_reg(prcm->cm_clksel1_core, CORE_MOD, CM_CLKSEL1);
1060                 if (cpu_is_omap2430())
1061                         cm_write_mod_reg(prcm->cm_clksel_mdm,
1062                                          OMAP2430_MDM_MOD, CM_CLKSEL);
1063
1064                 /* x2 to enter init_mem */
1065                 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
1066
1067                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
1068                                bypass);
1069
1070                 omap2_init_memory_params(omap2_dll_force_needed());
1071                 omap2_reprogram_sdrc(done_rate, 0);
1072
1073                 local_irq_restore(flags);
1074         }
1075         omap2_clksel_recalc(&dpll_ck);
1076
1077         return 0;
1078 }
1079
1080 /*-------------------------------------------------------------------------
1081  * Omap2 clock reset and init functions
1082  *-------------------------------------------------------------------------*/
1083
1084 #ifdef CONFIG_OMAP_RESET_CLOCKS
1085 static void __init omap2_clk_disable_unused(struct clk *clk)
1086 {
1087         u32 regval32;
1088
1089         regval32 = cm_read_reg(clk->enable_reg);
1090         if ((regval32 & (1 << clk->enable_bit)) == 0)
1091                 return;
1092
1093         printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1094         _omap2_clk_disable(clk);
1095 }
1096 #else
1097 #define omap2_clk_disable_unused        NULL
1098 #endif
1099
1100 static struct clk_functions omap2_clk_functions = {
1101         .clk_enable             = omap2_clk_enable,
1102         .clk_disable            = omap2_clk_disable,
1103         .clk_round_rate         = omap2_clk_round_rate,
1104         .clk_set_rate           = omap2_clk_set_rate,
1105         .clk_set_parent         = omap2_clk_set_parent,
1106         .clk_disable_unused     = omap2_clk_disable_unused,
1107 };
1108
1109 static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
1110 {
1111         u32 div, aplls, sclk = 13000000;
1112
1113         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
1114         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
1115         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;   /* Isolate field, 0,2,3 */
1116
1117         if (aplls == 0)
1118                 sclk = 19200000;
1119         else if (aplls == 2)
1120                 sclk = 13000000;
1121         else if (aplls == 3)
1122                 sclk = 12000000;
1123
1124         div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
1125         div &= OMAP_SYSCLKDIV_MASK;
1126         div >>= sys->rate_offset;
1127
1128         osc->rate = sclk * div;
1129         sys->rate = sclk;
1130 }
1131
1132 /*
1133  * Set clocks for bypass mode for reboot to work.
1134  */
1135 void omap2_clk_prepare_for_reboot(void)
1136 {
1137         u32 rate;
1138
1139         if (vclk == NULL || sclk == NULL)
1140                 return;
1141
1142         rate = clk_get_rate(sclk);
1143         clk_set_rate(vclk, rate);
1144 }
1145
1146 /*
1147  * Switch the MPU rate if specified on cmdline.
1148  * We cannot do this early until cmdline is parsed.
1149  */
1150 static int __init omap2_clk_arch_init(void)
1151 {
1152         if (!mpurate)
1153                 return -EINVAL;
1154
1155         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
1156                 printk(KERN_ERR "Could not find matching MPU rate\n");
1157
1158         propagate_rate(&osc_ck);                /* update main root fast */
1159         propagate_rate(&func_32k_ck);           /* update main root slow */
1160
1161         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
1162                "%ld.%01ld/%ld/%ld MHz\n",
1163                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1164                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1165
1166         return 0;
1167 }
1168 arch_initcall(omap2_clk_arch_init);
1169
1170 int __init omap2_clk_init(void)
1171 {
1172         struct prcm_config *prcm;
1173         struct clk ** clkp;
1174         u32 clkrate;
1175
1176         clk_init(&omap2_clk_functions);
1177         omap2_get_crystal_rate(&osc_ck, &sys_ck);
1178
1179         for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
1180              clkp++) {
1181
1182                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
1183                         clk_register(*clkp);
1184                         continue;
1185                 }
1186
1187                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
1188                         clk_register(*clkp);
1189                         continue;
1190                 }
1191         }
1192
1193         /* Check the MPU rate set by bootloader */
1194         clkrate = omap2_get_dpll_rate(&dpll_ck);
1195         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1196                 if (prcm->xtal_speed != sys_ck.rate)
1197                         continue;
1198                 if (prcm->dpll_speed <= clkrate)
1199                          break;
1200         }
1201         curr_prcm_set = prcm;
1202
1203         propagate_rate(&osc_ck);                /* update main root fast */
1204         propagate_rate(&func_32k_ck);           /* update main root slow */
1205
1206         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
1207                "%ld.%01ld/%ld/%ld MHz\n",
1208                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1209                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1210
1211         /*
1212          * Only enable those clocks we will need, let the drivers
1213          * enable other clocks as necessary
1214          */
1215         clk_enable(&sync_32k_ick);
1216         clk_enable(&omapctrl_ick);
1217
1218         /* Force the APLLs always active. The clocks are idled
1219          * automatically by hardware. */
1220         clk_enable(&apll96_ck);
1221         clk_enable(&apll54_ck);
1222
1223         if (cpu_is_omap2430())
1224                 clk_enable(&sdrc_ick);
1225
1226         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1227         vclk = clk_get(NULL, "virt_prcm_set");
1228         sclk = clk_get(NULL, "sys_ck");
1229
1230         return 0;
1231 }