2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <mach/prcm.h>
32 #include <mach/control.h>
33 #include <asm/div64.h>
35 #include <mach/sdrc.h>
39 #include "prm-regbits-24xx.h"
41 #include "cm-regbits-24xx.h"
42 #include "cm-regbits-34xx.h"
44 #define MAX_CLOCK_ENABLE_WAIT 100000
46 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
47 #define DPLL_MIN_MULTIPLIER 1
48 #define DPLL_MIN_DIVIDER 1
50 /* Possible error results from _dpll_test_mult */
51 #define DPLL_MULT_UNDERFLOW -1
54 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
55 * The higher the scale factor, the greater the risk of arithmetic overflow,
56 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
57 * must be a power of DPLL_SCALE_BASE.
59 #define DPLL_SCALE_FACTOR 64
60 #define DPLL_SCALE_BASE 2
61 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
62 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
65 #define DPLL_FINT_BAND1_MIN 750000
66 #define DPLL_FINT_BAND1_MAX 2100000
67 #define DPLL_FINT_BAND2_MIN 7500000
68 #define DPLL_FINT_BAND2_MAX 21000000
70 /* _dpll_test_fint() return codes */
71 #define DPLL_FINT_UNDERFLOW -1
72 #define DPLL_FINT_INVALID -2
74 /* Bitmask to isolate the register type of clk.enable_reg */
75 #define PRCM_REGTYPE_MASK 0xf0
76 /* various CM register type options */
77 #define CM_FCLKEN_REGTYPE 0x00
78 #define CM_ICLKEN_REGTYPE 0x10
79 #define CM_IDLEST_REGTYPE 0x20
83 /*-------------------------------------------------------------------------
84 * OMAP2/3 specific clock functions
85 *-------------------------------------------------------------------------*/
88 * _omap2_clk_read_reg - read a clock register
91 * Given a struct clk *, returns the value of the clock's register.
93 static u32 _omap2_clk_read_reg(u16 reg_offset, struct clk *clk)
95 if (clk->prcm_mod & CLK_REG_IN_SCM)
96 return omap_ctrl_readl(reg_offset);
97 else if (clk->prcm_mod & CLK_REG_IN_PRM)
98 return prm_read_mod_reg(clk->prcm_mod & PRCM_MOD_ADDR_MASK,
101 return cm_read_mod_reg(clk->prcm_mod, reg_offset);
105 * _omap2_clk_write_reg - write a clock's register
106 * @v: value to write to the clock's enable_reg
109 * Given a register value @v and struct clk * @clk, writes the value of @v to
110 * the clock's enable register. No return value.
112 static void _omap2_clk_write_reg(u32 v, u16 reg_offset, struct clk *clk)
114 if (clk->prcm_mod & CLK_REG_IN_SCM)
115 omap_ctrl_writel(v, reg_offset);
116 else if (clk->prcm_mod & CLK_REG_IN_PRM)
117 prm_write_mod_reg(v, clk->prcm_mod & PRCM_MOD_ADDR_MASK,
120 cm_write_mod_reg(v, clk->prcm_mod, reg_offset);
124 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
127 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
128 * don't take effect until the VALID_CONFIG bit is written, write the
129 * VALID_CONFIG bit and wait for the write to complete. No return value.
131 static void _omap2xxx_clk_commit(struct clk *clk)
133 if (!cpu_is_omap24xx())
136 if (!(clk->flags & DELAYED_APP))
139 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
140 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
142 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
146 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
147 * @clk: DPLL struct clk to test
148 * @n: divider value (N) to test
150 * Tests whether a particular divider @n will result in a valid DPLL
151 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
152 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
153 * (assuming that it is counting N upwards), or -2 if the enclosing loop
154 * should skip to the next iteration (again assuming N is increasing).
156 static int _dpll_test_fint(struct clk *clk, u8 n)
158 struct dpll_data *dd;
164 /* DPLL divider must result in a valid jitter correction val */
165 fint = clk->parent->rate / (n + 1);
166 if (fint < DPLL_FINT_BAND1_MIN) {
168 pr_debug("rejecting n=%d due to Fint failure, "
169 "lowering max_divider\n", n);
171 ret = DPLL_FINT_UNDERFLOW;
173 } else if (fint > DPLL_FINT_BAND1_MAX &&
174 fint < DPLL_FINT_BAND2_MIN) {
176 pr_debug("rejecting n=%d due to Fint failure\n", n);
177 ret = DPLL_FINT_INVALID;
179 } else if (fint > DPLL_FINT_BAND2_MAX) {
181 pr_debug("rejecting n=%d due to Fint failure, "
182 "boosting min_divider\n", n);
184 ret = DPLL_FINT_INVALID;
192 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
193 * @clk: OMAP clock struct ptr to use
195 * Convert a clockdomain name stored in a struct clk 'clk' into a
196 * clockdomain pointer, and save it into the struct clk. Intended to be
197 * called during clk_register(). No return value.
199 void omap2_init_clk_clkdm(struct clk *clk)
201 struct clockdomain *clkdm;
203 clkdm = clkdm_lookup(clk->clkdm.name);
205 pr_debug("clock: associated clk %s to clkdm %s\n",
206 clk->name, clk->clkdm.name);
207 clk->clkdm.ptr = clkdm;
209 pr_err("clock: %s: could not associate to clkdm %s\n",
210 clk->name, clk->clkdm.name);
215 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
216 * @clk: OMAP clock struct ptr to use
218 * Given a pointer to a source-selectable struct clk, read the hardware
219 * register and determine what its parent is currently set to. Update the
220 * clk->parent field with the appropriate clk ptr.
222 void omap2_init_clksel_parent(struct clk *clk)
224 const struct clksel *clks;
225 const struct clksel_rate *clkr;
231 r = _omap2_clk_read_reg(clk->clksel_reg, clk);
232 r &= clk->clksel_mask;
233 r >>= __ffs(clk->clksel_mask);
235 for (clks = clk->clksel; clks->parent && !found; clks++) {
236 for (clkr = clks->rates; clkr->div && !found; clkr++) {
237 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
238 if (clk->parent != clks->parent) {
239 pr_debug("clock: inited %s parent "
241 clk->name, clks->parent->name,
243 clk->parent->name : "NULL"));
245 omap_clk_del_child(clk->parent,
247 clk->parent = clks->parent;
248 omap_clk_add_child(clk->parent, clk);
256 printk(KERN_ERR "clock: init parent: could not find "
257 "regval %0x for clock %s\n", r, clk->name);
263 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
264 * @clk: struct clk * of a DPLL
265 * @parent_rate: rate of the parent of the DPLL clock
267 * DPLLs can be locked or bypassed - basically, enabled or disabled.
268 * When locked, the DPLL output depends on the M and N values. When
269 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
270 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
271 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
272 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
273 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
274 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
275 * if the clock @clk is not a DPLL.
277 u32 omap2_get_dpll_rate(struct clk *clk, unsigned long parent_rate)
280 u32 dpll_mult, dpll_div, v;
281 struct dpll_data *dd;
287 /* Return bypass rate if DPLL is bypassed */
288 v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
289 v &= dd->enable_mask;
290 v >>= __ffs(dd->enable_mask);
292 if (cpu_is_omap24xx()) {
294 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
295 v == OMAP2XXX_EN_DPLL_FRBYPASS)
298 } else if (cpu_is_omap34xx()) {
300 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
301 v == OMAP3XXX_EN_DPLL_FRBYPASS)
302 return dd->bypass_clk->rate;
306 v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
307 dpll_mult = v & dd->mult_mask;
308 dpll_mult >>= __ffs(dd->mult_mask);
309 dpll_div = v & dd->div1_mask;
310 dpll_div >>= __ffs(dd->div1_mask);
312 dpll_clk = (long long)parent_rate * dpll_mult;
313 do_div(dpll_clk, dpll_div + 1);
319 * Used for clocks that have the same value as the parent clock,
320 * divided by some factor
322 void omap2_fixed_divisor_recalc(struct clk *clk, unsigned long parent_rate,
327 WARN_ON(!clk->fixed_div); /* XXX move this to init */
329 rate = parent_rate / clk->fixed_div;
331 if (rate_storage == CURRENT_RATE)
333 else if (rate_storage == TEMP_RATE)
334 clk->temp_rate = rate;
338 * omap2_wait_clock_ready - wait for clock to enable
339 * @prcm_mod: CM submodule offset from CM_BASE (e.g., "MPU_MOD")
340 * @reg_index: offset of CM register address from prcm_mod
341 * @mask: value to mask against to determine if the clock is active
342 * @name: name of the clock (for printk)
344 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
345 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
347 int omap2_wait_clock_ready(s16 prcm_mod, u16 reg_index, u32 mask,
353 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
354 * 34xx reverses this, just to keep us on our toes
356 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
358 else if (cpu_mask & RATE_IN_343X)
362 while (((cm_read_mod_reg(prcm_mod, reg_index) & mask) != ena) &&
363 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
367 if (i < MAX_CLOCK_ENABLE_WAIT)
368 pr_debug("Clock %s stable after %d loops\n", name, i);
370 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
371 name, MAX_CLOCK_ENABLE_WAIT);
373 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
378 * omap2_clk_wait_ready - wait for a OMAP module to come out of target idle
379 * @clk: struct clk * recently enabled to indicate the module to test
381 * Wait for an OMAP module with a target idle state bit to come out of
382 * idle once both its interface clock and primary functional clock are
383 * both enabled. Any register read or write to the device before it
384 * returns from idle will cause an abort. Not all modules have target
385 * idle state bits (for example, DSS and CAM on OMAP24xx); so we don't
386 * wait for those. No return value.
388 * We don't need special code here for INVERT_ENABLE for the time
389 * being since INVERT_ENABLE only applies to clocks enabled by
392 * REVISIT: This function is misnamed: it should be something like
393 * "omap2_module_wait_ready", and in the long-term, it does not belong
394 * in the clock framework. It also shouldn't be doing register
395 * arithmetic to determine the companion clock.
397 static void omap2_clk_wait_ready(struct clk *clk)
399 u16 other_reg, idlest_reg;
402 if (!(clk->flags & WAIT_READY))
405 /* If we are enabling an iclk, also test the fclk; and vice versa */
406 other_bit = 1 << clk->enable_bit;
407 other_reg = clk->enable_reg & ~PRCM_REGTYPE_MASK;
409 if (clk->enable_reg & CM_ICLKEN_REGTYPE)
410 other_reg |= CM_FCLKEN_REGTYPE;
412 other_reg |= CM_ICLKEN_REGTYPE;
414 /* Ensure functional and interface clocks are running. */
415 if (!(cm_read_mod_reg(clk->prcm_mod, other_reg) & other_bit))
418 idlest_reg = other_reg & ~PRCM_REGTYPE_MASK;
419 idlest_reg |= CM_IDLEST_REGTYPE;
421 omap2_wait_clock_ready(clk->prcm_mod, idlest_reg, 1 << clk->idlest_bit,
425 /* Enables clock without considering parent dependencies or use count
426 * REVISIT: Maybe change this to use clk->enable like on omap1?
428 static int _omap2_clk_enable(struct clk *clk)
432 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
436 return clk->enable(clk);
438 v = _omap2_clk_read_reg(clk->enable_reg, clk);
439 if (clk->flags & INVERT_ENABLE)
440 v &= ~(1 << clk->enable_bit);
442 v |= (1 << clk->enable_bit);
443 _omap2_clk_write_reg(v, clk->enable_reg, clk);
444 v = _omap2_clk_read_reg(clk->enable_reg, clk); /* OCP barrier */
446 omap2_clk_wait_ready(clk);
451 /* Disables clock without considering parent dependencies or use count */
452 static void _omap2_clk_disable(struct clk *clk)
456 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
464 v = _omap2_clk_read_reg(clk->enable_reg, clk);
465 if (clk->flags & INVERT_ENABLE)
466 v |= (1 << clk->enable_bit);
468 v &= ~(1 << clk->enable_bit);
469 _omap2_clk_write_reg(v, clk->enable_reg, clk);
470 /* No OCP barrier needed here since it is a disable operation */
473 void omap2_clk_disable(struct clk *clk)
475 if (clk->usecount > 0 && !(--clk->usecount)) {
476 _omap2_clk_disable(clk);
478 omap2_clk_disable(clk->parent);
479 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
484 int omap2_clk_enable(struct clk *clk)
488 if (++clk->usecount > 1)
491 omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);
494 ret = omap2_clk_enable(clk->parent);
498 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
502 ret = _omap2_clk_enable(clk);
505 omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);
508 omap2_clk_disable(clk->parent);
517 * Used for clocks that are part of CLKSEL_xyz governed clocks.
518 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
520 void omap2_clksel_recalc(struct clk *clk, unsigned long parent_rate,
526 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
528 div = omap2_clksel_get_divisor(clk);
532 rate = parent_rate / div;
534 if (rate_storage == CURRENT_RATE)
536 else if (rate_storage == TEMP_RATE)
537 clk->temp_rate = rate;
539 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
543 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
544 * @clk: OMAP struct clk ptr to inspect
545 * @src_clk: OMAP struct clk ptr of the parent clk to search for
547 * Scan the struct clksel array associated with the clock to find
548 * the element associated with the supplied parent clock address.
549 * Returns a pointer to the struct clksel on success or NULL on error.
551 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
554 const struct clksel *clks;
559 for (clks = clk->clksel; clks->parent; clks++) {
560 if (clks->parent == src_clk)
561 break; /* Found the requested parent */
565 printk(KERN_ERR "clock: Could not find parent clock %s in "
566 "clksel array of clock %s\n", src_clk->name,
575 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
576 * @clk: OMAP struct clk to use
577 * @target_rate: desired clock rate
578 * @new_div: ptr to where we should store the divisor
580 * Finds 'best' divider value in an array based on the source and target
581 * rates. The divider array must be sorted with smallest divider first.
583 * Returns the rounded clock rate or returns 0xffffffff on error.
585 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
588 unsigned long test_rate;
589 const struct clksel *clks;
590 const struct clksel_rate *clkr;
593 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
594 clk->name, target_rate);
598 clks = omap2_get_clksel_by_parent(clk, clk->parent);
602 for (clkr = clks->rates; clkr->div; clkr++) {
603 if (!(clkr->flags & cpu_mask))
607 if (clkr->div <= last_div)
608 printk(KERN_ERR "clock: clksel_rate table not sorted "
609 "for clock %s", clk->name);
611 last_div = clkr->div;
613 test_rate = clk->parent->rate / clkr->div;
615 if (test_rate <= target_rate)
616 break; /* found it */
620 printk(KERN_ERR "clock: Could not find divisor for target "
621 "rate %ld for clock %s parent %s\n", target_rate,
622 clk->name, clk->parent->name);
626 *new_div = clkr->div;
628 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
629 (clk->parent->rate / clkr->div));
631 return (clk->parent->rate / clkr->div);
635 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
636 * @clk: OMAP struct clk to use
637 * @target_rate: desired clock rate
639 * Compatibility wrapper for OMAP clock framework
640 * Finds best target rate based on the source clock and possible dividers.
641 * rates. The divider array must be sorted with smallest divider first.
643 * Returns the rounded clock rate or returns 0xffffffff on error.
645 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
649 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
653 /* Given a clock and a rate apply a clock specific rounding function */
654 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
656 if (clk->round_rate != NULL)
657 return clk->round_rate(clk, rate);
663 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
664 * @clk: OMAP struct clk to use
665 * @field_val: register field value to find
667 * Given a struct clk of a rate-selectable clksel clock, and a register field
668 * value to search for, find the corresponding clock divisor. The register
669 * field value should be pre-masked and shifted down so the LSB is at bit 0
670 * before calling. Returns 0 on error
672 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
674 const struct clksel *clks;
675 const struct clksel_rate *clkr;
677 clks = omap2_get_clksel_by_parent(clk, clk->parent);
681 for (clkr = clks->rates; clkr->div; clkr++) {
682 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
687 printk(KERN_ERR "clock: Could not find fieldval %d for "
688 "clock %s parent %s\n", field_val, clk->name,
697 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
698 * @clk: OMAP struct clk to use
699 * @div: integer divisor to search for
701 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
702 * find the corresponding register field value. The return register value is
703 * the value before left-shifting. Returns 0xffffffff on error
705 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
707 const struct clksel *clks;
708 const struct clksel_rate *clkr;
710 /* should never happen */
713 clks = omap2_get_clksel_by_parent(clk, clk->parent);
717 for (clkr = clks->rates; clkr->div; clkr++) {
718 if ((clkr->flags & cpu_mask) && (clkr->div == div))
723 printk(KERN_ERR "clock: Could not find divisor %d for "
724 "clock %s parent %s\n", div, clk->name,
733 * omap2_clksel_get_divisor - get current divider applied to parent clock.
734 * @clk: OMAP struct clk to use.
736 * Returns the integer divisor upon success or 0 on error.
738 u32 omap2_clksel_get_divisor(struct clk *clk)
742 if (!clk->clksel_mask)
745 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
746 v &= clk->clksel_mask;
747 v >>= __ffs(clk->clksel_mask);
749 return omap2_clksel_to_divisor(clk, v);
752 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
754 u32 v, field_val, validrate, new_div = 0;
756 if (!clk->clksel_mask)
759 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
760 if (validrate != rate)
763 field_val = omap2_divisor_to_clksel(clk, new_div);
767 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
768 v &= ~clk->clksel_mask;
769 v |= field_val << __ffs(clk->clksel_mask);
770 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
771 v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
773 clk->rate = clk->parent->rate / new_div;
775 _omap2xxx_clk_commit(clk);
781 /* Set the clock rate for a clock source */
782 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
786 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
788 if (clk->set_rate != NULL)
789 ret = clk->set_rate(clk, rate);
795 * Converts encoded control register address into a full address
796 * On error, the return value (parent_div) will be 0.
798 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
801 const struct clksel *clks;
802 const struct clksel_rate *clkr;
804 clks = omap2_get_clksel_by_parent(clk, src_clk);
808 for (clkr = clks->rates; clkr->div; clkr++) {
809 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
810 break; /* Found the default rate for this platform */
814 printk(KERN_ERR "clock: Could not find default rate for "
815 "clock %s parent %s\n", clk->name,
816 src_clk->parent->name);
820 /* Should never happen. Add a clksel mask to the struct clk. */
821 WARN_ON(clk->clksel_mask == 0);
823 *field_val = clkr->val;
828 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
830 u32 field_val, v, parent_div;
835 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
839 if (clk->usecount > 0)
840 _omap2_clk_disable(clk);
842 /* Set new source value (previous dividers if any in effect) */
843 v = _omap2_clk_read_reg(clk->clksel_reg, clk);
844 v &= ~clk->clksel_mask;
845 v |= field_val << __ffs(clk->clksel_mask);
846 _omap2_clk_write_reg(v, clk->clksel_reg, clk);
847 v = _omap2_clk_read_reg(clk->clksel_reg, clk); /* OCP barrier */
849 _omap2xxx_clk_commit(clk);
851 if (clk->usecount > 0)
852 _omap2_clk_enable(clk);
854 clk->parent = new_parent;
856 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
857 clk->rate = new_parent->rate;
860 clk->rate /= parent_div;
862 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
863 clk->name, clk->parent->name, clk->rate);
868 struct clk *omap2_clk_get_parent(struct clk *clk)
873 /* DPLL rate rounding code */
876 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
877 * @clk: struct clk * of the DPLL
878 * @tolerance: maximum rate error tolerance
880 * Set the maximum DPLL rate error tolerance for the rate rounding
881 * algorithm. The rate tolerance is an attempt to balance DPLL power
882 * saving (the least divider value "n") vs. rate fidelity (the least
883 * difference between the desired DPLL target rate and the rounded
884 * rate out of the algorithm). So, increasing the tolerance is likely
885 * to decrease DPLL power consumption and increase DPLL rate error.
886 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
887 * DPLL; or 0 upon success.
889 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
891 if (!clk || !clk->dpll_data)
894 clk->dpll_data->rate_tolerance = tolerance;
899 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
900 unsigned int m, unsigned int n)
902 unsigned long long num;
904 num = (unsigned long long)parent_rate * m;
910 * _dpll_test_mult - test a DPLL multiplier value
911 * @m: pointer to the DPLL m (multiplier) value under test
912 * @n: current DPLL n (divider) value under test
913 * @new_rate: pointer to storage for the resulting rounded rate
914 * @target_rate: the desired DPLL rate
915 * @parent_rate: the DPLL's parent clock rate
917 * This code tests a DPLL multiplier value, ensuring that the
918 * resulting rate will not be higher than the target_rate, and that
919 * the multiplier value itself is valid for the DPLL. Initially, the
920 * integer pointed to by the m argument should be prescaled by
921 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
922 * a non-scaled m upon return. This non-scaled m will result in a
923 * new_rate as close as possible to target_rate (but not greater than
924 * target_rate) given the current (parent_rate, n, prescaled m)
925 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
926 * non-scaled m attempted to underflow, which can allow the calling
927 * function to bail out early; or 0 upon success.
929 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
930 unsigned long target_rate,
931 unsigned long parent_rate)
933 int r = 0, carry = 0;
935 /* Unscale m and round if necessary */
936 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
938 *m = (*m / DPLL_SCALE_FACTOR) + carry;
941 * The new rate must be <= the target rate to avoid programming
942 * a rate that is impossible for the hardware to handle
944 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
945 if (*new_rate > target_rate) {
950 /* Guard against m underflow */
951 if (*m < DPLL_MIN_MULTIPLIER) {
952 *m = DPLL_MIN_MULTIPLIER;
954 r = DPLL_MULT_UNDERFLOW;
958 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
964 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
965 * @clk: struct clk * for a DPLL
966 * @target_rate: desired DPLL clock rate
968 * Given a DPLL, a desired target rate, and a rate tolerance, round
969 * the target rate to a possible, programmable rate for this DPLL.
970 * Rate tolerance is assumed to be set by the caller before this
971 * function is called. Attempts to select the minimum possible n
972 * within the tolerance to reduce power consumption. Stores the
973 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
974 * will not need to call this (expensive) function again. Returns ~0
975 * if the target rate cannot be rounded, either because the rate is
976 * too low or because the rate tolerance is set too tightly; or the
977 * rounded rate upon success.
979 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
981 int m, n, r, e, scaled_max_m;
982 unsigned long scaled_rt_rp, new_rate;
983 int min_e = -1, min_e_m = -1, min_e_n = -1;
984 struct dpll_data *dd;
986 if (!clk || !clk->dpll_data)
991 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
992 "%ld\n", clk->name, target_rate);
994 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
995 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
997 dd->last_rounded_rate = 0;
999 for (n = dd->min_divider; n <= dd->max_divider; n++) {
1001 /* Is the (input clk, divider) pair valid for the DPLL? */
1002 r = _dpll_test_fint(clk, n);
1003 if (r == DPLL_FINT_UNDERFLOW)
1005 else if (r == DPLL_FINT_INVALID)
1008 /* Compute the scaled DPLL multiplier, based on the divider */
1009 m = scaled_rt_rp * n;
1012 * Since we're counting n up, a m overflow means we
1013 * can bail out completely (since as n increases in
1014 * the next iteration, there's no way that m can
1015 * increase beyond the current m)
1017 if (m > scaled_max_m)
1020 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
1023 /* m can't be set low enough for this n - try with a larger n */
1024 if (r == DPLL_MULT_UNDERFLOW)
1027 e = target_rate - new_rate;
1028 pr_debug("clock: n = %d: m = %d: rate error is %d "
1029 "(new_rate = %ld)\n", n, m, e, new_rate);
1032 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
1037 pr_debug("clock: found new least error %d\n", min_e);
1039 /* We found good settings -- bail out now */
1040 if (min_e <= dd->rate_tolerance)
1046 pr_debug("clock: error: target rate or tolerance too low\n");
1050 dd->last_rounded_m = min_e_m;
1051 dd->last_rounded_n = min_e_n;
1052 dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate,
1055 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
1056 min_e, min_e_m, min_e_n);
1057 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
1058 dd->last_rounded_rate, target_rate);
1060 return dd->last_rounded_rate;
1063 /*-------------------------------------------------------------------------
1064 * Omap2 clock reset and init functions
1065 *-------------------------------------------------------------------------*/
1067 #ifdef CONFIG_OMAP_RESET_CLOCKS
1068 void omap2_clk_disable_unused(struct clk *clk)
1072 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
1074 regval32 = _omap2_clk_read_reg(clk->enable_reg, clk);
1075 if ((regval32 & (1 << clk->enable_bit)) == v)
1078 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1079 _omap2_clk_disable(clk);
1083 int omap2_clk_register(struct clk *clk)
1085 if (!clk->clkdm.name) {
1086 pr_debug("clock: %s: missing clockdomain", clk->name);
1091 omap2_init_clk_clkdm(clk);