arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap24xx/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  19
  20 #include "prm.h"
  21 #include "cm.h"
  22 #include "prm_regbits_24xx.h"
  23 #include "cm_regbits_24xx.h"
  24
  25 static void omap2_sys_clk_recalc(struct clk * clk);
  26 static void omap2_clksel_recalc(struct clk * clk);
  27 static void omap2_followparent_recalc(struct clk * clk);
  28 static void omap2_propagate_rate(struct clk * clk);
  29 static void omap2_mpu_recalc(struct clk * clk);
  30 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  31 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  32 static void omap2_clk_disable(struct clk *clk);
  33 static void omap2_sys_clk_recalc(struct clk * clk);
  34 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
  35 static u32 omap2_clksel_get_divisor(struct clk *clk);
  36
  37 /* REVISIT: should use a clock flag for this, not a magic number */
  38 #define PARENT_CONTROLS_CLOCK   0xff
  39
  40 #define RATE_IN_242X    (1 << 0)
  41 #define RATE_IN_243X    (1 << 1)
  42 #define RATE_IN_343X    (1 << 2)
  43
  44 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  45  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  46  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  47  */
  48 struct prcm_config {
  49         unsigned long xtal_speed;       /* crystal rate */
  50         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  51         unsigned long mpu_speed;        /* speed of MPU */
  52         unsigned long cm_clksel_mpu;    /* mpu divider */
  53         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  54         unsigned long cm_clksel_gfx;    /* gfx dividers */
  55         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  56         unsigned long cm_clksel1_pll;   /* m,n */
  57         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  58         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  59         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  60         unsigned char flags;
  61 };
  62
  63 /* Mask for clksel which support parent settign in set_rate */
  64 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
  65                         CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
  66
  67 /* Mask for clksel regs which support rate operations */
  68 #define SRC_RATE_SEL_MASK (SRC_SEL_MASK | CM_MPU_SEL1 | CM_DSP_SEL1 | \
  69                         CM_GFX_SEL1 | CM_MODEM_SEL1)
  70
  71 /*
  72  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  73  * These configurations are characterized by voltage and speed for clocks.
  74  * The device is only validated for certain combinations. One way to express
  75  * these combinations is via the 'ratio's' which the clocks operate with
  76  * respect to each other. These ratio sets are for a given voltage/DPLL
  77  * setting. All configurations can be described by a DPLL setting and a ratio
  78  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  79  *
  80  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  81  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  82  * 2430 (iva2.1, NOdsp, mdm)
  83  */
  84
  85 /* Core fields for cm_clksel, not ratio governed */
  86 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  87 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  88 #define RX_CLKSEL_SSI                   (0x5 << 20)
  89
  90 /*-------------------------------------------------------------------------
  91  * Voltage/DPLL ratios
  92  *-------------------------------------------------------------------------*/
  93
  94 /* 2430 Ratio's, 2430-Ratio Config 1 */
  95 #define R1_CLKSEL_L3                    (4 << 0)
  96 #define R1_CLKSEL_L4                    (2 << 5)
  97 #define R1_CLKSEL_USB                   (4 << 25)
  98 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  99                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 100                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
 101 #define R1_CLKSEL_MPU                   (2 << 0)
 102 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 103 #define R1_CLKSEL_DSP                   (2 << 0)
 104 #define R1_CLKSEL_DSP_IF                (2 << 5)
 105 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 106 #define R1_CLKSEL_GFX                   (2 << 0)
 107 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 108 #define R1_CLKSEL_MDM                   (4 << 0)
 109 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 110
 111 /* 2430-Ratio Config 2 */
 112 #define R2_CLKSEL_L3                    (6 << 0)
 113 #define R2_CLKSEL_L4                    (2 << 5)
 114 #define R2_CLKSEL_USB                   (2 << 25)
 115 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 116                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 117                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 118 #define R2_CLKSEL_MPU                   (2 << 0)
 119 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 120 #define R2_CLKSEL_DSP                   (2 << 0)
 121 #define R2_CLKSEL_DSP_IF                (3 << 5)
 122 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 123 #define R2_CLKSEL_GFX                   (2 << 0)
 124 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 125 #define R2_CLKSEL_MDM                   (6 << 0)
 126 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 127
 128 /* 2430-Ratio Bootm (BYPASS) */
 129 #define RB_CLKSEL_L3                    (1 << 0)
 130 #define RB_CLKSEL_L4                    (1 << 5)
 131 #define RB_CLKSEL_USB                   (1 << 25)
 132 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 133                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 134                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 135 #define RB_CLKSEL_MPU                   (1 << 0)
 136 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 137 #define RB_CLKSEL_DSP                   (1 << 0)
 138 #define RB_CLKSEL_DSP_IF                (1 << 5)
 139 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 140 #define RB_CLKSEL_GFX                   (1 << 0)
 141 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 142 #define RB_CLKSEL_MDM                   (1 << 0)
 143 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 144
 145 /* 2420 Ratio Equivalents */
 146 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 147 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 148
 149 /* 2420-PRCM III 532MHz core */
 150 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 151 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 152 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 153 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 154                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 155                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 156                                         RIII_CLKSEL_L3
 157 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 158 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 159 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 160 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 161 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 162 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 163 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 164 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 165                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 166                                         RIII_CLKSEL_DSP
 167 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 168 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 169
 170 /* 2420-PRCM II 600MHz core */
 171 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 172 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 173 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 174 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 175                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 176                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 177                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 178 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 179 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 180 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 181 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 182 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 183 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 184 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 185 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 186                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 187                                         RII_CLKSEL_DSP
 188 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 189 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 190
 191 /* 2420-PRCM I 660MHz core */
 192 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 193 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 194 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 195 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 196                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 197                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 198                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 199 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 200 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 201 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 202 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 203 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 204 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 205 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 206 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 207                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 208                                         RI_CLKSEL_DSP
 209 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 210 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 211
 212 /* 2420-PRCM VII (boot) */
 213 #define RVII_CLKSEL_L3                  (1 << 0)
 214 #define RVII_CLKSEL_L4                  (1 << 5)
 215 #define RVII_CLKSEL_DSS1                (1 << 8)
 216 #define RVII_CLKSEL_DSS2                (0 << 13)
 217 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 218 #define RVII_CLKSEL_SSI                 (1 << 20)
 219 #define RVII_CLKSEL_USB                 (1 << 25)
 220
 221 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 222                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 223                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 224
 225 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 226 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 227
 228 #define RVII_CLKSEL_DSP                 (1 << 0)
 229 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 230 #define RVII_SYNC_DSP                   (0 << 7)
 231 #define RVII_CLKSEL_IVA                 (1 << 8)
 232 #define RVII_SYNC_IVA                   (0 << 13)
 233 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 234                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 235
 236 #define RVII_CLKSEL_GFX                 (1 << 0)
 237 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 238
 239 /*-------------------------------------------------------------------------
 240  * 2430 Target modes: Along with each configuration the CPU has several
 241  * modes which goes along with them. Modes mainly are the addition of
 242  * describe DPLL combinations to go along with a ratio.
 243  *-------------------------------------------------------------------------*/
 244
 245 /* Hardware governed */
 246 #define MX_48M_SRC                      (0 << 3)
 247 #define MX_54M_SRC                      (0 << 5)
 248 #define MX_APLLS_CLIKIN_12              (3 << 23)
 249 #define MX_APLLS_CLIKIN_13              (2 << 23)
 250 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 251
 252 /*
 253  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 254  * #2   (ratio1) baseport-target
 255  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 256  */
 257 #define M5A_DPLL_MULT_12                (133 << 12)
 258 #define M5A_DPLL_DIV_12                 (5 << 8)
 259 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 260                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 261                                         MX_APLLS_CLIKIN_12
 262 #define M5A_DPLL_MULT_13                (266 << 12)
 263 #define M5A_DPLL_DIV_13                 (12 << 8)
 264 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 265                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 266                                         MX_APLLS_CLIKIN_13
 267 #define M5A_DPLL_MULT_19                (180 << 12)
 268 #define M5A_DPLL_DIV_19                 (12 << 8)
 269 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 270                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 271                                         MX_APLLS_CLIKIN_19_2
 272 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 273 #define M5B_DPLL_MULT_12                (50 << 12)
 274 #define M5B_DPLL_DIV_12                 (2 << 8)
 275 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 276                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 277                                         MX_APLLS_CLIKIN_12
 278 #define M5B_DPLL_MULT_13                (200 << 12)
 279 #define M5B_DPLL_DIV_13                 (12 << 8)
 280
 281 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 282                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 283                                         MX_APLLS_CLIKIN_13
 284 #define M5B_DPLL_MULT_19                (125 << 12)
 285 #define M5B_DPLL_DIV_19                 (31 << 8)
 286 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 287                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 288                                         MX_APLLS_CLIKIN_19_2
 289 /*
 290  * #4   (ratio2)
 291  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 292  */
 293 #define M3_DPLL_MULT_12                 (55 << 12)
 294 #define M3_DPLL_DIV_12                  (1 << 8)
 295 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 296                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 297                                         MX_APLLS_CLIKIN_12
 298 #define M3_DPLL_MULT_13                 (330 << 12)
 299 #define M3_DPLL_DIV_13                  (12 << 8)
 300 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 301                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 302                                         MX_APLLS_CLIKIN_13
 303 #define M3_DPLL_MULT_19                 (275 << 12)
 304 #define M3_DPLL_DIV_19                  (15 << 8)
 305 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 306                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 307                                         MX_APLLS_CLIKIN_19_2
 308 /* boot (boot) */
 309 #define MB_DPLL_MULT                    (1 << 12)
 310 #define MB_DPLL_DIV                     (0 << 8)
 311 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 312                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 313
 314 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 315                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 316
 317 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 318                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 319
 320 /*
 321  * 2430 - chassis (sedna)
 322  * 165 (ratio1) same as above #2
 323  * 150 (ratio1)
 324  * 133 (ratio2) same as above #4
 325  * 110 (ratio2) same as above #3
 326  * 104 (ratio2)
 327  * boot (boot)
 328  */
 329
 330 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 331 #define MI_DPLL_MULT_12                 (55 << 12)
 332 #define MI_DPLL_DIV_12                  (1 << 8)
 333 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 334                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 335                                         MX_APLLS_CLIKIN_12
 336
 337 /*
 338  * 2420 Equivalent - mode registers
 339  * PRCM II , target DPLL = 2*300MHz = 600MHz
 340  */
 341 #define MII_DPLL_MULT_12                (50 << 12)
 342 #define MII_DPLL_DIV_12                 (1 << 8)
 343 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 344                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 345                                         MX_APLLS_CLIKIN_12
 346 #define MII_DPLL_MULT_13                (300 << 12)
 347 #define MII_DPLL_DIV_13                 (12 << 8)
 348 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 349                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 350                                         MX_APLLS_CLIKIN_13
 351
 352 /* PRCM III target DPLL = 2*266 = 532MHz*/
 353 #define MIII_DPLL_MULT_12               (133 << 12)
 354 #define MIII_DPLL_DIV_12                (5 << 8)
 355 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 356                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 357                                         MX_APLLS_CLIKIN_12
 358 #define MIII_DPLL_MULT_13               (266 << 12)
 359 #define MIII_DPLL_DIV_13                (12 << 8)
 360 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 361                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 362                                         MX_APLLS_CLIKIN_13
 363
 364 /* PRCM VII (boot bypass) */
 365 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 366 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 367
 368 /* High and low operation value */
 369 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 370 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 371
 372 /*
 373  * These represent optimal values for common parts, it won't work for all.
 374  * As long as you scale down, most parameters are still work, they just
 375  * become sub-optimal. The RFR value goes in the opposite direction. If you
 376  * don't adjust it down as your clock period increases the refresh interval
 377  * will not be met. Setting all parameters for complete worst case may work,
 378  * but may cut memory performance by 2x. Due to errata the DLLs need to be
 379  * unlocked and their value needs run time calibration. A dynamic call is
 380  * need for that as no single right value exists acorss production samples.
 381  *
 382  * Only the FULL speed values are given. Current code is such that rate
 383  * changes must be made at DPLLoutx2. The actual value adjustment for low
 384  * frequency operation will be handled by omap_set_performance()
 385  *
 386  * By having the boot loader boot up in the fastest L4 speed available likely
 387  * will result in something which you can switch between.
 388  */
 389 #define V24XX_SDRC_RFR_CTRL_165MHz      (0x00044c00 | 1)
 390 #define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
 391 #define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
 392 #define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
 393 #define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
 394
 395 /* MPU speed defines */
 396 #define S12M    12000000
 397 #define S13M    13000000
 398 #define S19M    19200000
 399 #define S26M    26000000
 400 #define S100M   100000000
 401 #define S133M   133000000
 402 #define S150M   150000000
 403 #define S165M   165000000
 404 #define S200M   200000000
 405 #define S266M   266000000
 406 #define S300M   300000000
 407 #define S330M   330000000
 408 #define S400M   400000000
 409 #define S532M   532000000
 410 #define S600M   600000000
 411 #define S660M   660000000
 412
 413 /*-------------------------------------------------------------------------
 414  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 415  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 416  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 417  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 418  *
 419  * Filling in table based on H4 boards and 2430-SDPs variants available.
 420  * There are quite a few more rates combinations which could be defined.
 421  *
 422  * When multiple values are defined the start up will try and choose the
 423  * fastest one. If a 'fast' value is defined, then automatically, the /2
 424  * one should be included as it can be used.    Generally having more that
 425  * one fast set does not make sense, as static timings need to be changed
 426  * to change the set.    The exception is the bypass setting which is
 427  * availble for low power bypass.
 428  *
 429  * Note: This table needs to be sorted, fastest to slowest.
 430  *-------------------------------------------------------------------------*/
 431 static struct prcm_config rate_table[] = {
 432         /* PRCM I - FAST */
 433         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 434                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 435                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 436                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
 437                 RATE_IN_242X},
 438
 439         /* PRCM II - FAST */
 440         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 441                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 442                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 443                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 444                 RATE_IN_242X},
 445
 446         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 447                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 448                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 449                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 450                 RATE_IN_242X},
 451
 452         /* PRCM III - FAST */
 453         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 454                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 455                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 456                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 457                 RATE_IN_242X},
 458
 459         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 460                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 461                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 462                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 463                 RATE_IN_242X},
 464
 465         /* PRCM II - SLOW */
 466         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 467                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 468                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 469                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 470                 RATE_IN_242X},
 471
 472         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 473                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 474                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 475                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
 476                 RATE_IN_242X},
 477
 478         /* PRCM III - SLOW */
 479         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 480                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 481                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 482                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 483                 RATE_IN_242X},
 484
 485         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 486                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 487                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 488                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
 489                 RATE_IN_242X},
 490
 491         /* PRCM-VII (boot-bypass) */
 492         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 493                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 494                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 495                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 496                 RATE_IN_242X},
 497
 498         /* PRCM-VII (boot-bypass) */
 499         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 500                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 501                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 502                 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
 503                 RATE_IN_242X},
 504
 505         /* PRCM #3 - ratio2 (ES2) - FAST */
 506         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 507                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 508                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 509                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 510                 V24XX_SDRC_RFR_CTRL_110MHz,
 511                 RATE_IN_243X},
 512
 513         /* PRCM #5a - ratio1 - FAST */
 514         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 515                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 516                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 517                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 518                 V24XX_SDRC_RFR_CTRL_133MHz,
 519                 RATE_IN_243X},
 520
 521         /* PRCM #5b - ratio1 - FAST */
 522         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 523                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 524                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 525                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 526                 V24XX_SDRC_RFR_CTRL_100MHz,
 527                 RATE_IN_243X},
 528
 529         /* PRCM #3 - ratio2 (ES2) - SLOW */
 530         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 531                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 532                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 533                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 534                 V24XX_SDRC_RFR_CTRL_110MHz,
 535                 RATE_IN_243X},
 536
 537         /* PRCM #5a - ratio1 - SLOW */
 538         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 539                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 540                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 541                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 542                 V24XX_SDRC_RFR_CTRL_133MHz,
 543                 RATE_IN_243X},
 544
 545         /* PRCM #5b - ratio1 - SLOW*/
 546         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 547                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 548                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 549                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 550                 V24XX_SDRC_RFR_CTRL_100MHz,
 551                 RATE_IN_243X},
 552
 553         /* PRCM-boot/bypass */
 554         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 555                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 556                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 557                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 558                 V24XX_SDRC_RFR_CTRL_BYPASS,
 559                 RATE_IN_243X},
 560
 561         /* PRCM-boot/bypass */
 562         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 563                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 564                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 565                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 566                 V24XX_SDRC_RFR_CTRL_BYPASS,
 567                 RATE_IN_243X},
 568
 569         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 570 };
 571
 572 /*-------------------------------------------------------------------------
 573  * 24xx clock tree.
 574  *
 575  * NOTE:In many cases here we are assigning a 'default' parent. In many
 576  *      cases the parent is selectable. The get/set parent calls will also
 577  *      switch sources.
 578  *
 579  *      Many some clocks say always_enabled, but they can be auto idled for
 580  *      power savings. They will always be available upon clock request.
 581  *
 582  *      Several sources are given initial rates which may be wrong, this will
 583  *      be fixed up in the init func.
 584  *
 585  *      Things are broadly separated below by clock domains. It is
 586  *      noteworthy that most periferals have dependencies on multiple clock
 587  *      domains. Many get their interface clocks from the L4 domain, but get
 588  *      functional clocks from fixed sources or other core domain derived
 589  *      clocks.
 590  *-------------------------------------------------------------------------*/
 591
 592 /* Base external input clocks */
 593 static struct clk func_32k_ck = {
 594         .name           = "func_32k_ck",
 595         .rate           = 32000,
 596         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 597                                 RATE_FIXED | ALWAYS_ENABLED,
 598 };
 599
 600 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 601 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 602         .name           = "osc_ck",
 603         .rate           = 26000000,             /* fixed up in clock init */
 604         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 605                                 RATE_FIXED | RATE_PROPAGATES,
 606 };
 607
 608 /* With out modem likely 12MHz, with modem likely 13MHz */
 609 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 610         .name           = "sys_ck",             /* ~ ref_clk also */
 611         .parent         = &osc_ck,
 612         .rate           = 13000000,
 613         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 614                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 615         .rate_offset    = OMAP_SYSCLKDIV_SHIFT, /* sysclkdiv 1 or 2, already handled or no boot */
 616         .recalc         = &omap2_sys_clk_recalc,
 617 };
 618
 619 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 620         .name           = "alt_ck",
 621         .rate           = 54000000,
 622         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 623                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 624         .recalc         = &omap2_propagate_rate,
 625 };
 626
 627 /*
 628  * Analog domain root source clocks
 629  */
 630
 631 /* dpll_ck, is broken out in to special cases through clksel */
 632 static struct clk dpll_ck = {
 633         .name           = "dpll_ck",
 634         .parent         = &sys_ck,              /* Can be func_32k also */
 635         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 636                                 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
 637         .recalc         = &omap2_clksel_recalc,
 638 };
 639
 640 static struct clk apll96_ck = {
 641         .name           = "apll96_ck",
 642         .parent         = &sys_ck,
 643         .rate           = 96000000,
 644         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 645                                 RATE_FIXED | RATE_PROPAGATES,
 646         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 647         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 648         .recalc         = &omap2_propagate_rate,
 649 };
 650
 651 static struct clk apll54_ck = {
 652         .name           = "apll54_ck",
 653         .parent         = &sys_ck,
 654         .rate           = 54000000,
 655         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 656                                 RATE_FIXED | RATE_PROPAGATES,
 657         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 658         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 659         .recalc         = &omap2_propagate_rate,
 660 };
 661
 662 /*
 663  * PRCM digital base sources
 664  */
 665 static struct clk func_54m_ck = {
 666         .name           = "func_54m_ck",
 667         .parent         = &apll54_ck,   /* can also be alt_clk */
 668         .rate           = 54000000,
 669         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 670                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 671         .src_offset     = OMAP24XX_54M_SOURCE_SHIFT,
 672         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 673         .enable_bit     = PARENT_CONTROLS_CLOCK,
 674         .recalc         = &omap2_propagate_rate,
 675 };
 676
 677 static struct clk core_ck = {
 678         .name           = "core_ck",
 679         .parent         = &dpll_ck,             /* can also be 32k */
 680         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 681                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 682         .recalc         = &omap2_propagate_rate,
 683 };
 684
 685 static struct clk func_96m_ck = {
 686         .name           = "func_96m_ck",
 687         .parent         = &apll96_ck,
 688         .rate           = 96000000,
 689         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 690                                 RATE_FIXED | RATE_PROPAGATES,
 691         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 692         .enable_bit     = PARENT_CONTROLS_CLOCK,
 693         .recalc         = &omap2_propagate_rate,
 694 };
 695
 696 static struct clk func_48m_ck = {
 697         .name           = "func_48m_ck",
 698         .parent         = &apll96_ck,    /* 96M or Alt */
 699         .rate           = 48000000,
 700         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 701                                 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 702         .src_offset     = OMAP24XX_48M_SOURCE_SHIFT,
 703         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 704         .enable_bit     = PARENT_CONTROLS_CLOCK,
 705         .recalc         = &omap2_propagate_rate,
 706 };
 707
 708 static struct clk func_12m_ck = {
 709         .name           = "func_12m_ck",
 710         .parent         = &func_48m_ck,
 711         .rate           = 12000000,
 712         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 713                                 RATE_FIXED | RATE_PROPAGATES,
 714         .recalc         = &omap2_propagate_rate,
 715         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 716         .enable_bit     = PARENT_CONTROLS_CLOCK,
 717 };
 718
 719 /* Secure timer, only available in secure mode */
 720 static struct clk wdt1_osc_ck = {
 721         .name           = "ck_wdt1_osc",
 722         .parent         = &osc_ck,
 723         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 724         .recalc         = &omap2_followparent_recalc,
 725 };
 726
 727 static struct clk sys_clkout = {
 728         .name           = "sys_clkout",
 729         .parent         = &func_54m_ck,
 730         .rate           = 54000000,
 731         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 732                                 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 733         .src_offset     = OMAP24XX_CLKOUT_SOURCE_SHIFT,
 734         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 735         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 736         .rate_offset    = OMAP24XX_CLKOUT_DIV_SHIFT,
 737         .recalc         = &omap2_clksel_recalc,
 738 };
 739
 740 /* In 2430, new in 2420 ES2 */
 741 static struct clk sys_clkout2 = {
 742         .name           = "sys_clkout2",
 743         .parent         = &func_54m_ck,
 744         .rate           = 54000000,
 745         .flags          = CLOCK_IN_OMAP242X | CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 746         .src_offset     = OMAP2420_CLKOUT2_SOURCE_SHIFT,
 747         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 748         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 749         .rate_offset    = OMAP2420_CLKOUT2_DIV_SHIFT,
 750         .recalc         = &omap2_clksel_recalc,
 751 };
 752
 753 static struct clk emul_ck = {
 754         .name           = "emul_ck",
 755         .parent         = &func_54m_ck,
 756         .flags          = CLOCK_IN_OMAP242X,
 757         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 758         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 759         .recalc         = &omap2_propagate_rate,
 760
 761 };
 762
 763 /*
 764  * MPU clock domain
 765  *      Clocks:
 766  *              MPU_FCLK, MPU_ICLK
 767  *              INT_M_FCLK, INT_M_I_CLK
 768  *
 769  * - Individual clocks are hardware managed.
 770  * - Base divider comes from: CM_CLKSEL_MPU
 771  *
 772  */
 773 static struct clk mpu_ck = {    /* Control cpu */
 774         .name           = "mpu_ck",
 775         .parent         = &core_ck,
 776         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
 777                                 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
 778                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 779         .rate_offset    = OMAP24XX_CLKSEL_MPU_SHIFT,    /* bits 0-4 */
 780         .recalc         = &omap2_clksel_recalc,
 781 };
 782
 783 /*
 784  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 785  * Clocks:
 786  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 787  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 788  */
 789 static struct clk iva2_1_fck = {
 790         .name           = "iva2_1_fck",
 791         .parent         = &core_ck,
 792         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 793                                 DELAYED_APP | RATE_PROPAGATES |
 794                                 CONFIG_PARTICIPANT,
 795         .rate_offset    = OMAP24XX_CLKSEL_DSP_SHIFT,
 796         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 797         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 798         .recalc         = &omap2_clksel_recalc,
 799 };
 800
 801 static struct clk iva2_1_ick = {
 802         .name           = "iva2_1_ick",
 803         .parent         = &iva2_1_fck,
 804         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
 805                                 DELAYED_APP | CONFIG_PARTICIPANT,
 806         .rate_offset    = OMAP24XX_CLKSEL_DSP_IF_SHIFT,
 807         .recalc         = &omap2_clksel_recalc,
 808 };
 809
 810 /*
 811  * Won't be too specific here. The core clock comes into this block
 812  * it is divided then tee'ed. One branch goes directly to xyz enable
 813  * controls. The other branch gets further divided by 2 then possibly
 814  * routed into a synchronizer and out of clocks abc.
 815  */
 816 static struct clk dsp_fck = {
 817         .name           = "dsp_fck",
 818         .parent         = &core_ck,
 819         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 820                         DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
 821         .rate_offset    = OMAP24XX_CLKSEL_DSP_SHIFT,
 822         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 823         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 824         .recalc         = &omap2_clksel_recalc,
 825 };
 826
 827 static struct clk dsp_ick = {
 828         .name           = "dsp_ick",     /* apparently ipi and isp */
 829         .parent         = &dsp_fck,
 830         .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 831                                 DELAYED_APP | CONFIG_PARTICIPANT,
 832         .rate_offset    = OMAP24XX_CLKSEL_DSP_IF_SHIFT,
 833         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 834         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
 835         .recalc         = &omap2_clksel_recalc,
 836 };
 837
 838 static struct clk iva1_ifck = {
 839         .name           = "iva1_ifck",
 840         .parent         = &core_ck,
 841         .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
 842                         CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
 843         .rate_offset    = OMAP2420_CLKSEL_IVA_SHIFT,
 844         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 845         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
 846         .recalc         = &omap2_clksel_recalc,
 847 };
 848
 849 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 850 static struct clk iva1_mpu_int_ifck = {
 851         .name           = "iva1_mpu_int_ifck",
 852         .parent         = &iva1_ifck,
 853         .flags          = CLOCK_IN_OMAP242X,
 854         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 855         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
 856         .recalc         = &omap2_clksel_recalc,
 857 };
 858
 859 /*
 860  * L3 clock domain
 861  * L3 clocks are used for both interface and functional clocks to
 862  * multiple entities. Some of these clocks are completely managed
 863  * by hardware, and some others allow software control. Hardware
 864  * managed ones general are based on directly CLK_REQ signals and
 865  * various auto idle settings. The functional spec sets many of these
 866  * as 'tie-high' for their enables.
 867  *
 868  * I-CLOCKS:
 869  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 870  *      CAM, HS-USB.
 871  * F-CLOCK
 872  *      SSI.
 873  *
 874  * GPMC memories and SDRC have timing and clock sensitive registers which
 875  * may very well need notification when the clock changes. Currently for low
 876  * operating points, these are taken care of in sleep.S.
 877  */
 878 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 879         .name           = "core_l3_ck",
 880         .parent         = &core_ck,
 881         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 882                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
 883                                 DELAYED_APP | CONFIG_PARTICIPANT |
 884                                 RATE_PROPAGATES,
 885         .rate_offset    = OMAP24XX_CLKSEL_L3_SHIFT,
 886         .recalc         = &omap2_clksel_recalc,
 887 };
 888
 889 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 890         .name           = "usb_l4_ick",
 891         .parent         = &core_l3_ck,
 892         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 893                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
 894                                 CONFIG_PARTICIPANT,
 895         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 896         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
 897         .rate_offset    = OMAP24XX_CLKSEL_USB_SHIFT,
 898         .recalc         = &omap2_clksel_recalc,
 899 };
 900
 901 /*
 902  * SSI is in L3 management domain, its direct parent is core not l3,
 903  * many core power domain entities are grouped into the L3 clock
 904  * domain.
 905  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
 906  *
 907  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 908  */
 909 static struct clk ssi_ssr_sst_fck = {
 910         .name           = "ssi_fck",
 911         .parent         = &core_ck,
 912         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 913                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
 914         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
 915         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 916         .rate_offset    = OMAP24XX_CLKSEL_SSI_SHIFT,
 917         .recalc         = &omap2_clksel_recalc,
 918 };
 919
 920 /*
 921  * GFX clock domain
 922  *      Clocks:
 923  * GFX_FCLK, GFX_ICLK
 924  * GFX_CG1(2d), GFX_CG2(3d)
 925  *
 926  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 927  * The 2d and 3d clocks run at a hardware determined
 928  * divided value of fclk.
 929  *
 930  */
 931 static struct clk gfx_3d_fck = {
 932         .name           = "gfx_3d_fck",
 933         .parent         = &core_l3_ck,
 934         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 935                                 RATE_CKCTL | CM_GFX_SEL1,
 936         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 937         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
 938         .rate_offset    = OMAP_CLKSEL_GFX_SHIFT,
 939         .recalc         = &omap2_clksel_recalc,
 940 };
 941
 942 static struct clk gfx_2d_fck = {
 943         .name           = "gfx_2d_fck",
 944         .parent         = &core_l3_ck,
 945         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 946                                 RATE_CKCTL | CM_GFX_SEL1,
 947         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 948         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
 949         .rate_offset    = OMAP_CLKSEL_GFX_SHIFT,
 950         .recalc         = &omap2_clksel_recalc,
 951 };
 952
 953 static struct clk gfx_ick = {
 954         .name           = "gfx_ick",            /* From l3 */
 955         .parent         = &core_l3_ck,
 956         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 957         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
 958         .enable_bit     = OMAP_EN_GFX_SHIFT,
 959         .recalc         = &omap2_followparent_recalc,
 960 };
 961
 962 /*
 963  * Modem clock domain (2430)
 964  *      CLOCKS:
 965  *              MDM_OSC_CLK
 966  *              MDM_ICLK
 967  */
 968 static struct clk mdm_ick = {           /* used both as a ick and fck */
 969         .name           = "mdm_ick",
 970         .parent         = &core_ck,
 971         .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
 972                                 DELAYED_APP | CONFIG_PARTICIPANT,
 973         .rate_offset    = OMAP2430_CLKSEL_MDM_SHIFT,
 974         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
 975         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
 976         .recalc         = &omap2_clksel_recalc,
 977 };
 978
 979 static struct clk mdm_osc_ck = {
 980         .name           = "mdm_osc_ck",
 981         .rate           = 26000000,
 982         .parent         = &osc_ck,
 983         .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
 984         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
 985         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
 986         .recalc         = &omap2_followparent_recalc,
 987 };
 988
 989 /*
 990  * L4 clock management domain
 991  *
 992  * This domain contains lots of interface clocks from the L4 interface, some
 993  * functional clocks.   Fixed APLL functional source clocks are managed in
 994  * this domain.
 995  */
 996 static struct clk l4_ck = {             /* used both as an ick and fck */
 997         .name           = "l4_ck",
 998         .parent         = &core_l3_ck,
 999         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1000                                 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
1001                                 DELAYED_APP | RATE_PROPAGATES,
1002         .rate_offset    = OMAP24XX_CLKSEL_L4_SHIFT,
1003         .recalc         = &omap2_clksel_recalc,
1004 };
1005
1006 static struct clk ssi_l4_ick = {
1007         .name           = "ssi_l4_ick",
1008         .parent         = &l4_ck,
1009         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1010         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1011         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1012         .recalc         = &omap2_followparent_recalc,
1013 };
1014
1015 /*
1016  * DSS clock domain
1017  * CLOCKs:
1018  * DSS_L4_ICLK, DSS_L3_ICLK,
1019  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1020  *
1021  * DSS is both initiator and target.
1022  */
1023 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1024         .name           = "dss_ick",
1025         .parent         = &l4_ck,       /* really both l3 and l4 */
1026         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1027         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1028         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1029         .recalc         = &omap2_followparent_recalc,
1030 };
1031
1032 static struct clk dss1_fck = {
1033         .name           = "dss1_fck",
1034         .parent         = &core_ck,             /* Core or sys */
1035         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1036                                 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1037         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1038         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1039         .rate_offset    = OMAP24XX_CLKSEL_DSS1_SHIFT,
1040         .src_offset     = OMAP24XX_CLKSEL_DSS1_SHIFT,
1041         .recalc         = &omap2_clksel_recalc,
1042 };
1043
1044 static struct clk dss2_fck = {          /* Alt clk used in power management */
1045         .name           = "dss2_fck",
1046         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1047         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1048                                 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
1049                                 DELAYED_APP,
1050         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1051         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1052         .src_offset     = OMAP24XX_CLKSEL_DSS2_SHIFT,
1053         .recalc         = &omap2_followparent_recalc,
1054 };
1055
1056 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1057         .name           = "dss_54m_fck",        /* 54m tv clk */
1058         .parent         = &func_54m_ck,
1059         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1060         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1061         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1062         .recalc         = &omap2_followparent_recalc,
1063 };
1064
1065 /*
1066  * CORE power domain ICLK & FCLK defines.
1067  * Many of the these can have more than one possible parent. Entries
1068  * here will likely have an L4 interface parent, and may have multiple
1069  * functional clock parents.
1070  */
1071 static struct clk gpt1_ick = {
1072         .name           = "gpt1_ick",
1073         .parent         = &l4_ck,
1074         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1075         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1076         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1077         .recalc         = &omap2_followparent_recalc,
1078 };
1079
1080 static struct clk gpt1_fck = {
1081         .name           = "gpt1_fck",
1082         .parent         = &func_32k_ck,
1083         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1084                                 CM_WKUP_SEL1,
1085         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1086         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1087         .src_offset     = OMAP24XX_CLKSEL_GPT1_SHIFT,
1088         .recalc         = &omap2_followparent_recalc,
1089 };
1090
1091 static struct clk gpt2_ick = {
1092         .name           = "gpt2_ick",
1093         .parent         = &l4_ck,
1094         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1095         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1096         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1097         .recalc         = &omap2_followparent_recalc,
1098 };
1099
1100 static struct clk gpt2_fck = {
1101         .name           = "gpt2_fck",
1102         .parent         = &func_32k_ck,
1103         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1104                                 CM_CORE_SEL2,
1105         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1106         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1107         .src_offset     = OMAP24XX_CLKSEL_GPT2_SHIFT,
1108         .recalc         = &omap2_followparent_recalc,
1109 };
1110
1111 static struct clk gpt3_ick = {
1112         .name           = "gpt3_ick",
1113         .parent         = &l4_ck,
1114         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1115         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1116         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1117         .recalc         = &omap2_followparent_recalc,
1118 };
1119
1120 static struct clk gpt3_fck = {
1121         .name           = "gpt3_fck",
1122         .parent         = &func_32k_ck,
1123         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1124                                 CM_CORE_SEL2,
1125         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1126         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1127         .src_offset     = OMAP24XX_CLKSEL_GPT3_SHIFT,
1128         .recalc         = &omap2_followparent_recalc,
1129 };
1130
1131 static struct clk gpt4_ick = {
1132         .name           = "gpt4_ick",
1133         .parent         = &l4_ck,
1134         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1135         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1136         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1137         .recalc         = &omap2_followparent_recalc,
1138 };
1139
1140 static struct clk gpt4_fck = {
1141         .name           = "gpt4_fck",
1142         .parent         = &func_32k_ck,
1143         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1144                                 CM_CORE_SEL2,
1145         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1146         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1147         .src_offset     = OMAP24XX_CLKSEL_GPT4_SHIFT,
1148         .recalc         = &omap2_followparent_recalc,
1149 };
1150
1151 static struct clk gpt5_ick = {
1152         .name           = "gpt5_ick",
1153         .parent         = &l4_ck,
1154         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1155         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1156         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1157         .recalc         = &omap2_followparent_recalc,
1158 };
1159
1160 static struct clk gpt5_fck = {
1161         .name           = "gpt5_fck",
1162         .parent         = &func_32k_ck,
1163         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1164                                 CM_CORE_SEL2,
1165         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1166         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1167         .src_offset     = OMAP24XX_CLKSEL_GPT5_SHIFT,
1168         .recalc         = &omap2_followparent_recalc,
1169 };
1170
1171 static struct clk gpt6_ick = {
1172         .name           = "gpt6_ick",
1173         .parent         = &l4_ck,
1174         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1175         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1176         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1177         .recalc         = &omap2_followparent_recalc,
1178 };
1179
1180 static struct clk gpt6_fck = {
1181         .name           = "gpt6_fck",
1182         .parent         = &func_32k_ck,
1183         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1184                                 CM_CORE_SEL2,
1185         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1186         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1187         .src_offset     = OMAP24XX_CLKSEL_GPT6_SHIFT,
1188         .recalc         = &omap2_followparent_recalc,
1189 };
1190
1191 static struct clk gpt7_ick = {
1192         .name           = "gpt7_ick",
1193         .parent         = &l4_ck,
1194         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1195         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1196         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1197         .recalc         = &omap2_followparent_recalc,
1198 };
1199
1200 static struct clk gpt7_fck = {
1201         .name           = "gpt7_fck",
1202         .parent         = &func_32k_ck,
1203         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1204                                 CM_CORE_SEL2,
1205         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1206         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1207         .src_offset     = OMAP24XX_CLKSEL_GPT7_SHIFT,
1208         .recalc         = &omap2_followparent_recalc,
1209 };
1210
1211 static struct clk gpt8_ick = {
1212         .name           = "gpt8_ick",
1213         .parent         = &l4_ck,
1214         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1215         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1216         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1217         .recalc         = &omap2_followparent_recalc,
1218 };
1219
1220 static struct clk gpt8_fck = {
1221         .name           = "gpt8_fck",
1222         .parent         = &func_32k_ck,
1223         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1224                                 CM_CORE_SEL2,
1225         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1226         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1227         .src_offset     = OMAP24XX_CLKSEL_GPT8_SHIFT,
1228         .recalc         = &omap2_followparent_recalc,
1229 };
1230
1231 static struct clk gpt9_ick = {
1232         .name           = "gpt9_ick",
1233         .parent         = &l4_ck,
1234         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1235         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1236         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1237         .recalc         = &omap2_followparent_recalc,
1238 };
1239
1240 static struct clk gpt9_fck = {
1241         .name           = "gpt9_fck",
1242         .parent         = &func_32k_ck,
1243         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1244                                         CM_CORE_SEL2,
1245         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1246         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1247         .src_offset     = OMAP24XX_CLKSEL_GPT9_SHIFT,
1248         .recalc         = &omap2_followparent_recalc,
1249 };
1250
1251 static struct clk gpt10_ick = {
1252         .name           = "gpt10_ick",
1253         .parent         = &l4_ck,
1254         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1255         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1256         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1257         .recalc         = &omap2_followparent_recalc,
1258 };
1259
1260 static struct clk gpt10_fck = {
1261         .name           = "gpt10_fck",
1262         .parent         = &func_32k_ck,
1263         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1264                                         CM_CORE_SEL2,
1265         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1266         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1267         .src_offset     = OMAP24XX_CLKSEL_GPT10_SHIFT,
1268         .recalc         = &omap2_followparent_recalc,
1269 };
1270
1271 static struct clk gpt11_ick = {
1272         .name           = "gpt11_ick",
1273         .parent         = &l4_ck,
1274         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1275         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1276         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1277         .recalc         = &omap2_followparent_recalc,
1278 };
1279
1280 static struct clk gpt11_fck = {
1281         .name           = "gpt11_fck",
1282         .parent         = &func_32k_ck,
1283         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1284                                         CM_CORE_SEL2,
1285         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1286         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1287         .src_offset     = OMAP24XX_CLKSEL_GPT11_SHIFT,
1288         .recalc         = &omap2_followparent_recalc,
1289 };
1290
1291 static struct clk gpt12_ick = {
1292         .name           = "gpt12_ick",
1293         .parent         = &l4_ck,
1294         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1295         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1296         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1297         .recalc         = &omap2_followparent_recalc,
1298 };
1299
1300 static struct clk gpt12_fck = {
1301         .name           = "gpt12_fck",
1302         .parent         = &func_32k_ck,
1303         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1304                                         CM_CORE_SEL2,
1305         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1306         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1307         .src_offset     = OMAP24XX_CLKSEL_GPT12_SHIFT,
1308         .recalc         = &omap2_followparent_recalc,
1309 };
1310
1311 /* REVISIT: bit comment below wrong? */
1312 static struct clk mcbsp1_ick = {
1313         .name           = "mcbsp1_ick",
1314         .parent         = &l4_ck,
1315         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1316         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit16 */
1317         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1318         .recalc         = &omap2_followparent_recalc,
1319 };
1320
1321 static struct clk mcbsp1_fck = {
1322         .name           = "mcbsp1_fck",
1323         .parent         = &func_96m_ck,
1324         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1325         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1326         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1327         .recalc         = &omap2_followparent_recalc,
1328 };
1329
1330 static struct clk mcbsp2_ick = {
1331         .name           = "mcbsp2_ick",
1332         .parent         = &l4_ck,
1333         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1334         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1335         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1336         .recalc         = &omap2_followparent_recalc,
1337 };
1338
1339 static struct clk mcbsp2_fck = {
1340         .name           = "mcbsp2_fck",
1341         .parent         = &func_96m_ck,
1342         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1343         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1344         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1345         .recalc         = &omap2_followparent_recalc,
1346 };
1347
1348 static struct clk mcbsp3_ick = {
1349         .name           = "mcbsp3_ick",
1350         .parent         = &l4_ck,
1351         .flags          = CLOCK_IN_OMAP243X,
1352         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1353         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1354         .recalc         = &omap2_followparent_recalc,
1355 };
1356
1357 static struct clk mcbsp3_fck = {
1358         .name           = "mcbsp3_fck",
1359         .parent         = &func_96m_ck,
1360         .flags          = CLOCK_IN_OMAP243X,
1361         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1362         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1363         .recalc         = &omap2_followparent_recalc,
1364 };
1365
1366 static struct clk mcbsp4_ick = {
1367         .name           = "mcbsp4_ick",
1368         .parent         = &l4_ck,
1369         .flags          = CLOCK_IN_OMAP243X,
1370         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1371         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1372         .recalc         = &omap2_followparent_recalc,
1373 };
1374
1375 static struct clk mcbsp4_fck = {
1376         .name           = "mcbsp4_fck",
1377         .parent         = &func_96m_ck,
1378         .flags          = CLOCK_IN_OMAP243X,
1379         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1380         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1381         .recalc         = &omap2_followparent_recalc,
1382 };
1383
1384 static struct clk mcbsp5_ick = {
1385         .name           = "mcbsp5_ick",
1386         .parent         = &l4_ck,
1387         .flags          = CLOCK_IN_OMAP243X,
1388         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1389         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1390         .recalc         = &omap2_followparent_recalc,
1391 };
1392
1393 static struct clk mcbsp5_fck = {
1394         .name           = "mcbsp5_fck",
1395         .parent         = &func_96m_ck,
1396         .flags          = CLOCK_IN_OMAP243X,
1397         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1398         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1399         .recalc         = &omap2_followparent_recalc,
1400 };
1401
1402 static struct clk mcspi1_ick = {
1403         .name           = "mcspi_ick",
1404         .id             = 1,
1405         .parent         = &l4_ck,
1406         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1407         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1408         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1409         .recalc         = &omap2_followparent_recalc,
1410 };
1411
1412 static struct clk mcspi1_fck = {
1413         .name           = "mcspi_fck",
1414         .id             = 1,
1415         .parent         = &func_48m_ck,
1416         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1417         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1418         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1419         .recalc         = &omap2_followparent_recalc,
1420 };
1421
1422 static struct clk mcspi2_ick = {
1423         .name           = "mcspi_ick",
1424         .id             = 2,
1425         .parent         = &l4_ck,
1426         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1427         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1428         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1429         .recalc         = &omap2_followparent_recalc,
1430 };
1431
1432 static struct clk mcspi2_fck = {
1433         .name           = "mcspi_fck",
1434         .id             = 2,
1435         .parent         = &func_48m_ck,
1436         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1437         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1438         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1439         .recalc         = &omap2_followparent_recalc,
1440 };
1441
1442 static struct clk mcspi3_ick = {
1443         .name           = "mcspi_ick",
1444         .id             = 3,
1445         .parent         = &l4_ck,
1446         .flags          = CLOCK_IN_OMAP243X,
1447         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1448         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1449         .recalc         = &omap2_followparent_recalc,
1450 };
1451
1452 static struct clk mcspi3_fck = {
1453         .name           = "mcspi_fck",
1454         .id             = 3,
1455         .parent         = &func_48m_ck,
1456         .flags          = CLOCK_IN_OMAP243X,
1457         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1458         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1459         .recalc         = &omap2_followparent_recalc,
1460 };
1461
1462 static struct clk uart1_ick = {
1463         .name           = "uart1_ick",
1464         .parent         = &l4_ck,
1465         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1466         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1467         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1468         .recalc         = &omap2_followparent_recalc,
1469 };
1470
1471 static struct clk uart1_fck = {
1472         .name           = "uart1_fck",
1473         .parent         = &func_48m_ck,
1474         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1475         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1476         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1477         .recalc         = &omap2_followparent_recalc,
1478 };
1479
1480 static struct clk uart2_ick = {
1481         .name           = "uart2_ick",
1482         .parent         = &l4_ck,
1483         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1484         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1485         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1486         .recalc         = &omap2_followparent_recalc,
1487 };
1488
1489 static struct clk uart2_fck = {
1490         .name           = "uart2_fck",
1491         .parent         = &func_48m_ck,
1492         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1493         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1494         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1495         .recalc         = &omap2_followparent_recalc,
1496 };
1497
1498 static struct clk uart3_ick = {
1499         .name           = "uart3_ick",
1500         .parent         = &l4_ck,
1501         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1502         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1503         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1504         .recalc         = &omap2_followparent_recalc,
1505 };
1506
1507 static struct clk uart3_fck = {
1508         .name           = "uart3_fck",
1509         .parent         = &func_48m_ck,
1510         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1511         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1512         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1513         .recalc         = &omap2_followparent_recalc,
1514 };
1515
1516 static struct clk gpios_ick = {
1517         .name           = "gpios_ick",
1518         .parent         = &l4_ck,
1519         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1520         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1521         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1522         .recalc         = &omap2_followparent_recalc,
1523 };
1524
1525 static struct clk gpios_fck = {
1526         .name           = "gpios_fck",
1527         .parent         = &func_32k_ck,
1528         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1529         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1530         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1531         .recalc         = &omap2_followparent_recalc,
1532 };
1533
1534 static struct clk mpu_wdt_ick = {
1535         .name           = "mpu_wdt_ick",
1536         .parent         = &l4_ck,
1537         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1538         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1539         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1540         .recalc         = &omap2_followparent_recalc,
1541 };
1542
1543 static struct clk mpu_wdt_fck = {
1544         .name           = "mpu_wdt_fck",
1545         .parent         = &func_32k_ck,
1546         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1547         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1548         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1549         .recalc         = &omap2_followparent_recalc,
1550 };
1551
1552 static struct clk sync_32k_ick = {
1553         .name           = "sync_32k_ick",
1554         .parent         = &l4_ck,
1555         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1556         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1557         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1558         .recalc         = &omap2_followparent_recalc,
1559 };
1560 static struct clk wdt1_ick = {
1561         .name           = "wdt1_ick",
1562         .parent         = &l4_ck,
1563         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1564         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1565         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1566         .recalc         = &omap2_followparent_recalc,
1567 };
1568 static struct clk omapctrl_ick = {
1569         .name           = "omapctrl_ick",
1570         .parent         = &l4_ck,
1571         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1572         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1573         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
1574         .recalc         = &omap2_followparent_recalc,
1575 };
1576 static struct clk icr_ick = {
1577         .name           = "icr_ick",
1578         .parent         = &l4_ck,
1579         .flags          = CLOCK_IN_OMAP243X,
1580         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1581         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
1582         .recalc         = &omap2_followparent_recalc,
1583 };
1584
1585 static struct clk cam_ick = {
1586         .name           = "cam_ick",
1587         .parent         = &l4_ck,
1588         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1589         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1590         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1591         .recalc         = &omap2_followparent_recalc,
1592 };
1593
1594 static struct clk cam_fck = {
1595         .name           = "cam_fck",
1596         .parent         = &func_96m_ck,
1597         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1598         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1600         .recalc         = &omap2_followparent_recalc,
1601 };
1602
1603 static struct clk mailboxes_ick = {
1604         .name           = "mailboxes_ick",
1605         .parent         = &l4_ck,
1606         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1607         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1608         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
1609         .recalc         = &omap2_followparent_recalc,
1610 };
1611
1612 static struct clk wdt4_ick = {
1613         .name           = "wdt4_ick",
1614         .parent         = &l4_ck,
1615         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1616         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1617         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1618         .recalc         = &omap2_followparent_recalc,
1619 };
1620
1621 static struct clk wdt4_fck = {
1622         .name           = "wdt4_fck",
1623         .parent         = &func_32k_ck,
1624         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1625         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1626         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1627         .recalc         = &omap2_followparent_recalc,
1628 };
1629
1630 static struct clk wdt3_ick = {
1631         .name           = "wdt3_ick",
1632         .parent         = &l4_ck,
1633         .flags          = CLOCK_IN_OMAP242X,
1634         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1635         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1636         .recalc         = &omap2_followparent_recalc,
1637 };
1638
1639 static struct clk wdt3_fck = {
1640         .name           = "wdt3_fck",
1641         .parent         = &func_32k_ck,
1642         .flags          = CLOCK_IN_OMAP242X,
1643         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1644         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1645         .recalc         = &omap2_followparent_recalc,
1646 };
1647
1648 static struct clk mspro_ick = {
1649         .name           = "mspro_ick",
1650         .parent         = &l4_ck,
1651         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1652         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1653         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1654         .recalc         = &omap2_followparent_recalc,
1655 };
1656
1657 static struct clk mspro_fck = {
1658         .name           = "mspro_fck",
1659         .parent         = &func_96m_ck,
1660         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1661         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1662         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1663         .recalc         = &omap2_followparent_recalc,
1664 };
1665
1666 static struct clk mmc_ick = {
1667         .name           = "mmc_ick",
1668         .parent         = &l4_ck,
1669         .flags          = CLOCK_IN_OMAP242X,
1670         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1671         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1672         .recalc         = &omap2_followparent_recalc,
1673 };
1674
1675 static struct clk mmc_fck = {
1676         .name           = "mmc_fck",
1677         .parent         = &func_96m_ck,
1678         .flags          = CLOCK_IN_OMAP242X,
1679         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1680         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1681         .recalc         = &omap2_followparent_recalc,
1682 };
1683
1684 static struct clk fac_ick = {
1685         .name           = "fac_ick",
1686         .parent         = &l4_ck,
1687         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1688         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1689         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1690         .recalc         = &omap2_followparent_recalc,
1691 };
1692
1693 static struct clk fac_fck = {
1694         .name           = "fac_fck",
1695         .parent         = &func_12m_ck,
1696         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1697         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1698         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1699         .recalc         = &omap2_followparent_recalc,
1700 };
1701
1702 static struct clk eac_ick = {
1703         .name           = "eac_ick",
1704         .parent         = &l4_ck,
1705         .flags          = CLOCK_IN_OMAP242X,
1706         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1707         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1708         .recalc         = &omap2_followparent_recalc,
1709 };
1710
1711 static struct clk eac_fck = {
1712         .name           = "eac_fck",
1713         .parent         = &func_96m_ck,
1714         .flags          = CLOCK_IN_OMAP242X,
1715         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1716         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1717         .recalc         = &omap2_followparent_recalc,
1718 };
1719
1720 static struct clk hdq_ick = {
1721         .name           = "hdq_ick",
1722         .parent         = &l4_ck,
1723         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1724         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1725         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1726         .recalc         = &omap2_followparent_recalc,
1727 };
1728
1729 static struct clk hdq_fck = {
1730         .name           = "hdq_fck",
1731         .parent         = &func_12m_ck,
1732         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1733         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1734         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1735         .recalc         = &omap2_followparent_recalc,
1736 };
1737
1738 static struct clk i2c2_ick = {
1739         .name           = "i2c_ick",
1740         .id             = 2,
1741         .parent         = &l4_ck,
1742         .flags          = CLOCK_IN_OMAP242X,
1743         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1744         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1745         .recalc         = &omap2_followparent_recalc,
1746 };
1747
1748 static struct clk i2c2_fck = {
1749         .name           = "i2c_fck",
1750         .id             = 2,
1751         .parent         = &func_12m_ck,
1752         .flags          = CLOCK_IN_OMAP242X,
1753         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1754         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1755         .recalc         = &omap2_followparent_recalc,
1756 };
1757
1758 static struct clk i2chs2_fck = {
1759         .name           = "i2chs_fck",
1760         .id             = 2,
1761         .parent         = &func_96m_ck,
1762         .flags          = CLOCK_IN_OMAP243X,
1763         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1764         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
1765         .recalc         = &omap2_followparent_recalc,
1766 };
1767
1768 static struct clk i2c1_ick = {
1769         .name           = "i2c_ick",
1770         .id             = 1,
1771         .parent         = &l4_ck,
1772         .flags          = CLOCK_IN_OMAP242X,
1773         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1774         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1775         .recalc         = &omap2_followparent_recalc,
1776 };
1777
1778 static struct clk i2c1_fck = {
1779         .name           = "i2c_fck",
1780         .id             = 1,
1781         .parent         = &func_12m_ck,
1782         .flags          = CLOCK_IN_OMAP242X,
1783         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1784         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1785         .recalc         = &omap2_followparent_recalc,
1786 };
1787
1788 static struct clk i2chs1_fck = {
1789         .name           = "i2chs_fck",
1790         .id             = 1,
1791         .parent         = &func_96m_ck,
1792         .flags          = CLOCK_IN_OMAP243X,
1793         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1794         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
1795         .recalc         = &omap2_followparent_recalc,
1796 };
1797
1798 static struct clk vlynq_ick = {
1799         .name           = "vlynq_ick",
1800         .parent         = &core_l3_ck,
1801         .flags          = CLOCK_IN_OMAP242X,
1802         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1803         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1804         .recalc         = &omap2_followparent_recalc,
1805 };
1806
1807 static struct clk vlynq_fck = {
1808         .name           = "vlynq_fck",
1809         .parent         = &func_96m_ck,
1810         .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1811         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1812         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1813         .src_offset     = OMAP2420_CLKSEL_VLYNQ_SHIFT,
1814         .recalc         = &omap2_clksel_recalc,
1815 };
1816
1817 static struct clk sdrc_ick = {
1818         .name           = "sdrc_ick",
1819         .parent         = &l4_ck,
1820         .flags          = CLOCK_IN_OMAP243X,
1821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
1822         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
1823         .recalc         = &omap2_followparent_recalc,
1824 };
1825
1826 static struct clk des_ick = {
1827         .name           = "des_ick",
1828         .parent         = &l4_ck,
1829         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1830         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1831         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
1832         .recalc         = &omap2_followparent_recalc,
1833 };
1834
1835 static struct clk sha_ick = {
1836         .name           = "sha_ick",
1837         .parent         = &l4_ck,
1838         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1839         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1840         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
1841         .recalc         = &omap2_followparent_recalc,
1842 };
1843
1844 static struct clk rng_ick = {
1845         .name           = "rng_ick",
1846         .parent         = &l4_ck,
1847         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1848         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1849         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
1850         .recalc         = &omap2_followparent_recalc,
1851 };
1852
1853 static struct clk aes_ick = {
1854         .name           = "aes_ick",
1855         .parent         = &l4_ck,
1856         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1857         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1858         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
1859         .recalc         = &omap2_followparent_recalc,
1860 };
1861
1862 static struct clk pka_ick = {
1863         .name           = "pka_ick",
1864         .parent         = &l4_ck,
1865         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1866         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1867         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
1868         .recalc         = &omap2_followparent_recalc,
1869 };
1870
1871 static struct clk usb_fck = {
1872         .name           = "usb_fck",
1873         .parent         = &func_48m_ck,
1874         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1875         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1876         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1877         .recalc         = &omap2_followparent_recalc,
1878 };
1879
1880 static struct clk usbhs_ick = {
1881         .name           = "usbhs_ick",
1882         .parent         = &core_l3_ck,
1883         .flags          = CLOCK_IN_OMAP243X,
1884         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1885         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
1886         .recalc         = &omap2_followparent_recalc,
1887 };
1888
1889 static struct clk mmchs1_ick = {
1890         .name           = "mmchs1_ick",
1891         .parent         = &l4_ck,
1892         .flags          = CLOCK_IN_OMAP243X,
1893         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1894         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1895         .recalc         = &omap2_followparent_recalc,
1896 };
1897
1898 static struct clk mmchs1_fck = {
1899         .name           = "mmchs1_fck",
1900         .parent         = &func_96m_ck,
1901         .flags          = CLOCK_IN_OMAP243X,
1902         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1903         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1904         .recalc         = &omap2_followparent_recalc,
1905 };
1906
1907 static struct clk mmchs2_ick = {
1908         .name           = "mmchs2_ick",
1909         .parent         = &l4_ck,
1910         .flags          = CLOCK_IN_OMAP243X,
1911         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1912         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1913         .recalc         = &omap2_followparent_recalc,
1914 };
1915
1916 static struct clk mmchs2_fck = {
1917         .name           = "mmchs2_fck",
1918         .parent         = &func_96m_ck,
1919         .flags          = CLOCK_IN_OMAP243X,
1920         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1921         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1922         .recalc         = &omap2_followparent_recalc,
1923 };
1924
1925 static struct clk gpio5_ick = {
1926         .name           = "gpio5_ick",
1927         .parent         = &l4_ck,
1928         .flags          = CLOCK_IN_OMAP243X,
1929         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1930         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1931         .recalc         = &omap2_followparent_recalc,
1932 };
1933
1934 static struct clk gpio5_fck = {
1935         .name           = "gpio5_fck",
1936         .parent         = &func_32k_ck,
1937         .flags          = CLOCK_IN_OMAP243X,
1938         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1939         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
1940         .recalc         = &omap2_followparent_recalc,
1941 };
1942
1943 static struct clk mdm_intc_ick = {
1944         .name           = "mdm_intc_ick",
1945         .parent         = &l4_ck,
1946         .flags          = CLOCK_IN_OMAP243X,
1947         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1948         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
1949         .recalc         = &omap2_followparent_recalc,
1950 };
1951
1952 static struct clk mmchsdb1_fck = {
1953         .name           = "mmchsdb1_fck",
1954         .parent         = &func_32k_ck,
1955         .flags          = CLOCK_IN_OMAP243X,
1956         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1957         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
1958         .recalc         = &omap2_followparent_recalc,
1959 };
1960
1961 static struct clk mmchsdb2_fck = {
1962         .name           = "mmchsdb2_fck",
1963         .parent         = &func_32k_ck,
1964         .flags          = CLOCK_IN_OMAP243X,
1965         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1966         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
1967         .recalc         = &omap2_followparent_recalc,
1968 };
1969
1970 /*
1971  * This clock is a composite clock which does entire set changes then
1972  * forces a rebalance. It keys on the MPU speed, but it really could
1973  * be any key speed part of a set in the rate table.
1974  *
1975  * to really change a set, you need memory table sets which get changed
1976  * in sram, pre-notifiers & post notifiers, changing the top set, without
1977  * having low level display recalc's won't work... this is why dpm notifiers
1978  * work, isr's off, walk a list of clocks already _off_ and not messing with
1979  * the bus.
1980  *
1981  * This clock should have no parent. It embodies the entire upper level
1982  * active set. A parent will mess up some of the init also.
1983  */
1984 static struct clk virt_prcm_set = {
1985         .name           = "virt_prcm_set",
1986         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1987                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1988         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1989         .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
1990         .set_rate       = &omap2_select_table_rate,
1991         .round_rate     = &omap2_round_to_table_rate,
1992 };
1993
1994 static struct clk *onchip_clks[] = {
1995         /* external root sources */
1996         &func_32k_ck,
1997         &osc_ck,
1998         &sys_ck,
1999         &alt_ck,
2000         /* internal analog sources */
2001         &dpll_ck,
2002         &apll96_ck,
2003         &apll54_ck,
2004         /* internal prcm root sources */
2005         &func_54m_ck,
2006         &core_ck,
2007         &func_96m_ck,
2008         &func_48m_ck,
2009         &func_12m_ck,
2010         &wdt1_osc_ck,
2011         &sys_clkout,
2012         &sys_clkout2,
2013         &emul_ck,
2014         /* mpu domain clocks */
2015         &mpu_ck,
2016         /* dsp domain clocks */
2017         &iva2_1_fck,            /* 2430 */
2018         &iva2_1_ick,
2019         &dsp_ick,               /* 2420 */
2020         &dsp_fck,
2021         &iva1_ifck,
2022         &iva1_mpu_int_ifck,
2023         /* GFX domain clocks */
2024         &gfx_3d_fck,
2025         &gfx_2d_fck,
2026         &gfx_ick,
2027         /* Modem domain clocks */
2028         &mdm_ick,
2029         &mdm_osc_ck,
2030         /* DSS domain clocks */
2031         &dss_ick,
2032         &dss1_fck,
2033         &dss2_fck,
2034         &dss_54m_fck,
2035         /* L3 domain clocks */
2036         &core_l3_ck,
2037         &ssi_ssr_sst_fck,
2038         &usb_l4_ick,
2039         /* L4 domain clocks */
2040         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2041         &ssi_l4_ick,
2042         /* virtual meta-group clock */
2043         &virt_prcm_set,
2044         /* general l4 interface ck, multi-parent functional clk */
2045         &gpt1_ick,
2046         &gpt1_fck,
2047         &gpt2_ick,
2048         &gpt2_fck,
2049         &gpt3_ick,
2050         &gpt3_fck,
2051         &gpt4_ick,
2052         &gpt4_fck,
2053         &gpt5_ick,
2054         &gpt5_fck,
2055         &gpt6_ick,
2056         &gpt6_fck,
2057         &gpt7_ick,
2058         &gpt7_fck,
2059         &gpt8_ick,
2060         &gpt8_fck,
2061         &gpt9_ick,
2062         &gpt9_fck,
2063         &gpt10_ick,
2064         &gpt10_fck,
2065         &gpt11_ick,
2066         &gpt11_fck,
2067         &gpt12_ick,
2068         &gpt12_fck,
2069         &mcbsp1_ick,
2070         &mcbsp1_fck,
2071         &mcbsp2_ick,
2072         &mcbsp2_fck,
2073         &mcbsp3_ick,
2074         &mcbsp3_fck,
2075         &mcbsp4_ick,
2076         &mcbsp4_fck,
2077         &mcbsp5_ick,
2078         &mcbsp5_fck,
2079         &mcspi1_ick,
2080         &mcspi1_fck,
2081         &mcspi2_ick,
2082         &mcspi2_fck,
2083         &mcspi3_ick,
2084         &mcspi3_fck,
2085         &uart1_ick,
2086         &uart1_fck,
2087         &uart2_ick,
2088         &uart2_fck,
2089         &uart3_ick,
2090         &uart3_fck,
2091         &gpios_ick,
2092         &gpios_fck,
2093         &mpu_wdt_ick,
2094         &mpu_wdt_fck,
2095         &sync_32k_ick,
2096         &wdt1_ick,
2097         &omapctrl_ick,
2098         &icr_ick,
2099         &cam_fck,
2100         &cam_ick,
2101         &mailboxes_ick,
2102         &wdt4_ick,
2103         &wdt4_fck,
2104         &wdt3_ick,
2105         &wdt3_fck,
2106         &mspro_ick,
2107         &mspro_fck,
2108         &mmc_ick,
2109         &mmc_fck,
2110         &fac_ick,
2111         &fac_fck,
2112         &eac_ick,
2113         &eac_fck,
2114         &hdq_ick,
2115         &hdq_fck,
2116         &i2c1_ick,
2117         &i2c1_fck,
2118         &i2chs1_fck,
2119         &i2c2_ick,
2120         &i2c2_fck,
2121         &i2chs2_fck,
2122         &vlynq_ick,
2123         &vlynq_fck,
2124         &sdrc_ick,
2125         &des_ick,
2126         &sha_ick,
2127         &rng_ick,
2128         &aes_ick,
2129         &pka_ick,
2130         &usb_fck,
2131         &usbhs_ick,
2132         &mmchs1_ick,
2133         &mmchs1_fck,
2134         &mmchs2_ick,
2135         &mmchs2_fck,
2136         &gpio5_ick,
2137         &gpio5_fck,
2138         &mdm_intc_ick,
2139         &mmchsdb1_fck,
2140         &mmchsdb2_fck,
2141 };
2142
2143 #endif