2 * linux/arch/arm/mach-omap24xx/clock.h
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Copyright (C) 2004 Nokia corporation
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
20 static void omap2_sys_clk_recalc(struct clk * clk);
21 static void omap2_clksel_recalc(struct clk * clk);
22 static void omap2_followparent_recalc(struct clk * clk);
23 static void omap2_propagate_rate(struct clk * clk);
24 static void omap2_mpu_recalc(struct clk * clk);
25 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
26 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
27 static void omap2_clk_disable(struct clk *clk);
28 static void omap2_sys_clk_recalc(struct clk * clk);
29 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
30 static u32 omap2_clksel_get_divisor(struct clk *clk);
33 #define RATE_IN_242X (1 << 0)
34 #define RATE_IN_243X (1 << 1)
38 #define M_LOCK_CTRL (1 << 2)
42 struct memory_timings {
43 u32 m_type; /* ddr = 1, sdr = 0 */
44 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
45 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
46 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
47 u32 base_cs; /* base chip select to use for calculations */
50 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
51 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
52 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
55 unsigned long xtal_speed; /* crystal rate */
56 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
57 unsigned long mpu_speed; /* speed of MPU */
58 unsigned long cm_clksel_mpu; /* mpu divider */
59 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
60 unsigned long cm_clksel_gfx; /* gfx dividers */
61 unsigned long cm_clksel1_core; /* major subsystem dividers */
62 unsigned long cm_clksel1_pll; /* m,n */
63 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
64 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
65 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
69 /* Mask for clksel which support parent settign in set_rate */
70 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
71 CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
73 /* Mask for clksel regs which support rate operations */
74 #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
75 CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
76 CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
80 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
81 * These configurations are characterized by voltage and speed for clocks.
82 * The device is only validated for certain combinations. One way to express
83 * these combinations is via the 'ratio's' which the clocks operate with
84 * respect to each other. These ratio sets are for a given voltage/DPLL
85 * setting. All configurations can be described by a DPLL setting and a ratio
86 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
88 * 2430 differs from 2420 in that there are no more phase synchronizers used.
89 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
90 * 2430 (iva2.1, NOdsp, mdm)
93 /* Core fields for cm_clksel, not ratio governed */
94 #define RX_CLKSEL_DSS1 (0x10 << 8)
95 #define RX_CLKSEL_DSS2 (0x0 << 13)
96 #define RX_CLKSEL_SSI (0x5 << 20)
98 /*-------------------------------------------------------------------------
100 *-------------------------------------------------------------------------*/
102 /* 2430 Ratio's, 2430-Ratio Config 1 */
103 #define R1_CLKSEL_L3 (4 << 0)
104 #define R1_CLKSEL_L4 (2 << 5)
105 #define R1_CLKSEL_USB (4 << 25)
106 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
107 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
108 R1_CLKSEL_L4 | R1_CLKSEL_L3
109 #define R1_CLKSEL_MPU (2 << 0)
110 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
111 #define R1_CLKSEL_DSP (2 << 0)
112 #define R1_CLKSEL_DSP_IF (2 << 5)
113 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
114 #define R1_CLKSEL_GFX (2 << 0)
115 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
116 #define R1_CLKSEL_MDM (4 << 0)
117 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
119 /* 2430-Ratio Config 2 */
120 #define R2_CLKSEL_L3 (6 << 0)
121 #define R2_CLKSEL_L4 (2 << 5)
122 #define R2_CLKSEL_USB (2 << 25)
123 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
124 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
125 R2_CLKSEL_L4 | R2_CLKSEL_L3
126 #define R2_CLKSEL_MPU (2 << 0)
127 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
128 #define R2_CLKSEL_DSP (2 << 0)
129 #define R2_CLKSEL_DSP_IF (3 << 5)
130 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
131 #define R2_CLKSEL_GFX (2 << 0)
132 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
133 #define R2_CLKSEL_MDM (6 << 0)
134 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
136 /* 2430-Ratio Bootm (BYPASS) */
137 #define RB_CLKSEL_L3 (1 << 0)
138 #define RB_CLKSEL_L4 (1 << 5)
139 #define RB_CLKSEL_USB (1 << 25)
140 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
141 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
142 RB_CLKSEL_L4 | RB_CLKSEL_L3
143 #define RB_CLKSEL_MPU (1 << 0)
144 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
145 #define RB_CLKSEL_DSP (1 << 0)
146 #define RB_CLKSEL_DSP_IF (1 << 5)
147 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
148 #define RB_CLKSEL_GFX (1 << 0)
149 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
150 #define RB_CLKSEL_MDM (1 << 0)
151 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
153 /* 2420 Ratio Equivalents */
154 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
155 #define RXX_CLKSEL_SSI (0x8 << 20)
157 /* 2420-PRCM III 532MHz core */
158 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
159 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
160 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
161 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
162 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
163 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
165 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
166 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
167 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
168 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
169 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
170 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
171 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
172 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
173 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
175 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
176 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
178 /* 2420-PRCM II 600MHz core */
179 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
180 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
181 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
182 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
183 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
184 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
185 RII_CLKSEL_L4 | RII_CLKSEL_L3
186 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
187 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
188 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
189 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
190 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
191 #define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */
192 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
193 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
194 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
196 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
197 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
199 /* 2420-PRCM VII (boot) */
200 #define RVII_CLKSEL_L3 (1 << 0)
201 #define RVII_CLKSEL_L4 (1 << 5)
202 #define RVII_CLKSEL_DSS1 (1 << 8)
203 #define RVII_CLKSEL_DSS2 (0 << 13)
204 #define RVII_CLKSEL_VLYNQ (1 << 15)
205 #define RVII_CLKSEL_SSI (1 << 20)
206 #define RVII_CLKSEL_USB (1 << 25)
208 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
209 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
210 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
212 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
213 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
215 #define RVII_CLKSEL_DSP (1 << 0)
216 #define RVII_CLKSEL_DSP_IF (1 << 5)
217 #define RVII_SYNC_DSP (0 << 7)
218 #define RVII_CLKSEL_IVA (1 << 8)
219 #define RVII_SYNC_IVA (0 << 13)
220 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
221 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
223 #define RVII_CLKSEL_GFX (1 << 0)
224 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
226 /*-------------------------------------------------------------------------
227 * 2430 Target modes: Along with each configuration the CPU has several
228 * modes which goes along with them. Modes mainly are the addition of
229 * describe DPLL combinations to go along with a ratio.
230 *-------------------------------------------------------------------------*/
232 /* Hardware governed */
233 #define MX_48M_SRC (0 << 3)
234 #define MX_54M_SRC (0 << 5)
235 #define MX_APLLS_CLIKIN_12 (3 << 23)
236 #define MX_APLLS_CLIKIN_13 (2 << 23)
237 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
240 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
241 * #2 (ratio1) baseport-target
242 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
244 #define M5A_DPLL_MULT_12 (133 << 12)
245 #define M5A_DPLL_DIV_12 (5 << 8)
246 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
247 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
249 #define M5A_DPLL_MULT_13 (266 << 12)
250 #define M5A_DPLL_DIV_13 (12 << 8)
251 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
252 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
254 #define M5A_DPLL_MULT_19 (180 << 12)
255 #define M5A_DPLL_DIV_19 (12 << 8)
256 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
257 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
259 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
260 #define M5B_DPLL_MULT_12 (50 << 12)
261 #define M5B_DPLL_DIV_12 (2 << 8)
262 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
263 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
265 #define M5B_DPLL_MULT_13 (200 << 12)
266 #define M5B_DPLL_DIV_13 (12 << 8)
268 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
269 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
271 #define M5B_DPLL_MULT_19 (125 << 12)
272 #define M5B_DPLL_DIV_19 (31 << 8)
273 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
274 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
278 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
280 #define M3_DPLL_MULT_12 (55 << 12)
281 #define M3_DPLL_DIV_12 (1 << 8)
282 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
283 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
285 #define M3_DPLL_MULT_13 (330 << 12)
286 #define M3_DPLL_DIV_13 (12 << 8)
287 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
288 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
290 #define M3_DPLL_MULT_19 (275 << 12)
291 #define M3_DPLL_DIV_19 (15 << 8)
292 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
293 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
296 #define MB_DPLL_MULT (1 << 12)
297 #define MB_DPLL_DIV (0 << 8)
298 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
299 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
301 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
302 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
304 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
305 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
308 * 2430 - chassis (sedna)
309 * 165 (ratio1) same as above #2
311 * 133 (ratio2) same as above #4
312 * 110 (ratio2) same as above #3
318 * 2420 Equivalent - mode registers
319 * PRCM II , target DPLL = 2*300MHz = 600MHz
321 #define MII_DPLL_MULT_12 (50 << 12)
322 #define MII_DPLL_DIV_12 (1 << 8)
323 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
324 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
326 #define MII_DPLL_MULT_13 (300 << 12)
327 #define MII_DPLL_DIV_13 (12 << 8)
328 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
329 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
332 /* PRCM III target DPLL = 2*266 = 532MHz*/
333 #define MIII_DPLL_MULT_12 (133 << 12)
334 #define MIII_DPLL_DIV_12 (5 << 8)
335 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
336 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
338 #define MIII_DPLL_MULT_13 (266 << 12)
339 #define MIII_DPLL_DIV_13 (12 << 8)
340 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
341 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
344 /* PRCM VII (boot bypass) */
345 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
346 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
348 /* High and low operation value */
349 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
350 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
353 * These represent optimal values for common parts, it won't work for all.
354 * As long as you scale down, most parameters are still work, they just
355 * become sub-optimal. The RFR value goes in the oppisite direction. If you
356 * don't adjust it down as your clock period increases the refresh interval
357 * will not be met. Setting all parameters for complete worst case may work,
358 * but may cut memory performance by 2x. Due to errata the DLLs need to be
359 * unlocked and their value needs run time calibration. A dynamic call is
360 * need for that as no single right value exists acorss production samples.
362 * Only the FULL speed values are given. Current code is such that rate
363 * changes must be made at DPLLoutx2. The actual value adjustment for low
364 * frequency operation will be handled by omap_set_performance()
366 * By having the boot loader boot up in the fastest L4 speed available likely
367 * will result in something which you can switch between.
369 #define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
370 #define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
371 #define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
372 #define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
374 /* MPU speed defines */
375 #define S12M 12000000
376 #define S13M 13000000
377 #define S19M 19200000
378 #define S26M 26000000
379 #define S100M 100000000
380 #define S133M 133000000
381 #define S150M 150000000
382 #define S165M 165000000
383 #define S200M 200000000
384 #define S266M 266000000
385 #define S300M 300000000
386 #define S330M 330000000
387 #define S400M 400000000
388 #define S532M 532000000
389 #define S600M 600000000
390 #define S660M 660000000
392 /*-------------------------------------------------------------------------
393 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
394 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
395 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
396 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
398 * Filling in table based on H4 boards and 2430-SDPs variants available.
399 * There are quite a few more rates combinations which could be defined.
401 * When multiple values are defiend the start up will try and choose the
402 * fastest one. If a 'fast' value is defined, then automatically, the /2
403 * one should be included as it can be used. Generally having more that
404 * one fast set does not make sense, as static timings need to be changed
405 * to change the set. The exception is the bypass setting which is
406 * availble for low power bypass.
408 * Note: This table needs to be sorted, fastest to slowest.
409 *-------------------------------------------------------------------------*/
410 static struct prcm_config rate_table[] = {
412 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
413 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
414 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
415 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
418 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
419 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
420 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
421 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
424 /* PRCM III - FAST */
425 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
426 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
427 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
428 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
431 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
432 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
433 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
434 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
438 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
439 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
440 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
441 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
444 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
445 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
446 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
447 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
450 /* PRCM III - SLOW */
451 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
452 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
453 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
454 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
457 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
458 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
459 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
460 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
463 /* PRCM-VII (boot-bypass) */
464 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
465 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
466 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
467 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
470 /* PRCM-VII (boot-bypass) */
471 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
472 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
473 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
474 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
477 /* PRCM #3 - ratio2 (ES2) - FAST */
478 {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
479 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
480 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
481 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
482 V24XX_SDRC_RFR_CTRL_110MHz,
485 /* PRCM #5a - ratio1 - FAST */
486 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
487 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
488 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
489 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
490 V24XX_SDRC_RFR_CTRL_133MHz,
493 /* PRCM #5b - ratio1 - FAST */
494 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
495 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
496 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
497 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
498 V24XX_SDRC_RFR_CTRL_100MHz,
501 /* PRCM #3 - ratio2 (ES2) - SLOW */
502 {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
503 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
504 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
505 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
506 V24XX_SDRC_RFR_CTRL_110MHz,
509 /* PRCM #5a - ratio1 - SLOW */
510 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
511 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
512 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
513 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
514 V24XX_SDRC_RFR_CTRL_133MHz,
517 /* PRCM #5b - ratio1 - SLOW*/
518 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
519 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
520 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
521 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
522 V24XX_SDRC_RFR_CTRL_100MHz,
525 /* PRCM-boot/bypass */
526 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
527 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
528 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
529 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
530 V24XX_SDRC_RFR_CTRL_BYPASS,
533 /* PRCM-boot/bypass */
534 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
535 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
536 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
537 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
538 V24XX_SDRC_RFR_CTRL_BYPASS,
541 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
544 /*-------------------------------------------------------------------------
547 * NOTE:In many cases here we are assigning a 'default' parent. In many
548 * cases the parent is selectable. The get/set parent calls will also
551 * Many some clocks say always_enabled, but they can be auto idled for
552 * power savings. They will always be available upon clock request.
554 * Several sources are given initial rates which may be wrong, this will
555 * be fixed up in the init func.
557 * Things are broadly separated below by clock domains. It is
558 * noteworthy that most periferals have dependencies on multiple clock
559 * domains. Many get their interface clocks from the L4 domain, but get
560 * functional clocks from fixed sources or other core domain derived
562 *-------------------------------------------------------------------------*/
564 /* Base external input clocks */
565 static struct clk func_32k_ck = {
566 .name = "func_32k_ck",
568 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
569 RATE_FIXED | ALWAYS_ENABLED,
572 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
573 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
575 .rate = 26000000, /* fixed up in clock init */
576 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
577 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
580 /* With out modem likely 12MHz, with modem likely 13MHz */
581 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
582 .name = "sys_ck", /* ~ ref_clk also */
585 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
586 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
587 .rate_offset = 6, /* sysclkdiv 1 or 2, already handled or no boot */
588 .recalc = &omap2_sys_clk_recalc,
591 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
594 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
595 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
596 .recalc = &omap2_propagate_rate,
600 * Analog domain root source clocks
603 /* dpll_ck, is broken out in to special cases through clksel */
604 static struct clk dpll_ck = {
606 .parent = &sys_ck, /* Can be func_32k also */
607 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
608 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
609 .recalc = &omap2_clksel_recalc,
612 static struct clk apll96_ck = {
616 .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
617 RATE_FIXED | RATE_PROPAGATES,
618 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
620 .recalc = &omap2_propagate_rate,
623 static struct clk apll54_ck = {
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628 RATE_FIXED | RATE_PROPAGATES,
629 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
631 .recalc = &omap2_propagate_rate,
635 * PRCM digital base sources
637 static struct clk func_54m_ck = {
638 .name = "func_54m_ck",
639 .parent = &apll54_ck, /* can also be alt_clk */
641 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
642 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
644 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
646 .recalc = &omap2_propagate_rate,
649 static struct clk core_ck = {
651 .parent = &dpll_ck, /* can also be 32k */
652 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
653 ALWAYS_ENABLED | RATE_PROPAGATES,
654 .recalc = &omap2_propagate_rate,
657 static struct clk sleep_ck = { /* sys_clk or 32k */
659 .parent = &func_32k_ck,
661 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
662 .recalc = &omap2_propagate_rate,
665 static struct clk func_96m_ck = {
666 .name = "func_96m_ck",
667 .parent = &apll96_ck,
669 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
670 RATE_FIXED | RATE_PROPAGATES,
671 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
673 .recalc = &omap2_propagate_rate,
676 static struct clk func_48m_ck = {
677 .name = "func_48m_ck",
678 .parent = &apll96_ck, /* 96M or Alt */
680 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
681 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
683 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
685 .recalc = &omap2_propagate_rate,
688 static struct clk func_12m_ck = {
689 .name = "func_12m_ck",
690 .parent = &func_48m_ck,
692 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
693 RATE_FIXED | RATE_PROPAGATES,
694 .recalc = &omap2_propagate_rate,
695 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
699 /* Secure timer, only available in secure mode */
700 static struct clk wdt1_osc_ck = {
701 .name = "ck_wdt1_osc",
703 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
704 .recalc = &omap2_followparent_recalc,
707 static struct clk sys_clkout = {
708 .name = "sys_clkout",
709 .parent = &func_54m_ck,
711 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
712 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
714 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
717 .recalc = &omap2_clksel_recalc,
720 /* In 2430, new in 2420 ES2 */
721 static struct clk sys_clkout2 = {
722 .name = "sys_clkout2",
723 .parent = &func_54m_ck,
725 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
726 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
728 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
731 .recalc = &omap2_clksel_recalc,
738 * INT_M_FCLK, INT_M_I_CLK
740 * - Individual clocks are hardware managed.
741 * - Base divider comes from: CM_CLKSEL_MPU
744 static struct clk mpu_ck = { /* Control cpu */
747 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
748 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
749 CONFIG_PARTICIPANT | RATE_PROPAGATES,
750 .rate_offset = 0, /* bits 0-4 */
751 .recalc = &omap2_clksel_recalc,
755 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
757 * 2430: IVA2.1_FCLK, IVA2.1_ICLK
758 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
760 static struct clk iva2_1_fck = {
761 .name = "iva2_1_fck",
763 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
764 DELAYED_APP | RATE_PROPAGATES |
767 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
769 .recalc = &omap2_clksel_recalc,
772 static struct clk iva2_1_ick = {
773 .name = "iva2_1_ick",
774 .parent = &iva2_1_fck,
775 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
776 DELAYED_APP | CONFIG_PARTICIPANT,
778 .recalc = &omap2_clksel_recalc,
782 * Won't be too specific here. The core clock comes into this block
783 * it is divided then tee'ed. One branch goes directly to xyz enable
784 * controls. The other branch gets further divided by 2 then possibly
785 * routed into a synchronizer and out of clocks abc.
787 static struct clk dsp_fck = {
790 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
791 DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
793 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
795 .recalc = &omap2_clksel_recalc,
798 static struct clk dsp_ick = {
799 .name = "dsp_ick", /* apparently ipi and isp */
801 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
802 DELAYED_APP | CONFIG_PARTICIPANT,
804 .enable_reg = (void __iomem *)&CM_ICLKEN_DSP,
805 .enable_bit = 1, /* for ipi */
806 .recalc = &omap2_clksel_recalc,
809 static struct clk iva1_ifck = {
812 .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
813 CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
815 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
817 .recalc = &omap2_clksel_recalc,
820 /* IVA1 mpu/int/i/f clocks are /2 of parent */
821 static struct clk iva1_mpu_int_ifck = {
822 .name = "iva1_mpu_int_ifck",
823 .parent = &iva1_ifck,
824 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
825 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
827 .recalc = &omap2_clksel_recalc,
832 * L3 clocks are used for both interface and functional clocks to
833 * multiple entities. Some of these clocks are completely managed
834 * by hardware, and some others allow software control. Hardware
835 * managed ones general are based on directly CLK_REQ signals and
836 * various auto idle settings. The functional spec sets many of these
837 * as 'tie-high' for their enables.
840 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
845 * GPMC memories and SDRC have timing and clock sensitive registers which
846 * may very well need notification when the clock changes. Currently for low
847 * operating points, these are taken care of in sleep.S.
849 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
850 .name = "core_l3_ck",
852 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
853 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
854 DELAYED_APP | CONFIG_PARTICIPANT |
857 .recalc = &omap2_clksel_recalc,
860 static struct clk usb_l4_ick = { /* FS-USB interface clock */
861 .name = "usb_l4_ick",
862 .parent = &core_l3_ck,
863 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
864 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
866 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
869 .recalc = &omap2_clksel_recalc,
873 * SSI is in L3 management domain, its direct parent is core not l3,
874 * many core power domain entities are grouped into the L3 clock
876 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
878 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
880 static struct clk ssi_ssr_sst_fck = {
883 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
884 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
885 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */
888 .recalc = &omap2_clksel_recalc,
895 * GFX_CG1(2d), GFX_CG2(3d)
897 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
898 * The 2d and 3d clocks run at a hardware determined
899 * divided value of fclk.
902 static struct clk gfx_3d_fck = {
903 .name = "gfx_3d_fck",
904 .parent = &core_l3_ck,
905 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
906 RATE_CKCTL | CM_GFX_SEL1,
907 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
910 .recalc = &omap2_clksel_recalc,
913 static struct clk gfx_2d_fck = {
914 .name = "gfx_2d_fck",
915 .parent = &core_l3_ck,
916 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
917 RATE_CKCTL | CM_GFX_SEL1,
918 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
921 .recalc = &omap2_clksel_recalc,
924 static struct clk gfx_ick = {
925 .name = "gfx_ick", /* From l3 */
926 .parent = &core_l3_ck,
927 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
929 .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */
931 .recalc = &omap2_followparent_recalc,
935 * Modem clock domain (2430)
940 static struct clk mdm_ick = { /* used both as a ick and fck */
943 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
944 DELAYED_APP | CONFIG_PARTICIPANT,
946 .enable_reg = (void __iomem *)&CM_ICLKEN_MDM,
948 .recalc = &omap2_clksel_recalc,
951 static struct clk mdm_osc_ck = {
952 .name = "mdm_osc_ck",
955 .flags = CLOCK_IN_OMAP243X | RATE_FIXED,
956 .enable_reg = (void __iomem *)&CM_FCLKEN_MDM,
958 .recalc = &omap2_followparent_recalc,
962 * L4 clock management domain
964 * This domain contains lots of interface clocks from the L4 interface, some
965 * functional clocks. Fixed APLL functional source clocks are managed in
968 static struct clk l4_ck = { /* used both as an ick and fck */
970 .parent = &core_l3_ck,
971 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
972 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
973 DELAYED_APP | RATE_PROPAGATES,
975 .recalc = &omap2_clksel_recalc,
978 static struct clk ssi_l4_ick = {
979 .name = "ssi_l4_ick",
981 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
982 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */
984 .recalc = &omap2_followparent_recalc,
990 * DSS_L4_ICLK, DSS_L3_ICLK,
991 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
993 * DSS is both initiator and target.
995 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
997 .parent = &l4_ck, /* really both l3 and l4 */
998 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
999 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1001 .recalc = &omap2_followparent_recalc,
1004 static struct clk dss1_fck = {
1006 .parent = &core_ck, /* Core or sys */
1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1008 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1009 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1013 .recalc = &omap2_clksel_recalc,
1016 static struct clk dss2_fck = { /* Alt clk used in power management */
1018 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1019 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1020 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED,
1021 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1024 .recalc = &omap2_followparent_recalc,
1027 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1028 .name = "dss_54m_fck", /* 54m tv clk */
1029 .parent = &func_54m_ck,
1031 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1032 RATE_FIXED | RATE_PROPAGATES,
1033 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1035 .recalc = &omap2_propagate_rate,
1039 * CORE power domain ICLK & FCLK defines.
1040 * Many of the these can have more than one possible parent. Entries
1041 * here will likely have an L4 interface parent, and may have multiple
1042 * functional clock parents.
1044 static struct clk gpt1_ick = {
1047 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1048 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */
1050 .recalc = &omap2_followparent_recalc,
1053 static struct clk gpt1_fck = {
1055 .parent = &func_32k_ck,
1056 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1058 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */
1061 .recalc = &omap2_followparent_recalc,
1064 static struct clk gpt2_ick = {
1067 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1068 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
1070 .recalc = &omap2_followparent_recalc,
1073 static struct clk gpt2_fck = {
1075 .parent = &func_32k_ck,
1076 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1078 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1081 .recalc = &omap2_followparent_recalc,
1084 static struct clk gpt3_ick = {
1087 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1088 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */
1090 .recalc = &omap2_followparent_recalc,
1093 static struct clk gpt3_fck = {
1095 .parent = &func_32k_ck,
1096 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1098 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1101 .recalc = &omap2_followparent_recalc,
1104 static struct clk gpt4_ick = {
1107 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1108 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */
1110 .recalc = &omap2_followparent_recalc,
1113 static struct clk gpt4_fck = {
1115 .parent = &func_32k_ck,
1116 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1118 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1121 .recalc = &omap2_followparent_recalc,
1124 static struct clk gpt5_ick = {
1127 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1128 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */
1130 .recalc = &omap2_followparent_recalc,
1133 static struct clk gpt5_fck = {
1135 .parent = &func_32k_ck,
1136 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1138 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1141 .recalc = &omap2_followparent_recalc,
1144 static struct clk gpt6_ick = {
1147 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1149 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */
1150 .recalc = &omap2_followparent_recalc,
1153 static struct clk gpt6_fck = {
1155 .parent = &func_32k_ck,
1156 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1158 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1161 .recalc = &omap2_followparent_recalc,
1164 static struct clk gpt7_ick = {
1167 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1168 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */
1170 .recalc = &omap2_followparent_recalc,
1173 static struct clk gpt7_fck = {
1175 .parent = &func_32k_ck,
1176 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1178 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1181 .recalc = &omap2_followparent_recalc,
1184 static struct clk gpt8_ick = {
1187 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1188 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */
1190 .recalc = &omap2_followparent_recalc,
1193 static struct clk gpt8_fck = {
1195 .parent = &func_32k_ck,
1196 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1198 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1201 .recalc = &omap2_followparent_recalc,
1204 static struct clk gpt9_ick = {
1207 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1208 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1210 .recalc = &omap2_followparent_recalc,
1213 static struct clk gpt9_fck = {
1215 .parent = &func_32k_ck,
1216 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1218 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1221 .recalc = &omap2_followparent_recalc,
1224 static struct clk gpt10_ick = {
1225 .name = "gpt10_ick",
1227 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1228 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1230 .recalc = &omap2_followparent_recalc,
1233 static struct clk gpt10_fck = {
1234 .name = "gpt10_fck",
1235 .parent = &func_32k_ck,
1236 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1238 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1241 .recalc = &omap2_followparent_recalc,
1244 static struct clk gpt11_ick = {
1245 .name = "gpt11_ick",
1247 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1248 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1250 .recalc = &omap2_followparent_recalc,
1253 static struct clk gpt11_fck = {
1254 .name = "gpt11_fck",
1255 .parent = &func_32k_ck,
1256 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1258 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1261 .recalc = &omap2_followparent_recalc,
1264 static struct clk gpt12_ick = {
1265 .name = "gpt12_ick",
1267 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1268 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */
1270 .recalc = &omap2_followparent_recalc,
1273 static struct clk gpt12_fck = {
1274 .name = "gpt12_fck",
1275 .parent = &func_32k_ck,
1276 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1278 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1281 .recalc = &omap2_followparent_recalc,
1284 static struct clk mcbsp1_ick = {
1285 .name = "mcbsp1_ick",
1287 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1289 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */
1290 .recalc = &omap2_followparent_recalc,
1293 static struct clk mcbsp1_fck = {
1294 .name = "mcbsp1_fck",
1295 .parent = &func_96m_ck,
1296 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1298 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1299 .recalc = &omap2_followparent_recalc,
1302 static struct clk mcbsp2_ick = {
1303 .name = "mcbsp2_ick",
1305 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1307 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1308 .recalc = &omap2_followparent_recalc,
1311 static struct clk mcbsp2_fck = {
1312 .name = "mcbsp2_fck",
1313 .parent = &func_96m_ck,
1314 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1316 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1317 .recalc = &omap2_followparent_recalc,
1320 static struct clk mcbsp3_ick = {
1321 .name = "mcbsp3_ick",
1323 .flags = CLOCK_IN_OMAP243X,
1324 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1326 .recalc = &omap2_followparent_recalc,
1329 static struct clk mcbsp3_fck = {
1330 .name = "mcbsp3_fck",
1331 .parent = &func_96m_ck,
1332 .flags = CLOCK_IN_OMAP243X,
1333 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1335 .recalc = &omap2_followparent_recalc,
1338 static struct clk mcbsp4_ick = {
1339 .name = "mcbsp4_ick",
1341 .flags = CLOCK_IN_OMAP243X,
1342 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1344 .recalc = &omap2_followparent_recalc,
1347 static struct clk mcbsp4_fck = {
1348 .name = "mcbsp4_fck",
1349 .parent = &func_96m_ck,
1350 .flags = CLOCK_IN_OMAP243X,
1351 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1353 .recalc = &omap2_followparent_recalc,
1356 static struct clk mcbsp5_ick = {
1357 .name = "mcbsp5_ick",
1359 .flags = CLOCK_IN_OMAP243X,
1360 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1362 .recalc = &omap2_followparent_recalc,
1365 static struct clk mcbsp5_fck = {
1366 .name = "mcbsp5_fck",
1367 .parent = &func_96m_ck,
1368 .flags = CLOCK_IN_OMAP243X,
1369 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1371 .recalc = &omap2_followparent_recalc,
1374 static struct clk mcspi1_ick = {
1375 .name = "mcspi1_ick",
1377 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1378 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1380 .recalc = &omap2_followparent_recalc,
1383 static struct clk mcspi1_fck = {
1384 .name = "mcspi1_fck",
1385 .parent = &func_48m_ck,
1386 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1387 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1389 .recalc = &omap2_followparent_recalc,
1392 static struct clk mcspi2_ick = {
1393 .name = "mcspi2_ick",
1395 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1396 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1398 .recalc = &omap2_followparent_recalc,
1401 static struct clk mcspi2_fck = {
1402 .name = "mcspi2_fck",
1403 .parent = &func_48m_ck,
1404 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1405 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1407 .recalc = &omap2_followparent_recalc,
1410 static struct clk mcspi3_ick = {
1411 .name = "mcspi3_ick",
1413 .flags = CLOCK_IN_OMAP243X,
1414 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1416 .recalc = &omap2_followparent_recalc,
1419 static struct clk mcspi3_fck = {
1420 .name = "mcspi3_fck",
1421 .parent = &func_48m_ck,
1422 .flags = CLOCK_IN_OMAP243X,
1423 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1425 .recalc = &omap2_followparent_recalc,
1428 static struct clk uart1_ick = {
1429 .name = "uart1_ick",
1431 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1432 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1434 .recalc = &omap2_followparent_recalc,
1437 static struct clk uart1_fck = {
1438 .name = "uart1_fck",
1439 .parent = &func_48m_ck,
1440 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1441 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1443 .recalc = &omap2_followparent_recalc,
1446 static struct clk uart2_ick = {
1447 .name = "uart2_ick",
1449 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1450 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1452 .recalc = &omap2_followparent_recalc,
1455 static struct clk uart2_fck = {
1456 .name = "uart2_fck",
1457 .parent = &func_48m_ck,
1458 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1459 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1461 .recalc = &omap2_followparent_recalc,
1464 static struct clk uart3_ick = {
1465 .name = "uart3_ick",
1467 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1468 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1470 .recalc = &omap2_followparent_recalc,
1473 static struct clk uart3_fck = {
1474 .name = "uart3_fck",
1475 .parent = &func_48m_ck,
1476 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1477 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1479 .recalc = &omap2_followparent_recalc,
1482 static struct clk gpios_ick = {
1483 .name = "gpios_ick",
1485 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1486 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1488 .recalc = &omap2_followparent_recalc,
1491 static struct clk gpios_fck = {
1492 .name = "gpios_fck",
1493 .parent = &func_32k_ck,
1494 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1495 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
1497 .recalc = &omap2_followparent_recalc,
1500 static struct clk mpu_wdt_ick = {
1501 .name = "mpu_wdt_ick",
1503 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1504 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1506 .recalc = &omap2_followparent_recalc,
1509 static struct clk mpu_wdt_fck = {
1510 .name = "mpu_wdt_fck",
1511 .parent = &func_32k_ck,
1512 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1513 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
1515 .recalc = &omap2_followparent_recalc,
1518 static struct clk sync_32k_ick = {
1519 .name = "sync_32k_ick",
1521 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1522 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1524 .recalc = &omap2_followparent_recalc,
1526 static struct clk wdt1_ick = {
1529 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1530 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1532 .recalc = &omap2_followparent_recalc,
1534 static struct clk omapctrl_ick = {
1535 .name = "omapctrl_ick",
1537 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1538 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1540 .recalc = &omap2_followparent_recalc,
1542 static struct clk icr_ick = {
1545 .flags = CLOCK_IN_OMAP243X,
1546 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1548 .recalc = &omap2_followparent_recalc,
1551 static struct clk cam_ick = {
1554 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1555 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1557 .recalc = &omap2_followparent_recalc,
1560 static struct clk cam_fck = {
1562 .parent = &func_96m_ck,
1563 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1564 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1566 .recalc = &omap2_followparent_recalc,
1569 static struct clk mailboxes_ick = {
1570 .name = "mailboxes_ick",
1572 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1575 .recalc = &omap2_followparent_recalc,
1578 static struct clk wdt4_ick = {
1581 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1582 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1584 .recalc = &omap2_followparent_recalc,
1587 static struct clk wdt4_fck = {
1589 .parent = &func_32k_ck,
1590 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1591 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1593 .recalc = &omap2_followparent_recalc,
1596 static struct clk wdt3_ick = {
1599 .flags = CLOCK_IN_OMAP242X,
1600 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1602 .recalc = &omap2_followparent_recalc,
1605 static struct clk wdt3_fck = {
1607 .parent = &func_32k_ck,
1608 .flags = CLOCK_IN_OMAP242X,
1609 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1611 .recalc = &omap2_followparent_recalc,
1614 static struct clk mspro_ick = {
1615 .name = "mspro_ick",
1617 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1618 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1620 .recalc = &omap2_followparent_recalc,
1623 static struct clk mspro_fck = {
1624 .name = "mspro_fck",
1625 .parent = &func_96m_ck,
1626 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1627 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1629 .recalc = &omap2_followparent_recalc,
1632 static struct clk mmc_ick = {
1635 .flags = CLOCK_IN_OMAP242X,
1636 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1638 .recalc = &omap2_followparent_recalc,
1641 static struct clk mmc_fck = {
1643 .parent = &func_96m_ck,
1644 .flags = CLOCK_IN_OMAP242X,
1645 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1647 .recalc = &omap2_followparent_recalc,
1650 static struct clk fac_ick = {
1653 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1654 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1656 .recalc = &omap2_followparent_recalc,
1659 static struct clk fac_fck = {
1661 .parent = &func_12m_ck,
1662 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1663 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1665 .recalc = &omap2_followparent_recalc,
1668 static struct clk eac_ick = {
1671 .flags = CLOCK_IN_OMAP242X,
1672 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1674 .recalc = &omap2_followparent_recalc,
1677 static struct clk eac_fck = {
1679 .parent = &func_96m_ck,
1680 .flags = CLOCK_IN_OMAP242X,
1681 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1683 .recalc = &omap2_followparent_recalc,
1686 static struct clk hdq_ick = {
1689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1690 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1692 .recalc = &omap2_followparent_recalc,
1695 static struct clk hdq_fck = {
1697 .parent = &func_12m_ck,
1698 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1699 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1701 .recalc = &omap2_followparent_recalc,
1704 static struct clk i2c2_ick = {
1707 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1708 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1710 .recalc = &omap2_followparent_recalc,
1713 static struct clk i2c2_fck = {
1715 .parent = &func_12m_ck,
1716 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1717 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1719 .recalc = &omap2_followparent_recalc,
1722 static struct clk i2chs2_fck = {
1723 .name = "i2chs2_fck",
1724 .parent = &func_96m_ck,
1725 .flags = CLOCK_IN_OMAP243X,
1726 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1728 .recalc = &omap2_followparent_recalc,
1731 static struct clk i2c1_ick = {
1734 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1735 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1737 .recalc = &omap2_followparent_recalc,
1740 static struct clk i2c1_fck = {
1742 .parent = &func_12m_ck,
1743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1744 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1746 .recalc = &omap2_followparent_recalc,
1749 static struct clk i2chs1_fck = {
1750 .name = "i2chs1_fck",
1751 .parent = &func_96m_ck,
1752 .flags = CLOCK_IN_OMAP243X,
1753 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1755 .recalc = &omap2_followparent_recalc,
1758 static struct clk vlynq_ick = {
1759 .name = "vlynq_ick",
1760 .parent = &core_l3_ck,
1761 .flags = CLOCK_IN_OMAP242X,
1762 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1764 .recalc = &omap2_followparent_recalc,
1767 static struct clk vlynq_fck = {
1768 .name = "vlynq_fck",
1769 .parent = &func_96m_ck,
1770 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1771 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1774 .recalc = &omap2_followparent_recalc,
1777 static struct clk sdrc_ick = {
1780 .flags = CLOCK_IN_OMAP243X,
1781 .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE,
1783 .recalc = &omap2_followparent_recalc,
1786 static struct clk des_ick = {
1789 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1790 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1792 .recalc = &omap2_followparent_recalc,
1795 static struct clk sha_ick = {
1798 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1799 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1801 .recalc = &omap2_followparent_recalc,
1804 static struct clk rng_ick = {
1807 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1808 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1810 .recalc = &omap2_followparent_recalc,
1813 static struct clk aes_ick = {
1816 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1817 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1819 .recalc = &omap2_followparent_recalc,
1822 static struct clk pka_ick = {
1825 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1826 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1828 .recalc = &omap2_followparent_recalc,
1831 static struct clk usb_fck = {
1833 .parent = &func_48m_ck,
1834 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1835 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1837 .recalc = &omap2_followparent_recalc,
1840 static struct clk usbhs_ick = {
1841 .name = "usbhs_ick",
1842 .parent = &core_l3_ck,
1843 .flags = CLOCK_IN_OMAP243X,
1844 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1846 .recalc = &omap2_followparent_recalc,
1849 static struct clk mmchs1_ick = {
1850 .name = "mmchs1_ick",
1852 .flags = CLOCK_IN_OMAP243X,
1853 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1855 .recalc = &omap2_followparent_recalc,
1858 static struct clk mmchs1_fck = {
1859 .name = "mmchs1_fck",
1860 .parent = &func_96m_ck,
1861 .flags = CLOCK_IN_OMAP243X,
1862 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1864 .recalc = &omap2_followparent_recalc,
1867 static struct clk mmchs2_ick = {
1868 .name = "mmchs2_ick",
1870 .flags = CLOCK_IN_OMAP243X,
1871 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1873 .recalc = &omap2_followparent_recalc,
1876 static struct clk mmchs2_fck = {
1877 .name = "mmchs2_fck",
1878 .parent = &func_96m_ck,
1879 .flags = CLOCK_IN_OMAP243X,
1880 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1882 .recalc = &omap2_followparent_recalc,
1885 static struct clk gpio5_ick = {
1886 .name = "gpio5_ick",
1888 .flags = CLOCK_IN_OMAP243X,
1889 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1891 .recalc = &omap2_followparent_recalc,
1894 static struct clk gpio5_fck = {
1895 .name = "gpio5_fck",
1896 .parent = &func_32k_ck,
1897 .flags = CLOCK_IN_OMAP243X,
1898 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1900 .recalc = &omap2_followparent_recalc,
1903 static struct clk mdm_intc_ick = {
1904 .name = "mdm_intc_ick",
1906 .flags = CLOCK_IN_OMAP243X,
1907 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1909 .recalc = &omap2_followparent_recalc,
1912 static struct clk mmchsdb1_fck = {
1913 .name = "mmchsdb1_fck",
1914 .parent = &func_32k_ck,
1915 .flags = CLOCK_IN_OMAP243X,
1916 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1918 .recalc = &omap2_followparent_recalc,
1921 static struct clk mmchsdb2_fck = {
1922 .name = "mmchsdb2_fck",
1923 .parent = &func_32k_ck,
1924 .flags = CLOCK_IN_OMAP243X,
1925 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1927 .recalc = &omap2_followparent_recalc,
1931 * This clock is a composite clock which does entire set changes then
1932 * forces a rebalance. It keys on the MPU speed, but it really could
1933 * be any key speed part of a set in the rate table.
1935 * to really change a set, you need memory table sets which get changed
1936 * in sram, pre-notifiers & post notifiers, changing the top set, without
1937 * having low level display recalc's won't work... this is why dpm notifiers
1938 * work, isr's off, walk a list of clocks already _off_ and not messing with
1941 * This clock should have no parent. It embodies the entire upper level
1942 * active set. A parent will mess up some of the init also.
1944 static struct clk virt_prcm_set = {
1945 .name = "virt_prcm_set",
1946 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1947 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1948 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1949 .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */
1950 .set_rate = &omap2_select_table_rate,
1951 .round_rate = &omap2_round_to_table_rate,
1954 static struct clk *onchip_clks[] = {
1955 /* external root sources */
1960 /* internal analog sources */
1964 /* internal prcm root sources */
1974 /* mpu domain clocks */
1976 /* dsp domain clocks */
1977 &iva2_1_fck, /* 2430 */
1979 &dsp_ick, /* 2420 */
1983 /* GFX domain clocks */
1987 /* Modem domain clocks */
1990 /* DSS domain clocks */
1995 /* L3 domain clocks */
1999 /* L4 domain clocks */
2000 &l4_ck, /* used as both core_l4 and wu_l4 */
2002 /* virtual meta-group clock */
2004 /* general l4 interface ck, multi-parent functional clk */