arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.h
   3  *
   4  *  Copyright (C) 2005 Texas Instruments Inc.
   5  *  Richard Woodruff <r-woodruff2@ti.com>
   6  *  Created for OMAP2.
   7  *
   8  *  Copyright (C) 2004 Nokia corporation
   9  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  11  *
  12  *  Copyright (C) 2007 Texas Instruments, Inc.
  13  *  Copyright (C) 2007 Nokia Corporation
  14  *  Paul Walmsley
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  22 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  23
  24 #include "prm.h"
  25 #include "cm.h"
  26 #include "prm_regbits_24xx.h"
  27 #include "cm_regbits_24xx.h"
  28 #include "sdrc.h"
  29
  30 static void omap2_clksel_recalc(struct clk * clk);
  31 static void omap2_table_mpu_recalc(struct clk *clk);
  32 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
  33 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
  34 static void omap2_clk_disable(struct clk *clk);
  35 static void omap2_sys_clk_recalc(struct clk * clk);
  36 static void omap2_init_clksel_parent(struct clk *clk);
  37 static u32 omap2_clksel_get_divisor(struct clk *clk);
  38 static u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
  39 static u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
  40 static void omap2_osc_clk_recalc(struct clk *clk);
  41 static void omap2_sys_clk_recalc(struct clk *clk);
  42 static void omap2_dpll_recalc(struct clk *clk);
  43 static void omap2_fixed_divisor_recalc(struct clk *clk);
  44 static int omap2_clk_fixed_enable(struct clk *clk);
  45 static void omap2_clk_fixed_disable(struct clk *clk);
  46 static long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
  47 static int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
  48 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
  49 static int omap2_enable_osc_ck(struct clk *clk);
  50 static void omap2_disable_osc_ck(struct clk *clk);
  51
  52 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
  53  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
  54  * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
  55  */
  56 struct prcm_config {
  57         unsigned long xtal_speed;       /* crystal rate */
  58         unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
  59         unsigned long mpu_speed;        /* speed of MPU */
  60         unsigned long cm_clksel_mpu;    /* mpu divider */
  61         unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
  62         unsigned long cm_clksel_gfx;    /* gfx dividers */
  63         unsigned long cm_clksel1_core;  /* major subsystem dividers */
  64         unsigned long cm_clksel1_pll;   /* m,n */
  65         unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
  66         unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
  67         unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
  68         unsigned char flags;
  69 };
  70
  71 /*
  72  * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
  73  * These configurations are characterized by voltage and speed for clocks.
  74  * The device is only validated for certain combinations. One way to express
  75  * these combinations is via the 'ratio's' which the clocks operate with
  76  * respect to each other. These ratio sets are for a given voltage/DPLL
  77  * setting. All configurations can be described by a DPLL setting and a ratio
  78  * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
  79  *
  80  * 2430 differs from 2420 in that there are no more phase synchronizers used.
  81  * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
  82  * 2430 (iva2.1, NOdsp, mdm)
  83  */
  84
  85 /* Core fields for cm_clksel, not ratio governed */
  86 #define RX_CLKSEL_DSS1                  (0x10 << 8)
  87 #define RX_CLKSEL_DSS2                  (0x0 << 13)
  88 #define RX_CLKSEL_SSI                   (0x5 << 20)
  89
  90 /*-------------------------------------------------------------------------
  91  * Voltage/DPLL ratios
  92  *-------------------------------------------------------------------------*/
  93
  94 /* 2430 Ratio's, 2430-Ratio Config 1 */
  95 #define R1_CLKSEL_L3                    (4 << 0)
  96 #define R1_CLKSEL_L4                    (2 << 5)
  97 #define R1_CLKSEL_USB                   (4 << 25)
  98 #define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
  99                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 100                                         R1_CLKSEL_L4 | R1_CLKSEL_L3
 101 #define R1_CLKSEL_MPU                   (2 << 0)
 102 #define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
 103 #define R1_CLKSEL_DSP                   (2 << 0)
 104 #define R1_CLKSEL_DSP_IF                (2 << 5)
 105 #define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
 106 #define R1_CLKSEL_GFX                   (2 << 0)
 107 #define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
 108 #define R1_CLKSEL_MDM                   (4 << 0)
 109 #define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
 110
 111 /* 2430-Ratio Config 2 */
 112 #define R2_CLKSEL_L3                    (6 << 0)
 113 #define R2_CLKSEL_L4                    (2 << 5)
 114 #define R2_CLKSEL_USB                   (2 << 25)
 115 #define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
 116                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 117                                         R2_CLKSEL_L4 | R2_CLKSEL_L3
 118 #define R2_CLKSEL_MPU                   (2 << 0)
 119 #define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
 120 #define R2_CLKSEL_DSP                   (2 << 0)
 121 #define R2_CLKSEL_DSP_IF                (3 << 5)
 122 #define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
 123 #define R2_CLKSEL_GFX                   (2 << 0)
 124 #define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
 125 #define R2_CLKSEL_MDM                   (6 << 0)
 126 #define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
 127
 128 /* 2430-Ratio Bootm (BYPASS) */
 129 #define RB_CLKSEL_L3                    (1 << 0)
 130 #define RB_CLKSEL_L4                    (1 << 5)
 131 #define RB_CLKSEL_USB                   (1 << 25)
 132 #define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
 133                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 134                                         RB_CLKSEL_L4 | RB_CLKSEL_L3
 135 #define RB_CLKSEL_MPU                   (1 << 0)
 136 #define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
 137 #define RB_CLKSEL_DSP                   (1 << 0)
 138 #define RB_CLKSEL_DSP_IF                (1 << 5)
 139 #define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
 140 #define RB_CLKSEL_GFX                   (1 << 0)
 141 #define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
 142 #define RB_CLKSEL_MDM                   (1 << 0)
 143 #define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
 144
 145 /* 2420 Ratio Equivalents */
 146 #define RXX_CLKSEL_VLYNQ                (0x12 << 15)
 147 #define RXX_CLKSEL_SSI                  (0x8 << 20)
 148
 149 /* 2420-PRCM III 532MHz core */
 150 #define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
 151 #define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
 152 #define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
 153 #define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
 154                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
 155                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
 156                                         RIII_CLKSEL_L3
 157 #define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
 158 #define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
 159 #define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
 160 #define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
 161 #define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
 162 #define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
 163 #define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
 164 #define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
 165                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
 166                                         RIII_CLKSEL_DSP
 167 #define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
 168 #define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
 169
 170 /* 2420-PRCM II 600MHz core */
 171 #define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
 172 #define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
 173 #define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
 174 #define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
 175                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 176                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 177                                         RII_CLKSEL_L4 | RII_CLKSEL_L3
 178 #define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
 179 #define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
 180 #define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
 181 #define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
 182 #define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
 183 #define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
 184 #define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
 185 #define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
 186                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
 187                                         RII_CLKSEL_DSP
 188 #define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
 189 #define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
 190
 191 /* 2420-PRCM I 660MHz core */
 192 #define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
 193 #define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
 194 #define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
 195 #define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
 196                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
 197                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
 198                                         RI_CLKSEL_L4 | RI_CLKSEL_L3
 199 #define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
 200 #define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
 201 #define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
 202 #define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
 203 #define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
 204 #define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
 205 #define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
 206 #define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
 207                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
 208                                         RI_CLKSEL_DSP
 209 #define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
 210 #define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
 211
 212 /* 2420-PRCM VII (boot) */
 213 #define RVII_CLKSEL_L3                  (1 << 0)
 214 #define RVII_CLKSEL_L4                  (1 << 5)
 215 #define RVII_CLKSEL_DSS1                (1 << 8)
 216 #define RVII_CLKSEL_DSS2                (0 << 13)
 217 #define RVII_CLKSEL_VLYNQ               (1 << 15)
 218 #define RVII_CLKSEL_SSI                 (1 << 20)
 219 #define RVII_CLKSEL_USB                 (1 << 25)
 220
 221 #define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
 222                                         RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
 223                                         RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
 224
 225 #define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
 226 #define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
 227
 228 #define RVII_CLKSEL_DSP                 (1 << 0)
 229 #define RVII_CLKSEL_DSP_IF              (1 << 5)
 230 #define RVII_SYNC_DSP                   (0 << 7)
 231 #define RVII_CLKSEL_IVA                 (1 << 8)
 232 #define RVII_SYNC_IVA                   (0 << 13)
 233 #define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
 234                                         RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
 235
 236 #define RVII_CLKSEL_GFX                 (1 << 0)
 237 #define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
 238
 239 /*-------------------------------------------------------------------------
 240  * 2430 Target modes: Along with each configuration the CPU has several
 241  * modes which goes along with them. Modes mainly are the addition of
 242  * describe DPLL combinations to go along with a ratio.
 243  *-------------------------------------------------------------------------*/
 244
 245 /* Hardware governed */
 246 #define MX_48M_SRC                      (0 << 3)
 247 #define MX_54M_SRC                      (0 << 5)
 248 #define MX_APLLS_CLIKIN_12              (3 << 23)
 249 #define MX_APLLS_CLIKIN_13              (2 << 23)
 250 #define MX_APLLS_CLIKIN_19_2            (0 << 23)
 251
 252 /*
 253  * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
 254  * #2   (ratio1) baseport-target
 255  * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
 256  */
 257 #define M5A_DPLL_MULT_12                (133 << 12)
 258 #define M5A_DPLL_DIV_12                 (5 << 8)
 259 #define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 260                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
 261                                         MX_APLLS_CLIKIN_12
 262 #define M5A_DPLL_MULT_13                (266 << 12)
 263 #define M5A_DPLL_DIV_13                 (12 << 8)
 264 #define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 265                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
 266                                         MX_APLLS_CLIKIN_13
 267 #define M5A_DPLL_MULT_19                (180 << 12)
 268 #define M5A_DPLL_DIV_19                 (12 << 8)
 269 #define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 270                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
 271                                         MX_APLLS_CLIKIN_19_2
 272 /* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
 273 #define M5B_DPLL_MULT_12                (50 << 12)
 274 #define M5B_DPLL_DIV_12                 (2 << 8)
 275 #define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 276                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
 277                                         MX_APLLS_CLIKIN_12
 278 #define M5B_DPLL_MULT_13                (200 << 12)
 279 #define M5B_DPLL_DIV_13                 (12 << 8)
 280
 281 #define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 282                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
 283                                         MX_APLLS_CLIKIN_13
 284 #define M5B_DPLL_MULT_19                (125 << 12)
 285 #define M5B_DPLL_DIV_19                 (31 << 8)
 286 #define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
 287                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
 288                                         MX_APLLS_CLIKIN_19_2
 289 /*
 290  * #4   (ratio2)
 291  * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
 292  */
 293 #define M3_DPLL_MULT_12                 (55 << 12)
 294 #define M3_DPLL_DIV_12                  (1 << 8)
 295 #define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 296                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
 297                                         MX_APLLS_CLIKIN_12
 298 #define M3_DPLL_MULT_13                 (330 << 12)
 299 #define M3_DPLL_DIV_13                  (12 << 8)
 300 #define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
 301                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
 302                                         MX_APLLS_CLIKIN_13
 303 #define M3_DPLL_MULT_19                 (275 << 12)
 304 #define M3_DPLL_DIV_19                  (15 << 8)
 305 #define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
 306                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
 307                                         MX_APLLS_CLIKIN_19_2
 308 /* boot (boot) */
 309 #define MB_DPLL_MULT                    (1 << 12)
 310 #define MB_DPLL_DIV                     (0 << 8)
 311 #define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 312                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_12
 313
 314 #define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 315                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_13
 316
 317 #define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
 318                                         MB_DPLL_MULT | MX_APLLS_CLIKIN_19
 319
 320 /*
 321  * 2430 - chassis (sedna)
 322  * 165 (ratio1) same as above #2
 323  * 150 (ratio1)
 324  * 133 (ratio2) same as above #4
 325  * 110 (ratio2) same as above #3
 326  * 104 (ratio2)
 327  * boot (boot)
 328  */
 329
 330 /* PRCM I target DPLL = 2*330MHz = 660MHz */
 331 #define MI_DPLL_MULT_12                 (55 << 12)
 332 #define MI_DPLL_DIV_12                  (1 << 8)
 333 #define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
 334                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
 335                                         MX_APLLS_CLIKIN_12
 336
 337 /*
 338  * 2420 Equivalent - mode registers
 339  * PRCM II , target DPLL = 2*300MHz = 600MHz
 340  */
 341 #define MII_DPLL_MULT_12                (50 << 12)
 342 #define MII_DPLL_DIV_12                 (1 << 8)
 343 #define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
 344                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
 345                                         MX_APLLS_CLIKIN_12
 346 #define MII_DPLL_MULT_13                (300 << 12)
 347 #define MII_DPLL_DIV_13                 (12 << 8)
 348 #define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
 349                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
 350                                         MX_APLLS_CLIKIN_13
 351
 352 /* PRCM III target DPLL = 2*266 = 532MHz*/
 353 #define MIII_DPLL_MULT_12               (133 << 12)
 354 #define MIII_DPLL_DIV_12                (5 << 8)
 355 #define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
 356                                         MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
 357                                         MX_APLLS_CLIKIN_12
 358 #define MIII_DPLL_MULT_13               (266 << 12)
 359 #define MIII_DPLL_DIV_13                (12 << 8)
 360 #define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
 361                                         MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
 362                                         MX_APLLS_CLIKIN_13
 363
 364 /* PRCM VII (boot bypass) */
 365 #define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
 366 #define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
 367
 368 /* High and low operation value */
 369 #define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
 370 #define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
 371
 372 /* MPU speed defines */
 373 #define S12M    12000000
 374 #define S13M    13000000
 375 #define S19M    19200000
 376 #define S26M    26000000
 377 #define S100M   100000000
 378 #define S133M   133000000
 379 #define S150M   150000000
 380 #define S165M   165000000
 381 #define S200M   200000000
 382 #define S266M   266000000
 383 #define S300M   300000000
 384 #define S330M   330000000
 385 #define S400M   400000000
 386 #define S532M   532000000
 387 #define S600M   600000000
 388 #define S660M   660000000
 389
 390 /*-------------------------------------------------------------------------
 391  * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
 392  * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
 393  * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
 394  * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
 395  *
 396  * Filling in table based on H4 boards and 2430-SDPs variants available.
 397  * There are quite a few more rates combinations which could be defined.
 398  *
 399  * When multiple values are defined the start up will try and choose the
 400  * fastest one. If a 'fast' value is defined, then automatically, the /2
 401  * one should be included as it can be used.    Generally having more that
 402  * one fast set does not make sense, as static timings need to be changed
 403  * to change the set.    The exception is the bypass setting which is
 404  * availble for low power bypass.
 405  *
 406  * Note: This table needs to be sorted, fastest to slowest.
 407  *-------------------------------------------------------------------------*/
 408 static struct prcm_config rate_table[] = {
 409         /* PRCM I - FAST */
 410         {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 411                 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
 412                 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
 413                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
 414                 RATE_IN_242X},
 415
 416         /* PRCM II - FAST */
 417         {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 418                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 419                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 420                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 421                 RATE_IN_242X},
 422
 423         {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
 424                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 425                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 426                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 427                 RATE_IN_242X},
 428
 429         /* PRCM III - FAST */
 430         {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 431                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 432                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 433                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 434                 RATE_IN_242X},
 435
 436         {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
 437                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 438                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 439                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 440                 RATE_IN_242X},
 441
 442         /* PRCM II - SLOW */
 443         {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 444                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 445                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
 446                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 447                 RATE_IN_242X},
 448
 449         {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
 450                 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
 451                 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
 452                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
 453                 RATE_IN_242X},
 454
 455         /* PRCM III - SLOW */
 456         {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 457                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 458                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
 459                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 460                 RATE_IN_242X},
 461
 462         {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
 463                 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
 464                 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
 465                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
 466                 RATE_IN_242X},
 467
 468         /* PRCM-VII (boot-bypass) */
 469         {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
 470                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 471                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
 472                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 473                 RATE_IN_242X},
 474
 475         /* PRCM-VII (boot-bypass) */
 476         {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
 477                 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
 478                 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
 479                 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
 480                 RATE_IN_242X},
 481
 482         /* PRCM #3 - ratio2 (ES2) - FAST */
 483         {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
 484                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 485                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 486                 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
 487                 SDRC_RFR_CTRL_110MHz,
 488                 RATE_IN_243X},
 489
 490         /* PRCM #5a - ratio1 - FAST */
 491         {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
 492                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 493                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 494                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 495                 SDRC_RFR_CTRL_133MHz,
 496                 RATE_IN_243X},
 497
 498         /* PRCM #5b - ratio1 - FAST */
 499         {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
 500                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 501                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 502                 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
 503                 SDRC_RFR_CTRL_100MHz,
 504                 RATE_IN_243X},
 505
 506         /* PRCM #3 - ratio2 (ES2) - SLOW */
 507         {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
 508                 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
 509                 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
 510                 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
 511                 SDRC_RFR_CTRL_110MHz,
 512                 RATE_IN_243X},
 513
 514         /* PRCM #5a - ratio1 - SLOW */
 515         {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
 516                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 517                 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
 518                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 519                 SDRC_RFR_CTRL_133MHz,
 520                 RATE_IN_243X},
 521
 522         /* PRCM #5b - ratio1 - SLOW*/
 523         {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
 524                 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
 525                 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
 526                 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
 527                 SDRC_RFR_CTRL_100MHz,
 528                 RATE_IN_243X},
 529
 530         /* PRCM-boot/bypass */
 531         {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
 532                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 533                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
 534                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 535                 SDRC_RFR_CTRL_BYPASS,
 536                 RATE_IN_243X},
 537
 538         /* PRCM-boot/bypass */
 539         {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
 540                 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
 541                 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
 542                 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
 543                 SDRC_RFR_CTRL_BYPASS,
 544                 RATE_IN_243X},
 545
 546         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 547 };
 548
 549 /*-------------------------------------------------------------------------
 550  * 24xx clock tree.
 551  *
 552  * NOTE:In many cases here we are assigning a 'default' parent. In many
 553  *      cases the parent is selectable. The get/set parent calls will also
 554  *      switch sources.
 555  *
 556  *      Many some clocks say always_enabled, but they can be auto idled for
 557  *      power savings. They will always be available upon clock request.
 558  *
 559  *      Several sources are given initial rates which may be wrong, this will
 560  *      be fixed up in the init func.
 561  *
 562  *      Things are broadly separated below by clock domains. It is
 563  *      noteworthy that most periferals have dependencies on multiple clock
 564  *      domains. Many get their interface clocks from the L4 domain, but get
 565  *      functional clocks from fixed sources or other core domain derived
 566  *      clocks.
 567  *-------------------------------------------------------------------------*/
 568
 569 /* Base external input clocks */
 570 static struct clk func_32k_ck = {
 571         .name           = "func_32k_ck",
 572         .rate           = 32000,
 573         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 574                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 575         .recalc         = &propagate_rate,
 576 };
 577
 578 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
 579 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
 580         .name           = "osc_ck",
 581         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 582                                 RATE_PROPAGATES,
 583         .enable         = &omap2_enable_osc_ck,
 584         .disable        = &omap2_disable_osc_ck,
 585         .recalc         = &omap2_osc_clk_recalc,
 586 };
 587
 588 /* With out modem likely 12MHz, with modem likely 13MHz */
 589 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
 590         .name           = "sys_ck",             /* ~ ref_clk also */
 591         .parent         = &osc_ck,
 592         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 593                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 594         .recalc         = &omap2_sys_clk_recalc,
 595 };
 596
 597 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
 598         .name           = "alt_ck",
 599         .rate           = 54000000,
 600         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 601                                 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 602         .recalc         = &propagate_rate,
 603 };
 604
 605 /*
 606  * Analog domain root source clocks
 607  */
 608
 609 /* dpll_ck, is broken out in to special cases through clksel */
 610 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 611  * deal with this
 612  */
 613
 614 static const struct dpll_data dpll_dd = {
 615         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 616         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 617         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 618         .auto_idle_mask         = OMAP24XX_AUTO_DPLL_MASK,
 619         .auto_idle_val          = 0x3, /* stop DPLL upon idle */
 620 };
 621
 622 static struct clk dpll_ck = {
 623         .name           = "dpll_ck",
 624         .parent         = &sys_ck,              /* Can be func_32k also */
 625         .dpll_data      = &dpll_dd,
 626         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 627                                 RATE_PROPAGATES | ALWAYS_ENABLED,
 628         .recalc         = &omap2_dpll_recalc,
 629         .set_rate       = &omap2_reprogram_dpll,
 630 };
 631
 632 static struct clk apll96_ck = {
 633         .name           = "apll96_ck",
 634         .parent         = &sys_ck,
 635         .rate           = 96000000,
 636         .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 637                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 638         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 639         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 640         .enable         = &omap2_clk_fixed_enable,
 641         .disable        = &omap2_clk_fixed_disable,
 642         .recalc         = &propagate_rate,
 643 };
 644
 645 static struct clk apll54_ck = {
 646         .name           = "apll54_ck",
 647         .parent         = &sys_ck,
 648         .rate           = 54000000,
 649         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 650                                 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 651         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 652         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 653         .enable         = &omap2_clk_fixed_enable,
 654         .disable        = &omap2_clk_fixed_disable,
 655         .recalc         = &propagate_rate,
 656 };
 657
 658 /*
 659  * PRCM digital base sources
 660  */
 661
 662 /* func_54m_ck */
 663
 664 static const struct clksel_rate func_54m_apll54_rates[] = {
 665         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 666         { .div = 0 },
 667 };
 668
 669 static const struct clksel_rate func_54m_alt_rates[] = {
 670         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 671         { .div = 0 },
 672 };
 673
 674 static const struct clksel func_54m_clksel[] = {
 675         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 676         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 677         { .parent = NULL },
 678 };
 679
 680 static struct clk func_54m_ck = {
 681         .name           = "func_54m_ck",
 682         .parent         = &apll54_ck,   /* can also be alt_clk */
 683         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 684                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 685         .init           = &omap2_init_clksel_parent,
 686         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 687         .clksel_mask    = OMAP24XX_54M_SOURCE,
 688         .clksel         = func_54m_clksel,
 689         .recalc         = &omap2_clksel_recalc,
 690 };
 691
 692 static struct clk core_ck = {
 693         .name           = "core_ck",
 694         .parent         = &dpll_ck,             /* can also be 32k */
 695         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 696                                 ALWAYS_ENABLED | RATE_PROPAGATES,
 697         .recalc         = &followparent_recalc,
 698 };
 699
 700 /* func_96m_ck */
 701 static const struct clksel_rate func_96m_apll96_rates[] = {
 702         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 703         { .div = 0 },
 704 };
 705
 706 static const struct clksel_rate func_96m_alt_rates[] = {
 707         { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
 708         { .div = 0 },
 709 };
 710
 711 static const struct clksel func_96m_clksel[] = {
 712         { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
 713         { .parent = &alt_ck,    .rates = func_96m_alt_rates },
 714         { .parent = NULL }
 715 };
 716
 717 /* The parent of this clock is not selectable on 2420. */
 718 static struct clk func_96m_ck = {
 719         .name           = "func_96m_ck",
 720         .parent         = &apll96_ck,
 721         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 722                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 723         .init           = &omap2_init_clksel_parent,
 724         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 725         .clksel_mask    = OMAP2430_96M_SOURCE,
 726         .clksel         = func_96m_clksel,
 727         .recalc         = &omap2_clksel_recalc,
 728         .round_rate     = &omap2_clksel_round_rate,
 729         .set_rate       = &omap2_clksel_set_rate
 730 };
 731
 732 /* func_48m_ck */
 733
 734 static const struct clksel_rate func_48m_apll96_rates[] = {
 735         { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 736         { .div = 0 },
 737 };
 738
 739 static const struct clksel_rate func_48m_alt_rates[] = {
 740         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 741         { .div = 0 },
 742 };
 743
 744 static const struct clksel func_48m_clksel[] = {
 745         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 746         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 747         { .parent = NULL }
 748 };
 749
 750 static struct clk func_48m_ck = {
 751         .name           = "func_48m_ck",
 752         .parent         = &apll96_ck,    /* 96M or Alt */
 753         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 754                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 755         .init           = &omap2_init_clksel_parent,
 756         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 757         .clksel_mask    = OMAP24XX_48M_SOURCE,
 758         .clksel         = func_48m_clksel,
 759         .recalc         = &omap2_clksel_recalc,
 760         .round_rate     = &omap2_clksel_round_rate,
 761         .set_rate       = &omap2_clksel_set_rate
 762 };
 763
 764 static struct clk func_12m_ck = {
 765         .name           = "func_12m_ck",
 766         .parent         = &func_48m_ck,
 767         .fixed_div      = 4,
 768         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 769                                 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
 770         .recalc         = &omap2_fixed_divisor_recalc,
 771 };
 772
 773 /* Secure timer, only available in secure mode */
 774 static struct clk wdt1_osc_ck = {
 775         .name           = "ck_wdt1_osc",
 776         .parent         = &osc_ck,
 777         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 778         .recalc         = &followparent_recalc,
 779 };
 780
 781 /*
 782  * The common_clkout* clksel_rate structs are common to
 783  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 784  * sys_clkout2_* are 2420-only, so the
 785  * clksel_rate flags fields are inaccurate for those clocks. This is
 786  * harmless since access to those clocks are gated by the struct clk
 787  * flags fields, which mark them as 2420-only.
 788  */
 789 static const struct clksel_rate common_clkout_src_core_rates[] = {
 790         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 791         { .div = 0 }
 792 };
 793
 794 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 795         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 796         { .div = 0 }
 797 };
 798
 799 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 800         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
 801         { .div = 0 }
 802 };
 803
 804 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 805         { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
 806         { .div = 0 }
 807 };
 808
 809 static const struct clksel common_clkout_src_clksel[] = {
 810         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 811         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 812         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 813         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 814         { .parent = NULL }
 815 };
 816
 817 static struct clk sys_clkout_src = {
 818         .name           = "sys_clkout_src",
 819         .parent         = &func_54m_ck,
 820         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 821                                 RATE_PROPAGATES,
 822         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 823         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 824         .init           = &omap2_init_clksel_parent,
 825         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 826         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 827         .clksel         = common_clkout_src_clksel,
 828         .recalc         = &omap2_clksel_recalc,
 829         .round_rate     = &omap2_clksel_round_rate,
 830         .set_rate       = &omap2_clksel_set_rate
 831 };
 832
 833 static const struct clksel_rate common_clkout_rates[] = {
 834         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
 835         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 836         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 837         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 838         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 839         { .div = 0 },
 840 };
 841
 842 static const struct clksel sys_clkout_clksel[] = {
 843         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 844         { .parent = NULL }
 845 };
 846
 847 static struct clk sys_clkout = {
 848         .name           = "sys_clkout",
 849         .parent         = &sys_clkout_src,
 850         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 851                                 PARENT_CONTROLS_CLOCK,
 852         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 853         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 854         .clksel         = sys_clkout_clksel,
 855         .recalc         = &omap2_clksel_recalc,
 856         .round_rate     = &omap2_clksel_round_rate,
 857         .set_rate       = &omap2_clksel_set_rate
 858 };
 859
 860 /* In 2430, new in 2420 ES2 */
 861 static struct clk sys_clkout2_src = {
 862         .name           = "sys_clkout2_src",
 863         .parent         = &func_54m_ck,
 864         .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
 865         .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 866         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 867         .init           = &omap2_init_clksel_parent,
 868         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 869         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 870         .clksel         = common_clkout_src_clksel,
 871         .recalc         = &omap2_clksel_recalc,
 872         .round_rate     = &omap2_clksel_round_rate,
 873         .set_rate       = &omap2_clksel_set_rate
 874 };
 875
 876 static const struct clksel sys_clkout2_clksel[] = {
 877         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 878         { .parent = NULL }
 879 };
 880
 881 /* In 2430, new in 2420 ES2 */
 882 static struct clk sys_clkout2 = {
 883         .name           = "sys_clkout2",
 884         .parent         = &sys_clkout2_src,
 885         .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
 886         .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
 887         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 888         .clksel         = sys_clkout2_clksel,
 889         .recalc         = &omap2_clksel_recalc,
 890         .round_rate     = &omap2_clksel_round_rate,
 891         .set_rate       = &omap2_clksel_set_rate
 892 };
 893
 894 static struct clk emul_ck = {
 895         .name           = "emul_ck",
 896         .parent         = &func_54m_ck,
 897         .flags          = CLOCK_IN_OMAP242X,
 898         .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
 899         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 900         .recalc         = &followparent_recalc,
 901
 902 };
 903
 904 /*
 905  * MPU clock domain
 906  *      Clocks:
 907  *              MPU_FCLK, MPU_ICLK
 908  *              INT_M_FCLK, INT_M_I_CLK
 909  *
 910  * - Individual clocks are hardware managed.
 911  * - Base divider comes from: CM_CLKSEL_MPU
 912  *
 913  */
 914 static const struct clksel_rate mpu_core_rates[] = {
 915         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 916         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 917         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 918         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 919         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 920         { .div = 0 },
 921 };
 922
 923 static const struct clksel mpu_clksel[] = {
 924         { .parent = &core_ck, .rates = mpu_core_rates },
 925         { .parent = NULL }
 926 };
 927
 928 static struct clk mpu_ck = {    /* Control cpu */
 929         .name           = "mpu_ck",
 930         .parent         = &core_ck,
 931         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 932                                 ALWAYS_ENABLED | DELAYED_APP |
 933                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
 934         .init           = &omap2_init_clksel_parent,
 935         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 936         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 937         .clksel         = mpu_clksel,
 938         .recalc         = &omap2_clksel_recalc,
 939         .round_rate     = &omap2_clksel_round_rate,
 940         .set_rate       = &omap2_clksel_set_rate
 941 };
 942
 943 /*
 944  * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
 945  * Clocks:
 946  *      2430: IVA2.1_FCLK, IVA2.1_ICLK
 947  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 948  */
 949 /* XXX Okay, this is dumb.  iva2_1fck and dsp_fck are the same clock.
 950  * they should just be treated as such.
 951  */
 952
 953 /* iva2_1_fck */
 954 static const struct clksel_rate iva2_1_fck_core_rates[] = {
 955         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 956         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 957         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 958         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 959         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 960         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 961         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 962         { .div = 0 },
 963 };
 964
 965 static const struct clksel iva2_1_fck_clksel[] = {
 966         { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
 967         { .parent = NULL }
 968 };
 969
 970 static struct clk iva2_1_fck = {
 971         .name           = "iva2_1_fck",
 972         .parent         = &core_ck,
 973         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES |
 974                                 CONFIG_PARTICIPANT,
 975         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 976         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 977         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 978         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 979         .clksel         = iva2_1_fck_clksel,
 980         .recalc         = &omap2_clksel_recalc,
 981         .round_rate     = &omap2_clksel_round_rate,
 982         .set_rate       = &omap2_clksel_set_rate
 983 };
 984
 985 /* iva2_1_ick */
 986 static const struct clksel_rate iva2_1_ick_core_rates[] = {
 987         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
 988         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 989         { .div = 3, .val = 3, .flags = RATE_IN_243X },
 990         { .div = 0 },
 991 };
 992
 993 static const struct clksel iva2_1_ick_clksel[] = {
 994         { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
 995         { .parent = NULL }
 996 };
 997
 998 static struct clk iva2_1_ick = {
 999         .name           = "iva2_1_ick",
1000         .parent         = &iva2_1_fck,
1001         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1002         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1003         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1004         .clksel         = iva2_1_ick_clksel,
1005         .recalc         = &omap2_clksel_recalc,
1006         .round_rate     = &omap2_clksel_round_rate,
1007         .set_rate       = &omap2_clksel_set_rate
1008 };
1009
1010 /*
1011  * Won't be too specific here. The core clock comes into this block
1012  * it is divided then tee'ed. One branch goes directly to xyz enable
1013  * controls. The other branch gets further divided by 2 then possibly
1014  * routed into a synchronizer and out of clocks abc.
1015  */
1016 static const struct clksel_rate dsp_fck_core_rates[] = {
1017         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1018         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1019         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1020         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1021         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1022         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1023         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1024         { .div = 0 },
1025 };
1026
1027 static const struct clksel dsp_fck_clksel[] = {
1028         { .parent = &core_ck, .rates = dsp_fck_core_rates },
1029         { .parent = NULL }
1030 };
1031
1032 static struct clk dsp_fck = {
1033         .name           = "dsp_fck",
1034         .parent         = &core_ck,
1035         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP |
1036                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1037         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1038         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1039         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1040         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
1041         .clksel         = dsp_fck_clksel,
1042         .recalc         = &omap2_clksel_recalc,
1043         .round_rate     = &omap2_clksel_round_rate,
1044         .set_rate       = &omap2_clksel_set_rate
1045 };
1046
1047 static const struct clksel_rate dsp_ick_core_rates[] = {
1048         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1049         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1050         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1051         { .div = 0 },
1052 };
1053
1054 static const struct clksel dsp_ick_clksel[] = {
1055         { .parent = &core_ck, .rates = dsp_ick_core_rates },
1056         { .parent = NULL }
1057 };
1058
1059 static struct clk dsp_ick = {
1060         .name           = "dsp_ick",     /* apparently ipi and isp */
1061         .parent         = &core_ck,
1062         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1063         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1064         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,            /* for ipi */
1065         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1066         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1067         .clksel         = dsp_ick_clksel,
1068         .recalc         = &omap2_clksel_recalc,
1069 };
1070
1071 static const struct clksel_rate iva1_ifck_core_rates[] = {
1072         { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1073         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1074         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1075         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1076         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1077         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1078         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1079         { .div = 0 },
1080 };
1081
1082 static const struct clksel iva1_ifck_clksel[] = {
1083         { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1084         { .parent = NULL }
1085 };
1086
1087 static struct clk iva1_ifck = {
1088         .name           = "iva1_ifck",
1089         .parent         = &core_ck,
1090         .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1091                                 RATE_PROPAGATES | DELAYED_APP,
1092         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1093         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1094         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1095         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
1096         .clksel         = iva1_ifck_clksel,
1097         .recalc         = &omap2_clksel_recalc,
1098         .round_rate     = &omap2_clksel_round_rate,
1099         .set_rate       = &omap2_clksel_set_rate
1100 };
1101
1102 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1103 static struct clk iva1_mpu_int_ifck = {
1104         .name           = "iva1_mpu_int_ifck",
1105         .parent         = &iva1_ifck,
1106         .flags          = CLOCK_IN_OMAP242X,
1107         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
1108         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1109         .fixed_div      = 2,
1110         .recalc         = &omap2_fixed_divisor_recalc,
1111 };
1112
1113 /*
1114  * L3 clock domain
1115  * L3 clocks are used for both interface and functional clocks to
1116  * multiple entities. Some of these clocks are completely managed
1117  * by hardware, and some others allow software control. Hardware
1118  * managed ones general are based on directly CLK_REQ signals and
1119  * various auto idle settings. The functional spec sets many of these
1120  * as 'tie-high' for their enables.
1121  *
1122  * I-CLOCKS:
1123  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1124  *      CAM, HS-USB.
1125  * F-CLOCK
1126  *      SSI.
1127  *
1128  * GPMC memories and SDRC have timing and clock sensitive registers which
1129  * may very well need notification when the clock changes. Currently for low
1130  * operating points, these are taken care of in sleep.S.
1131  */
1132 static const struct clksel_rate core_l3_core_rates[] = {
1133         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1134         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1135         { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1136         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1137         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1138         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1139         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1140         { .div = 0 }
1141 };
1142
1143 static const struct clksel core_l3_clksel[] = {
1144         { .parent = &core_ck, .rates = core_l3_core_rates },
1145         { .parent = NULL }
1146 };
1147
1148 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1149         .name           = "core_l3_ck",
1150         .parent         = &core_ck,
1151         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1152                                 ALWAYS_ENABLED | DELAYED_APP |
1153                                 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1154         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1155         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1156         .clksel         = core_l3_clksel,
1157         .recalc         = &omap2_clksel_recalc,
1158         .round_rate     = &omap2_clksel_round_rate,
1159         .set_rate       = &omap2_clksel_set_rate
1160 };
1161
1162 /* usb_l4_ick */
1163 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1164         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1165         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1166         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1167         { .div = 0 }
1168 };
1169
1170 static const struct clksel usb_l4_ick_clksel[] = {
1171         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1172         { .parent = NULL },
1173 };
1174
1175 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1176         .name           = "usb_l4_ick",
1177         .parent         = &core_l3_ck,
1178         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1179                                 DELAYED_APP | CONFIG_PARTICIPANT,
1180         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1181         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1182         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1183         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
1184         .clksel         = usb_l4_ick_clksel,
1185         .recalc         = &omap2_clksel_recalc,
1186         .round_rate     = &omap2_clksel_round_rate,
1187         .set_rate       = &omap2_clksel_set_rate
1188 };
1189
1190 /*
1191  * SSI is in L3 management domain, its direct parent is core not l3,
1192  * many core power domain entities are grouped into the L3 clock
1193  * domain.
1194  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1195  *
1196  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1197  */
1198 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1199         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1200         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1201         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1202         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1203         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1204         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1205         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1206         { .div = 0 }
1207 };
1208
1209 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1210         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1211         { .parent = NULL }
1212 };
1213
1214 static struct clk ssi_ssr_sst_fck = {
1215         .name           = "ssi_fck",
1216         .parent         = &core_ck,
1217         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1218                                 DELAYED_APP,
1219         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),       /* bit 1 */
1220         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1221         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1222         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
1223         .clksel         = ssi_ssr_sst_fck_clksel,
1224         .recalc         = &omap2_clksel_recalc,
1225         .round_rate     = &omap2_clksel_round_rate,
1226         .set_rate       = &omap2_clksel_set_rate
1227 };
1228
1229 /*
1230  * GFX clock domain
1231  *      Clocks:
1232  * GFX_FCLK, GFX_ICLK
1233  * GFX_CG1(2d), GFX_CG2(3d)
1234  *
1235  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1236  * The 2d and 3d clocks run at a hardware determined
1237  * divided value of fclk.
1238  *
1239  */
1240 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1241
1242 /*
1243  * These clksel_rate/clksel structs are shared between gfx_3d_fck and
1244  * gfx_2d_fck
1245  */
1246 static const struct clksel_rate gfx_fck_core_l3_rates[] = {
1247         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1248         { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1249         { .div = 3, .val = 3, .flags = RATE_IN_243X },
1250         { .div = 4, .val = 4, .flags = RATE_IN_243X },
1251         { .div = 0 }
1252 };
1253
1254 static const struct clksel gfx_fck_clksel[] = {
1255         { .parent = &core_l3_ck, .rates = gfx_fck_core_l3_rates },
1256         { .parent = NULL },
1257 };
1258
1259 static struct clk gfx_3d_fck = {
1260         .name           = "gfx_3d_fck",
1261         .parent         = &core_l3_ck,
1262         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1263         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1264         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1265         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1266         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1267         .clksel         = gfx_fck_clksel,
1268         .recalc         = &omap2_clksel_recalc,
1269         .round_rate     = &omap2_clksel_round_rate,
1270         .set_rate       = &omap2_clksel_set_rate
1271 };
1272
1273 static struct clk gfx_2d_fck = {
1274         .name           = "gfx_2d_fck",
1275         .parent         = &core_l3_ck,
1276         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1277         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
1278         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1279         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1280         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1281         .clksel         = gfx_fck_clksel,
1282         .recalc         = &omap2_clksel_recalc,
1283         .round_rate     = &omap2_clksel_round_rate,
1284         .set_rate       = &omap2_clksel_set_rate
1285 };
1286
1287 static struct clk gfx_ick = {
1288         .name           = "gfx_ick",            /* From l3 */
1289         .parent         = &core_l3_ck,
1290         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1291         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),  /* bit 0 */
1292         .enable_bit     = OMAP_EN_GFX_SHIFT,
1293         .recalc         = &followparent_recalc,
1294 };
1295
1296 /*
1297  * Modem clock domain (2430)
1298  *      CLOCKS:
1299  *              MDM_OSC_CLK
1300  *              MDM_ICLK
1301  * These clocks are usable in chassis mode only.
1302  */
1303 static const struct clksel_rate mdm_ick_core_rates[] = {
1304         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1305         { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1306         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1307         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1308         { .div = 0 }
1309 };
1310
1311 static const struct clksel mdm_ick_clksel[] = {
1312         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1313         { .parent = NULL }
1314 };
1315
1316 static struct clk mdm_ick = {           /* used both as a ick and fck */
1317         .name           = "mdm_ick",
1318         .parent         = &core_ck,
1319         .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1320         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1321         .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1322         .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1323         .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
1324         .clksel         = mdm_ick_clksel,
1325         .recalc         = &omap2_clksel_recalc,
1326         .round_rate     = &omap2_clksel_round_rate,
1327         .set_rate       = &omap2_clksel_set_rate
1328 };
1329
1330 static struct clk mdm_osc_ck = {
1331         .name           = "mdm_osc_ck",
1332         .parent         = &osc_ck,
1333         .flags          = CLOCK_IN_OMAP243X,
1334         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
1335         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1336         .recalc         = &followparent_recalc,
1337 };
1338
1339 /*
1340  * L4 clock management domain
1341  *
1342  * This domain contains lots of interface clocks from the L4 interface, some
1343  * functional clocks.   Fixed APLL functional source clocks are managed in
1344  * this domain.
1345  */
1346 static const struct clksel_rate l4_core_l3_rates[] = {
1347         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1348         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1349         { .div = 0 }
1350 };
1351
1352 static const struct clksel l4_clksel[] = {
1353         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1354         { .parent = NULL }
1355 };
1356
1357 static struct clk l4_ck = {             /* used both as an ick and fck */
1358         .name           = "l4_ck",
1359         .parent         = &core_l3_ck,
1360         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1361                                 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1362         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1363         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1364         .clksel         = l4_clksel,
1365         .recalc         = &omap2_clksel_recalc,
1366         .round_rate     = &omap2_clksel_round_rate,
1367         .set_rate       = &omap2_clksel_set_rate
1368 };
1369
1370 static struct clk ssi_l4_ick = {
1371         .name           = "ssi_l4_ick",
1372         .parent         = &l4_ck,
1373         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1374         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),        /* bit 1 */
1375         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1376         .recalc         = &followparent_recalc,
1377 };
1378
1379 /*
1380  * DSS clock domain
1381  * CLOCKs:
1382  * DSS_L4_ICLK, DSS_L3_ICLK,
1383  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1384  *
1385  * DSS is both initiator and target.
1386  */
1387 /* XXX Add RATE_NOT_VALIDATED */
1388
1389 static const struct clksel_rate dss1_fck_sys_rates[] = {
1390         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1391         { .div = 0 }
1392 };
1393
1394 static const struct clksel_rate dss1_fck_core_rates[] = {
1395         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1396         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1397         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1398         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1399         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1400         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1401         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1402         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1403         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1404         { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1405         { .div = 0 }
1406 };
1407
1408 static const struct clksel dss1_fck_clksel[] = {
1409         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
1410         { .parent = &core_ck, .rates = dss1_fck_core_rates },
1411         { .parent = NULL },
1412 };
1413
1414 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1415         .name           = "dss_ick",
1416         .parent         = &l4_ck,       /* really both l3 and l4 */
1417         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1418         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1419         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1420         .recalc         = &followparent_recalc,
1421 };
1422
1423 static struct clk dss1_fck = {
1424         .name           = "dss1_fck",
1425         .parent         = &core_ck,             /* Core or sys */
1426         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1427                                 DELAYED_APP,
1428         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1429         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1430         .init           = &omap2_init_clksel_parent,
1431         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1432         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
1433         .clksel         = dss1_fck_clksel,
1434         .recalc         = &omap2_clksel_recalc,
1435         .round_rate     = &omap2_clksel_round_rate,
1436         .set_rate       = &omap2_clksel_set_rate
1437 };
1438
1439 static const struct clksel_rate dss2_fck_sys_rates[] = {
1440         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1441         { .div = 0 }
1442 };
1443
1444 static const struct clksel_rate dss2_fck_48m_rates[] = {
1445         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1446         { .div = 0 }
1447 };
1448
1449 static const struct clksel dss2_fck_clksel[] = {
1450         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
1451         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1452         { .parent = NULL }
1453 };
1454
1455 static struct clk dss2_fck = {          /* Alt clk used in power management */
1456         .name           = "dss2_fck",
1457         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1458         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1459                                 DELAYED_APP,
1460         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1461         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1462         .init           = &omap2_init_clksel_parent,
1463         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1464         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
1465         .clksel         = dss2_fck_clksel,
1466         .recalc         = &followparent_recalc,
1467 };
1468
1469 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1470         .name           = "dss_54m_fck",        /* 54m tv clk */
1471         .parent         = &func_54m_ck,
1472         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1473         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1475         .recalc         = &followparent_recalc,
1476 };
1477
1478 /*
1479  * CORE power domain ICLK & FCLK defines.
1480  * Many of the these can have more than one possible parent. Entries
1481  * here will likely have an L4 interface parent, and may have multiple
1482  * functional clock parents.
1483  */
1484 static const struct clksel_rate gpt_32k_rates[] = {
1485         { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1486         { .div = 0 }
1487 };
1488
1489 static const struct clksel_rate gpt_sys_rates[] = {
1490         { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1491         { .div = 0 }
1492 };
1493
1494 static const struct clksel_rate gpt_alt_rates[] = {
1495         { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1496         { .div = 0 }
1497 };
1498
1499 static const struct clksel gpt_clksel[] = {
1500         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1501         { .parent = &sys_ck,      .rates = gpt_sys_rates },
1502         { .parent = &alt_ck,      .rates = gpt_alt_rates },
1503         { .parent = NULL },
1504 };
1505
1506 static struct clk gpt1_ick = {
1507         .name           = "gpt1_ick",
1508         .parent         = &l4_ck,
1509         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1510         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
1511         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1512         .recalc         = &followparent_recalc,
1513 };
1514
1515 static struct clk gpt1_fck = {
1516         .name           = "gpt1_fck",
1517         .parent         = &func_32k_ck,
1518         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1519         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),        /* Bit0 */
1520         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1521         .init           = &omap2_init_clksel_parent,
1522         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1523         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
1524         .clksel         = gpt_clksel,
1525         .recalc         = &omap2_clksel_recalc,
1526         .round_rate     = &omap2_clksel_round_rate,
1527         .set_rate       = &omap2_clksel_set_rate
1528 };
1529
1530 static struct clk gpt2_ick = {
1531         .name           = "gpt2_ick",
1532         .parent         = &l4_ck,
1533         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1534         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit4 */
1535         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1536         .recalc         = &followparent_recalc,
1537 };
1538
1539 static struct clk gpt2_fck = {
1540         .name           = "gpt2_fck",
1541         .parent         = &func_32k_ck,
1542         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1543         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1545         .init           = &omap2_init_clksel_parent,
1546         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1547         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
1548         .clksel         = gpt_clksel,
1549         .recalc         = &omap2_clksel_recalc,
1550 };
1551
1552 static struct clk gpt3_ick = {
1553         .name           = "gpt3_ick",
1554         .parent         = &l4_ck,
1555         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1556         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit5 */
1557         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1558         .recalc         = &followparent_recalc,
1559 };
1560
1561 static struct clk gpt3_fck = {
1562         .name           = "gpt3_fck",
1563         .parent         = &func_32k_ck,
1564         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1565         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1566         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1567         .init           = &omap2_init_clksel_parent,
1568         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1569         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
1570         .clksel         = gpt_clksel,
1571         .recalc         = &omap2_clksel_recalc,
1572 };
1573
1574 static struct clk gpt4_ick = {
1575         .name           = "gpt4_ick",
1576         .parent         = &l4_ck,
1577         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1578         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),        /* Bit6 */
1579         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk gpt4_fck = {
1584         .name           = "gpt4_fck",
1585         .parent         = &func_32k_ck,
1586         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1587         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1588         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1589         .init           = &omap2_init_clksel_parent,
1590         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1591         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
1592         .clksel         = gpt_clksel,
1593         .recalc         = &omap2_clksel_recalc,
1594 };
1595
1596 static struct clk gpt5_ick = {
1597         .name           = "gpt5_ick",
1598         .parent         = &l4_ck,
1599         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1600         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* Bit7 */
1601         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1602         .recalc         = &followparent_recalc,
1603 };
1604
1605 static struct clk gpt5_fck = {
1606         .name           = "gpt5_fck",
1607         .parent         = &func_32k_ck,
1608         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1609         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1610         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1611         .init           = &omap2_init_clksel_parent,
1612         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1613         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
1614         .clksel         = gpt_clksel,
1615         .recalc         = &omap2_clksel_recalc,
1616 };
1617
1618 static struct clk gpt6_ick = {
1619         .name           = "gpt6_ick",
1620         .parent         = &l4_ck,
1621         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1622         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit8 */
1623         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 static struct clk gpt6_fck = {
1628         .name           = "gpt6_fck",
1629         .parent         = &func_32k_ck,
1630         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1632         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1633         .init           = &omap2_init_clksel_parent,
1634         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1635         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
1636         .clksel         = gpt_clksel,
1637         .recalc         = &omap2_clksel_recalc,
1638 };
1639
1640 static struct clk gpt7_ick = {
1641         .name           = "gpt7_ick",
1642         .parent         = &l4_ck,
1643         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1644         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit9 */
1645         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1646         .recalc         = &followparent_recalc,
1647 };
1648
1649 static struct clk gpt7_fck = {
1650         .name           = "gpt7_fck",
1651         .parent         = &func_32k_ck,
1652         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1654         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1655         .init           = &omap2_init_clksel_parent,
1656         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1657         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1658         .clksel         = gpt_clksel,
1659         .recalc         = &omap2_clksel_recalc,
1660 };
1661
1662 static struct clk gpt8_ick = {
1663         .name           = "gpt8_ick",
1664         .parent         = &l4_ck,
1665         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1666         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit10 */
1667         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1668         .recalc         = &followparent_recalc,
1669 };
1670
1671 static struct clk gpt8_fck = {
1672         .name           = "gpt8_fck",
1673         .parent         = &func_32k_ck,
1674         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1675         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1676         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1677         .init           = &omap2_init_clksel_parent,
1678         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1679         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1680         .clksel         = gpt_clksel,
1681         .recalc         = &omap2_clksel_recalc,
1682 };
1683
1684 static struct clk gpt9_ick = {
1685         .name           = "gpt9_ick",
1686         .parent         = &l4_ck,
1687         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1688         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1689         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1690         .recalc         = &followparent_recalc,
1691 };
1692
1693 static struct clk gpt9_fck = {
1694         .name           = "gpt9_fck",
1695         .parent         = &func_32k_ck,
1696         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1697         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1698         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1699         .init           = &omap2_init_clksel_parent,
1700         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1701         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1702         .clksel         = gpt_clksel,
1703         .recalc         = &omap2_clksel_recalc,
1704 };
1705
1706 static struct clk gpt10_ick = {
1707         .name           = "gpt10_ick",
1708         .parent         = &l4_ck,
1709         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1710         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1711         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1712         .recalc         = &followparent_recalc,
1713 };
1714
1715 static struct clk gpt10_fck = {
1716         .name           = "gpt10_fck",
1717         .parent         = &func_32k_ck,
1718         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1719         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1720         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1721         .init           = &omap2_init_clksel_parent,
1722         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1723         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1724         .clksel         = gpt_clksel,
1725         .recalc         = &omap2_clksel_recalc,
1726 };
1727
1728 static struct clk gpt11_ick = {
1729         .name           = "gpt11_ick",
1730         .parent         = &l4_ck,
1731         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1732         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1734         .recalc         = &followparent_recalc,
1735 };
1736
1737 static struct clk gpt11_fck = {
1738         .name           = "gpt11_fck",
1739         .parent         = &func_32k_ck,
1740         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1741         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1742         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1743         .init           = &omap2_init_clksel_parent,
1744         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1745         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1746         .clksel         = gpt_clksel,
1747         .recalc         = &omap2_clksel_recalc,
1748 };
1749
1750 static struct clk gpt12_ick = {
1751         .name           = "gpt12_ick",
1752         .parent         = &l4_ck,
1753         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1754         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),         /* bit14 */
1755         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1756         .recalc         = &followparent_recalc,
1757 };
1758
1759 static struct clk gpt12_fck = {
1760         .name           = "gpt12_fck",
1761         .parent         = &func_32k_ck,
1762         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1763         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1764         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1765         .init           = &omap2_init_clksel_parent,
1766         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1767         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1768         .clksel         = gpt_clksel,
1769         .recalc         = &omap2_clksel_recalc,
1770 };
1771
1772 static struct clk mcbsp1_ick = {
1773         .name           = "mcbsp1_ick",
1774         .parent         = &l4_ck,
1775         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1776         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1778         .recalc         = &followparent_recalc,
1779 };
1780
1781 static struct clk mcbsp1_fck = {
1782         .name           = "mcbsp1_fck",
1783         .parent         = &func_96m_ck,
1784         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1785         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1786         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1787         .recalc         = &followparent_recalc,
1788 };
1789
1790 static struct clk mcbsp2_ick = {
1791         .name           = "mcbsp2_ick",
1792         .parent         = &l4_ck,
1793         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1794         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1795         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1796         .recalc         = &followparent_recalc,
1797 };
1798
1799 static struct clk mcbsp2_fck = {
1800         .name           = "mcbsp2_fck",
1801         .parent         = &func_96m_ck,
1802         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1803         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1804         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1805         .recalc         = &followparent_recalc,
1806 };
1807
1808 static struct clk mcbsp3_ick = {
1809         .name           = "mcbsp3_ick",
1810         .parent         = &l4_ck,
1811         .flags          = CLOCK_IN_OMAP243X,
1812         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1813         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 static struct clk mcbsp3_fck = {
1818         .name           = "mcbsp3_fck",
1819         .parent         = &func_96m_ck,
1820         .flags          = CLOCK_IN_OMAP243X,
1821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1822         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1823         .recalc         = &followparent_recalc,
1824 };
1825
1826 static struct clk mcbsp4_ick = {
1827         .name           = "mcbsp4_ick",
1828         .parent         = &l4_ck,
1829         .flags          = CLOCK_IN_OMAP243X,
1830         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1831         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1832         .recalc         = &followparent_recalc,
1833 };
1834
1835 static struct clk mcbsp4_fck = {
1836         .name           = "mcbsp4_fck",
1837         .parent         = &func_96m_ck,
1838         .flags          = CLOCK_IN_OMAP243X,
1839         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1840         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1841         .recalc         = &followparent_recalc,
1842 };
1843
1844 static struct clk mcbsp5_ick = {
1845         .name           = "mcbsp5_ick",
1846         .parent         = &l4_ck,
1847         .flags          = CLOCK_IN_OMAP243X,
1848         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1849         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1850         .recalc         = &followparent_recalc,
1851 };
1852
1853 static struct clk mcbsp5_fck = {
1854         .name           = "mcbsp5_fck",
1855         .parent         = &func_96m_ck,
1856         .flags          = CLOCK_IN_OMAP243X,
1857         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1858         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1859         .recalc         = &followparent_recalc,
1860 };
1861
1862 static struct clk mcspi1_ick = {
1863         .name           = "mcspi_ick",
1864         .id             = 1,
1865         .parent         = &l4_ck,
1866         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1867         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1868         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1869         .recalc         = &followparent_recalc,
1870 };
1871
1872 static struct clk mcspi1_fck = {
1873         .name           = "mcspi_fck",
1874         .id             = 1,
1875         .parent         = &func_48m_ck,
1876         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1877         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1878         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1879         .recalc         = &followparent_recalc,
1880 };
1881
1882 static struct clk mcspi2_ick = {
1883         .name           = "mcspi_ick",
1884         .id             = 2,
1885         .parent         = &l4_ck,
1886         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1888         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1889         .recalc         = &followparent_recalc,
1890 };
1891
1892 static struct clk mcspi2_fck = {
1893         .name           = "mcspi_fck",
1894         .id             = 2,
1895         .parent         = &func_48m_ck,
1896         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1898         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1899         .recalc         = &followparent_recalc,
1900 };
1901
1902 static struct clk mcspi3_ick = {
1903         .name           = "mcspi_ick",
1904         .id             = 3,
1905         .parent         = &l4_ck,
1906         .flags          = CLOCK_IN_OMAP243X,
1907         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1908         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1909         .recalc         = &followparent_recalc,
1910 };
1911
1912 static struct clk mcspi3_fck = {
1913         .name           = "mcspi_fck",
1914         .id             = 3,
1915         .parent         = &func_48m_ck,
1916         .flags          = CLOCK_IN_OMAP243X,
1917         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1918         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1919         .recalc         = &followparent_recalc,
1920 };
1921
1922 static struct clk uart1_ick = {
1923         .name           = "uart1_ick",
1924         .parent         = &l4_ck,
1925         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1928         .recalc         = &followparent_recalc,
1929 };
1930
1931 static struct clk uart1_fck = {
1932         .name           = "uart1_fck",
1933         .parent         = &func_48m_ck,
1934         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1935         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1936         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1937         .recalc         = &followparent_recalc,
1938 };
1939
1940 static struct clk uart2_ick = {
1941         .name           = "uart2_ick",
1942         .parent         = &l4_ck,
1943         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1944         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1945         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1946         .recalc         = &followparent_recalc,
1947 };
1948
1949 static struct clk uart2_fck = {
1950         .name           = "uart2_fck",
1951         .parent         = &func_48m_ck,
1952         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1953         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1954         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1955         .recalc         = &followparent_recalc,
1956 };
1957
1958 static struct clk uart3_ick = {
1959         .name           = "uart3_ick",
1960         .parent         = &l4_ck,
1961         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1962         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1963         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1964         .recalc         = &followparent_recalc,
1965 };
1966
1967 static struct clk uart3_fck = {
1968         .name           = "uart3_fck",
1969         .parent         = &func_48m_ck,
1970         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1971         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1972         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk gpios_ick = {
1977         .name           = "gpios_ick",
1978         .parent         = &l4_ck,
1979         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1980         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1981         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1982         .recalc         = &followparent_recalc,
1983 };
1984
1985 static struct clk gpios_fck = {
1986         .name           = "gpios_fck",
1987         .parent         = &func_32k_ck,
1988         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1989         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
1990         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1991         .recalc         = &followparent_recalc,
1992 };
1993
1994 static struct clk mpu_wdt_ick = {
1995         .name           = "mpu_wdt_ick",
1996         .parent         = &l4_ck,
1997         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1998         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1999         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2000         .recalc         = &followparent_recalc,
2001 };
2002
2003 static struct clk mpu_wdt_fck = {
2004         .name           = "mpu_wdt_fck",
2005         .parent         = &func_32k_ck,
2006         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2007         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
2008         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2009         .recalc         = &followparent_recalc,
2010 };
2011
2012 static struct clk sync_32k_ick = {
2013         .name           = "sync_32k_ick",
2014         .parent         = &l4_ck,
2015         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2016         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2017         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2018         .recalc         = &followparent_recalc,
2019 };
2020 static struct clk wdt1_ick = {
2021         .name           = "wdt1_ick",
2022         .parent         = &l4_ck,
2023         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2024         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2025         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2026         .recalc         = &followparent_recalc,
2027 };
2028 static struct clk omapctrl_ick = {
2029         .name           = "omapctrl_ick",
2030         .parent         = &l4_ck,
2031         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2032         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2033         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2034         .recalc         = &followparent_recalc,
2035 };
2036 static struct clk icr_ick = {
2037         .name           = "icr_ick",
2038         .parent         = &l4_ck,
2039         .flags          = CLOCK_IN_OMAP243X,
2040         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2041         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2042         .recalc         = &followparent_recalc,
2043 };
2044
2045 static struct clk cam_ick = {
2046         .name           = "cam_ick",
2047         .parent         = &l4_ck,
2048         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2049         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2050         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2051         .recalc         = &followparent_recalc,
2052 };
2053
2054 static struct clk cam_fck = {
2055         .name           = "cam_fck",
2056         .parent         = &func_96m_ck,
2057         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2058         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2059         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2060         .recalc         = &followparent_recalc,
2061 };
2062
2063 static struct clk mailboxes_ick = {
2064         .name           = "mailboxes_ick",
2065         .parent         = &l4_ck,
2066         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2067         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2068         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2069         .recalc         = &followparent_recalc,
2070 };
2071
2072 static struct clk wdt4_ick = {
2073         .name           = "wdt4_ick",
2074         .parent         = &l4_ck,
2075         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2076         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2077         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2078         .recalc         = &followparent_recalc,
2079 };
2080
2081 static struct clk wdt4_fck = {
2082         .name           = "wdt4_fck",
2083         .parent         = &func_32k_ck,
2084         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2085         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2086         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2087         .recalc         = &followparent_recalc,
2088 };
2089
2090 static struct clk wdt3_ick = {
2091         .name           = "wdt3_ick",
2092         .parent         = &l4_ck,
2093         .flags          = CLOCK_IN_OMAP242X,
2094         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2095         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2096         .recalc         = &followparent_recalc,
2097 };
2098
2099 static struct clk wdt3_fck = {
2100         .name           = "wdt3_fck",
2101         .parent         = &func_32k_ck,
2102         .flags          = CLOCK_IN_OMAP242X,
2103         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2104         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2105         .recalc         = &followparent_recalc,
2106 };
2107
2108 static struct clk mspro_ick = {
2109         .name           = "mspro_ick",
2110         .parent         = &l4_ck,
2111         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2112         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2113         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk mspro_fck = {
2118         .name           = "mspro_fck",
2119         .parent         = &func_96m_ck,
2120         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2121         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2122         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2123         .recalc         = &followparent_recalc,
2124 };
2125
2126 static struct clk mmc_ick = {
2127         .name           = "mmc_ick",
2128         .parent         = &l4_ck,
2129         .flags          = CLOCK_IN_OMAP242X,
2130         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2131         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2132         .recalc         = &followparent_recalc,
2133 };
2134
2135 static struct clk mmc_fck = {
2136         .name           = "mmc_fck",
2137         .parent         = &func_96m_ck,
2138         .flags          = CLOCK_IN_OMAP242X,
2139         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2140         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2141         .recalc         = &followparent_recalc,
2142 };
2143
2144 static struct clk fac_ick = {
2145         .name           = "fac_ick",
2146         .parent         = &l4_ck,
2147         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2148         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2149         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2150         .recalc         = &followparent_recalc,
2151 };
2152
2153 static struct clk fac_fck = {
2154         .name           = "fac_fck",
2155         .parent         = &func_12m_ck,
2156         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2157         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2158         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2159         .recalc         = &followparent_recalc,
2160 };
2161
2162 static struct clk eac_ick = {
2163         .name           = "eac_ick",
2164         .parent         = &l4_ck,
2165         .flags          = CLOCK_IN_OMAP242X,
2166         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2167         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2168         .recalc         = &followparent_recalc,
2169 };
2170
2171 static struct clk eac_fck = {
2172         .name           = "eac_fck",
2173         .parent         = &func_96m_ck,
2174         .flags          = CLOCK_IN_OMAP242X,
2175         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2176         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2177         .recalc         = &followparent_recalc,
2178 };
2179
2180 static struct clk hdq_ick = {
2181         .name           = "hdq_ick",
2182         .parent         = &l4_ck,
2183         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2184         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2185         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2186         .recalc         = &followparent_recalc,
2187 };
2188
2189 static struct clk hdq_fck = {
2190         .name           = "hdq_fck",
2191         .parent         = &func_12m_ck,
2192         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2193         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2194         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2195         .recalc         = &followparent_recalc,
2196 };
2197
2198 static struct clk i2c2_ick = {
2199         .name           = "i2c_ick",
2200         .id             = 2,
2201         .parent         = &l4_ck,
2202         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2203         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2204         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2205         .recalc         = &followparent_recalc,
2206 };
2207
2208 static struct clk i2c2_fck = {
2209         .name           = "i2c_fck",
2210         .id             = 2,
2211         .parent         = &func_12m_ck,
2212         .flags          = CLOCK_IN_OMAP242X,
2213         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2214         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2215         .recalc         = &followparent_recalc,
2216 };
2217
2218 static struct clk i2chs2_fck = {
2219         .name           = "i2chs_fck",
2220         .id             = 2,
2221         .parent         = &func_96m_ck,
2222         .flags          = CLOCK_IN_OMAP243X,
2223         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2224         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2225         .recalc         = &followparent_recalc,
2226 };
2227
2228 static struct clk i2c1_ick = {
2229         .name           = "i2c_ick",
2230         .id             = 1,
2231         .parent         = &l4_ck,
2232         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2233         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2234         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2235         .recalc         = &followparent_recalc,
2236 };
2237
2238 static struct clk i2c1_fck = {
2239         .name           = "i2c_fck",
2240         .id             = 1,
2241         .parent         = &func_12m_ck,
2242         .flags          = CLOCK_IN_OMAP242X,
2243         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2244         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2245         .recalc         = &followparent_recalc,
2246 };
2247
2248 static struct clk i2chs1_fck = {
2249         .name           = "i2chs_fck",
2250         .id             = 1,
2251         .parent         = &func_96m_ck,
2252         .flags          = CLOCK_IN_OMAP243X,
2253         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2254         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2255         .recalc         = &followparent_recalc,
2256 };
2257
2258 static struct clk gpmc_fck = {
2259         .name           = "gpmc_fck",
2260         .parent         = &core_l3_ck,
2261         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2262         .recalc         = &followparent_recalc,
2263 };
2264
2265 static struct clk sdma_fck = {
2266         .name           = "sdma_fck",
2267         .parent         = &core_l3_ck,
2268         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2269         .recalc         = &followparent_recalc,
2270 };
2271
2272 static struct clk sdma_ick = {
2273         .name           = "sdma_ick",
2274         .parent         = &l4_ck,
2275         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2276         .recalc         = &followparent_recalc,
2277 };
2278
2279 static struct clk vlynq_ick = {
2280         .name           = "vlynq_ick",
2281         .parent         = &core_l3_ck,
2282         .flags          = CLOCK_IN_OMAP242X,
2283         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2284         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2285         .recalc         = &followparent_recalc,
2286 };
2287
2288 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2289         { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2290         { .div = 0 }
2291 };
2292
2293 static const struct clksel_rate vlynq_fck_core_rates[] = {
2294         { .div = 1, .val = 1, .flags = RATE_IN_242X },
2295         { .div = 2, .val = 2, .flags = RATE_IN_242X },
2296         { .div = 3, .val = 3, .flags = RATE_IN_242X },
2297         { .div = 4, .val = 4, .flags = RATE_IN_242X },
2298         { .div = 6, .val = 6, .flags = RATE_IN_242X },
2299         { .div = 8, .val = 8, .flags = RATE_IN_242X },
2300         { .div = 9, .val = 9, .flags = RATE_IN_242X },
2301         { .div = 12, .val = 12, .flags = RATE_IN_242X },
2302         { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2303         { .div = 18, .val = 18, .flags = RATE_IN_242X },
2304         { .div = 0 }
2305 };
2306
2307 static const struct clksel vlynq_fck_clksel[] = {
2308         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2309         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
2310         { .parent = NULL }
2311 };
2312
2313 static struct clk vlynq_fck = {
2314         .name           = "vlynq_fck",
2315         .parent         = &func_96m_ck,
2316         .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
2317         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2318         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2319         .init           = &omap2_init_clksel_parent,
2320         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2321         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
2322         .clksel         = vlynq_fck_clksel,
2323         .recalc         = &omap2_clksel_recalc,
2324         .round_rate     = &omap2_clksel_round_rate,
2325         .set_rate       = &omap2_clksel_set_rate
2326 };
2327
2328 static struct clk sdrc_ick = {
2329         .name           = "sdrc_ick",
2330         .parent         = &l4_ck,
2331         .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2332         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2333         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2334         .recalc         = &followparent_recalc,
2335 };
2336
2337 static struct clk des_ick = {
2338         .name           = "des_ick",
2339         .parent         = &l4_ck,
2340         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2341         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2342         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2343         .recalc         = &followparent_recalc,
2344 };
2345
2346 static struct clk sha_ick = {
2347         .name           = "sha_ick",
2348         .parent         = &l4_ck,
2349         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2350         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2351         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2352         .recalc         = &followparent_recalc,
2353 };
2354
2355 static struct clk rng_ick = {
2356         .name           = "rng_ick",
2357         .parent         = &l4_ck,
2358         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2359         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2360         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2361         .recalc         = &followparent_recalc,
2362 };
2363
2364 static struct clk aes_ick = {
2365         .name           = "aes_ick",
2366         .parent         = &l4_ck,
2367         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2369         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2370         .recalc         = &followparent_recalc,
2371 };
2372
2373 static struct clk pka_ick = {
2374         .name           = "pka_ick",
2375         .parent         = &l4_ck,
2376         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2377         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2378         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2379         .recalc         = &followparent_recalc,
2380 };
2381
2382 static struct clk usb_fck = {
2383         .name           = "usb_fck",
2384         .parent         = &func_48m_ck,
2385         .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2386         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2387         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2388         .recalc         = &followparent_recalc,
2389 };
2390
2391 static struct clk usbhs_ick = {
2392         .name           = "usbhs_ick",
2393         .parent         = &core_l3_ck,
2394         .flags          = CLOCK_IN_OMAP243X,
2395         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2396         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2397         .recalc         = &followparent_recalc,
2398 };
2399
2400 static struct clk mmchs1_ick = {
2401         .name           = "mmchs1_ick",
2402         .parent         = &l4_ck,
2403         .flags          = CLOCK_IN_OMAP243X,
2404         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2405         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2406         .recalc         = &followparent_recalc,
2407 };
2408
2409 static struct clk mmchs1_fck = {
2410         .name           = "mmchs1_fck",
2411         .parent         = &func_96m_ck,
2412         .flags          = CLOCK_IN_OMAP243X,
2413         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2414         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2415         .recalc         = &followparent_recalc,
2416 };
2417
2418 static struct clk mmchs2_ick = {
2419         .name           = "mmchs2_ick",
2420         .parent         = &l4_ck,
2421         .flags          = CLOCK_IN_OMAP243X,
2422         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2423         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2424         .recalc         = &followparent_recalc,
2425 };
2426
2427 static struct clk mmchs2_fck = {
2428         .name           = "mmchs2_fck",
2429         .parent         = &func_96m_ck,
2430         .flags          = CLOCK_IN_OMAP243X,
2431         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2432         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2433         .recalc         = &followparent_recalc,
2434 };
2435
2436 static struct clk gpio5_ick = {
2437         .name           = "gpio5_ick",
2438         .parent         = &l4_ck,
2439         .flags          = CLOCK_IN_OMAP243X,
2440         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2441         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2442         .recalc         = &followparent_recalc,
2443 };
2444
2445 static struct clk gpio5_fck = {
2446         .name           = "gpio5_fck",
2447         .parent         = &func_32k_ck,
2448         .flags          = CLOCK_IN_OMAP243X,
2449         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2450         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2451         .recalc         = &followparent_recalc,
2452 };
2453
2454 static struct clk mdm_intc_ick = {
2455         .name           = "mdm_intc_ick",
2456         .parent         = &l4_ck,
2457         .flags          = CLOCK_IN_OMAP243X,
2458         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2459         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2460         .recalc         = &followparent_recalc,
2461 };
2462
2463 static struct clk mmchsdb1_fck = {
2464         .name           = "mmchsdb1_fck",
2465         .parent         = &func_32k_ck,
2466         .flags          = CLOCK_IN_OMAP243X,
2467         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2468         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2469         .recalc         = &followparent_recalc,
2470 };
2471
2472 static struct clk mmchsdb2_fck = {
2473         .name           = "mmchsdb2_fck",
2474         .parent         = &func_32k_ck,
2475         .flags          = CLOCK_IN_OMAP243X,
2476         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2477         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2478         .recalc         = &followparent_recalc,
2479 };
2480
2481 /*
2482  * This clock is a composite clock which does entire set changes then
2483  * forces a rebalance. It keys on the MPU speed, but it really could
2484  * be any key speed part of a set in the rate table.
2485  *
2486  * to really change a set, you need memory table sets which get changed
2487  * in sram, pre-notifiers & post notifiers, changing the top set, without
2488  * having low level display recalc's won't work... this is why dpm notifiers
2489  * work, isr's off, walk a list of clocks already _off_ and not messing with
2490  * the bus.
2491  *
2492  * This clock should have no parent. It embodies the entire upper level
2493  * active set. A parent will mess up some of the init also.
2494  */
2495 static struct clk virt_prcm_set = {
2496         .name           = "virt_prcm_set",
2497         .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2498                                 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2499         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2500         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2501         .set_rate       = &omap2_select_table_rate,
2502         .round_rate     = &omap2_round_to_table_rate,
2503 };
2504
2505 static struct clk *onchip_clks[] __initdata = {
2506         /* external root sources */
2507         &func_32k_ck,
2508         &osc_ck,
2509         &sys_ck,
2510         &alt_ck,
2511         /* internal analog sources */
2512         &dpll_ck,
2513         &apll96_ck,
2514         &apll54_ck,
2515         /* internal prcm root sources */
2516         &func_54m_ck,
2517         &core_ck,
2518         &func_96m_ck,
2519         &func_48m_ck,
2520         &func_12m_ck,
2521         &wdt1_osc_ck,
2522         &sys_clkout_src,
2523         &sys_clkout,
2524         &sys_clkout2_src,
2525         &sys_clkout2,
2526         &emul_ck,
2527         /* mpu domain clocks */
2528         &mpu_ck,
2529         /* dsp domain clocks */
2530         &iva2_1_fck,            /* 2430 */
2531         &iva2_1_ick,
2532         &dsp_ick,               /* 2420 */
2533         &dsp_fck,
2534         &iva1_ifck,
2535         &iva1_mpu_int_ifck,
2536         /* GFX domain clocks */
2537         &gfx_3d_fck,
2538         &gfx_2d_fck,
2539         &gfx_ick,
2540         /* Modem domain clocks */
2541         &mdm_ick,
2542         &mdm_osc_ck,
2543         /* DSS domain clocks */
2544         &dss_ick,
2545         &dss1_fck,
2546         &dss2_fck,
2547         &dss_54m_fck,
2548         /* L3 domain clocks */
2549         &core_l3_ck,
2550         &ssi_ssr_sst_fck,
2551         &usb_l4_ick,
2552         /* L4 domain clocks */
2553         &l4_ck,                 /* used as both core_l4 and wu_l4 */
2554         &ssi_l4_ick,
2555         /* virtual meta-group clock */
2556         &virt_prcm_set,
2557         /* general l4 interface ck, multi-parent functional clk */
2558         &gpt1_ick,
2559         &gpt1_fck,
2560         &gpt2_ick,
2561         &gpt2_fck,
2562         &gpt3_ick,
2563         &gpt3_fck,
2564         &gpt4_ick,
2565         &gpt4_fck,
2566         &gpt5_ick,
2567         &gpt5_fck,
2568         &gpt6_ick,
2569         &gpt6_fck,
2570         &gpt7_ick,
2571         &gpt7_fck,
2572         &gpt8_ick,
2573         &gpt8_fck,
2574         &gpt9_ick,
2575         &gpt9_fck,
2576         &gpt10_ick,
2577         &gpt10_fck,
2578         &gpt11_ick,
2579         &gpt11_fck,
2580         &gpt12_ick,
2581         &gpt12_fck,
2582         &mcbsp1_ick,
2583         &mcbsp1_fck,
2584         &mcbsp2_ick,
2585         &mcbsp2_fck,
2586         &mcbsp3_ick,
2587         &mcbsp3_fck,
2588         &mcbsp4_ick,
2589         &mcbsp4_fck,
2590         &mcbsp5_ick,
2591         &mcbsp5_fck,
2592         &mcspi1_ick,
2593         &mcspi1_fck,
2594         &mcspi2_ick,
2595         &mcspi2_fck,
2596         &mcspi3_ick,
2597         &mcspi3_fck,
2598         &uart1_ick,
2599         &uart1_fck,
2600         &uart2_ick,
2601         &uart2_fck,
2602         &uart3_ick,
2603         &uart3_fck,
2604         &gpios_ick,
2605         &gpios_fck,
2606         &mpu_wdt_ick,
2607         &mpu_wdt_fck,
2608         &sync_32k_ick,
2609         &wdt1_ick,
2610         &omapctrl_ick,
2611         &icr_ick,
2612         &cam_fck,
2613         &cam_ick,
2614         &mailboxes_ick,
2615         &wdt4_ick,
2616         &wdt4_fck,
2617         &wdt3_ick,
2618         &wdt3_fck,
2619         &mspro_ick,
2620         &mspro_fck,
2621         &mmc_ick,
2622         &mmc_fck,
2623         &fac_ick,
2624         &fac_fck,
2625         &eac_ick,
2626         &eac_fck,
2627         &hdq_ick,
2628         &hdq_fck,
2629         &i2c1_ick,
2630         &i2c1_fck,
2631         &i2chs1_fck,
2632         &i2c2_ick,
2633         &i2c2_fck,
2634         &i2chs2_fck,
2635         &gpmc_fck,
2636         &sdma_fck,
2637         &sdma_ick,
2638         &vlynq_ick,
2639         &vlynq_fck,
2640         &sdrc_ick,
2641         &des_ick,
2642         &sha_ick,
2643         &rng_ick,
2644         &aes_ick,
2645         &pka_ick,
2646         &usb_fck,
2647         &usbhs_ick,
2648         &mmchs1_ick,
2649         &mmchs1_fck,
2650         &mmchs2_ick,
2651         &mmchs2_fck,
2652         &gpio5_ick,
2653         &gpio5_fck,
2654         &mdm_intc_ick,
2655         &mmchsdb1_fck,
2656         &mmchsdb2_fck,
2657 };
2658
2659 #endif