2 * linux/arch/arm/mach-omap2/clock24xx.h
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Copyright (C) 2004 Nokia corporation
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
12 * Copyright (C) 2007 Texas Instruments, Inc.
13 * Copyright (C) 2007 Nokia Corporation
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
22 #define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
28 #include "prm_regbits_24xx.h"
29 #include "cm_regbits_24xx.h"
32 static void omap2_table_mpu_recalc(struct clk *clk);
33 static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
34 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
35 static void omap2_sys_clk_recalc(struct clk *clk);
36 static void omap2_osc_clk_recalc(struct clk *clk);
37 static void omap2_sys_clk_recalc(struct clk *clk);
38 static void omap2_dpll_recalc(struct clk *clk);
39 static int omap2_clk_fixed_enable(struct clk *clk);
40 static void omap2_clk_fixed_disable(struct clk *clk);
41 static int omap2_enable_osc_ck(struct clk *clk);
42 static void omap2_disable_osc_ck(struct clk *clk);
43 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
45 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
46 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
47 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
50 unsigned long xtal_speed; /* crystal rate */
51 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
52 unsigned long mpu_speed; /* speed of MPU */
53 unsigned long cm_clksel_mpu; /* mpu divider */
54 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
55 unsigned long cm_clksel_gfx; /* gfx dividers */
56 unsigned long cm_clksel1_core; /* major subsystem dividers */
57 unsigned long cm_clksel1_pll; /* m,n */
58 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
59 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
60 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
65 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
66 * These configurations are characterized by voltage and speed for clocks.
67 * The device is only validated for certain combinations. One way to express
68 * these combinations is via the 'ratio's' which the clocks operate with
69 * respect to each other. These ratio sets are for a given voltage/DPLL
70 * setting. All configurations can be described by a DPLL setting and a ratio
71 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
73 * 2430 differs from 2420 in that there are no more phase synchronizers used.
74 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
75 * 2430 (iva2.1, NOdsp, mdm)
78 /* Core fields for cm_clksel, not ratio governed */
79 #define RX_CLKSEL_DSS1 (0x10 << 8)
80 #define RX_CLKSEL_DSS2 (0x0 << 13)
81 #define RX_CLKSEL_SSI (0x5 << 20)
83 /*-------------------------------------------------------------------------
85 *-------------------------------------------------------------------------*/
87 /* 2430 Ratio's, 2430-Ratio Config 1 */
88 #define R1_CLKSEL_L3 (4 << 0)
89 #define R1_CLKSEL_L4 (2 << 5)
90 #define R1_CLKSEL_USB (4 << 25)
91 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
92 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
93 R1_CLKSEL_L4 | R1_CLKSEL_L3
94 #define R1_CLKSEL_MPU (2 << 0)
95 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
96 #define R1_CLKSEL_DSP (2 << 0)
97 #define R1_CLKSEL_DSP_IF (2 << 5)
98 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
99 #define R1_CLKSEL_GFX (2 << 0)
100 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
101 #define R1_CLKSEL_MDM (4 << 0)
102 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
104 /* 2430-Ratio Config 2 */
105 #define R2_CLKSEL_L3 (6 << 0)
106 #define R2_CLKSEL_L4 (2 << 5)
107 #define R2_CLKSEL_USB (2 << 25)
108 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
109 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
110 R2_CLKSEL_L4 | R2_CLKSEL_L3
111 #define R2_CLKSEL_MPU (2 << 0)
112 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
113 #define R2_CLKSEL_DSP (2 << 0)
114 #define R2_CLKSEL_DSP_IF (3 << 5)
115 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
116 #define R2_CLKSEL_GFX (2 << 0)
117 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
118 #define R2_CLKSEL_MDM (6 << 0)
119 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
121 /* 2430-Ratio Bootm (BYPASS) */
122 #define RB_CLKSEL_L3 (1 << 0)
123 #define RB_CLKSEL_L4 (1 << 5)
124 #define RB_CLKSEL_USB (1 << 25)
125 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
126 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
127 RB_CLKSEL_L4 | RB_CLKSEL_L3
128 #define RB_CLKSEL_MPU (1 << 0)
129 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
130 #define RB_CLKSEL_DSP (1 << 0)
131 #define RB_CLKSEL_DSP_IF (1 << 5)
132 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
133 #define RB_CLKSEL_GFX (1 << 0)
134 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
135 #define RB_CLKSEL_MDM (1 << 0)
136 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
138 /* 2420 Ratio Equivalents */
139 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
140 #define RXX_CLKSEL_SSI (0x8 << 20)
142 /* 2420-PRCM III 532MHz core */
143 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
144 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
145 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
146 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
147 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
148 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
150 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
151 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
152 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
153 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
154 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
155 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
156 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
157 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
158 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
160 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
161 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
163 /* 2420-PRCM II 600MHz core */
164 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
165 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
166 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
167 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
168 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
169 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
170 RII_CLKSEL_L4 | RII_CLKSEL_L3
171 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
172 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
173 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
174 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
175 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
176 #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
177 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
178 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
179 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
181 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
182 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
184 /* 2420-PRCM I 660MHz core */
185 #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
186 #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
187 #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
188 #define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
189 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
190 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
191 RI_CLKSEL_L4 | RI_CLKSEL_L3
192 #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
193 #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
194 #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
195 #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
196 #define RI_SYNC_DSP (1 << 7) /* Activate sync */
197 #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
198 #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
199 #define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
200 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
202 #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
203 #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
205 /* 2420-PRCM VII (boot) */
206 #define RVII_CLKSEL_L3 (1 << 0)
207 #define RVII_CLKSEL_L4 (1 << 5)
208 #define RVII_CLKSEL_DSS1 (1 << 8)
209 #define RVII_CLKSEL_DSS2 (0 << 13)
210 #define RVII_CLKSEL_VLYNQ (1 << 15)
211 #define RVII_CLKSEL_SSI (1 << 20)
212 #define RVII_CLKSEL_USB (1 << 25)
214 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
215 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
216 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
218 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
219 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
221 #define RVII_CLKSEL_DSP (1 << 0)
222 #define RVII_CLKSEL_DSP_IF (1 << 5)
223 #define RVII_SYNC_DSP (0 << 7)
224 #define RVII_CLKSEL_IVA (1 << 8)
225 #define RVII_SYNC_IVA (0 << 13)
226 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
227 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
229 #define RVII_CLKSEL_GFX (1 << 0)
230 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
232 /*-------------------------------------------------------------------------
233 * 2430 Target modes: Along with each configuration the CPU has several
234 * modes which goes along with them. Modes mainly are the addition of
235 * describe DPLL combinations to go along with a ratio.
236 *-------------------------------------------------------------------------*/
238 /* Hardware governed */
239 #define MX_48M_SRC (0 << 3)
240 #define MX_54M_SRC (0 << 5)
241 #define MX_APLLS_CLIKIN_12 (3 << 23)
242 #define MX_APLLS_CLIKIN_13 (2 << 23)
243 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
246 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
247 * #2 (ratio1) baseport-target
248 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
250 #define M5A_DPLL_MULT_12 (133 << 12)
251 #define M5A_DPLL_DIV_12 (5 << 8)
252 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
253 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
255 #define M5A_DPLL_MULT_13 (266 << 12)
256 #define M5A_DPLL_DIV_13 (12 << 8)
257 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
258 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
260 #define M5A_DPLL_MULT_19 (180 << 12)
261 #define M5A_DPLL_DIV_19 (12 << 8)
262 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
263 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
265 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
266 #define M5B_DPLL_MULT_12 (50 << 12)
267 #define M5B_DPLL_DIV_12 (2 << 8)
268 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
269 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
271 #define M5B_DPLL_MULT_13 (200 << 12)
272 #define M5B_DPLL_DIV_13 (12 << 8)
274 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
275 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
277 #define M5B_DPLL_MULT_19 (125 << 12)
278 #define M5B_DPLL_DIV_19 (31 << 8)
279 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
280 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
284 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
286 #define M3_DPLL_MULT_12 (55 << 12)
287 #define M3_DPLL_DIV_12 (1 << 8)
288 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
289 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
291 #define M3_DPLL_MULT_13 (330 << 12)
292 #define M3_DPLL_DIV_13 (12 << 8)
293 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
294 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
296 #define M3_DPLL_MULT_19 (275 << 12)
297 #define M3_DPLL_DIV_19 (15 << 8)
298 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
299 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
302 #define MB_DPLL_MULT (1 << 12)
303 #define MB_DPLL_DIV (0 << 8)
304 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
305 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
307 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
308 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
310 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
311 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
314 * 2430 - chassis (sedna)
315 * 165 (ratio1) same as above #2
317 * 133 (ratio2) same as above #4
318 * 110 (ratio2) same as above #3
323 /* PRCM I target DPLL = 2*330MHz = 660MHz */
324 #define MI_DPLL_MULT_12 (55 << 12)
325 #define MI_DPLL_DIV_12 (1 << 8)
326 #define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
327 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
331 * 2420 Equivalent - mode registers
332 * PRCM II , target DPLL = 2*300MHz = 600MHz
334 #define MII_DPLL_MULT_12 (50 << 12)
335 #define MII_DPLL_DIV_12 (1 << 8)
336 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
337 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
339 #define MII_DPLL_MULT_13 (300 << 12)
340 #define MII_DPLL_DIV_13 (12 << 8)
341 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
342 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
345 /* PRCM III target DPLL = 2*266 = 532MHz*/
346 #define MIII_DPLL_MULT_12 (133 << 12)
347 #define MIII_DPLL_DIV_12 (5 << 8)
348 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
349 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
351 #define MIII_DPLL_MULT_13 (266 << 12)
352 #define MIII_DPLL_DIV_13 (12 << 8)
353 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
354 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
357 /* PRCM VII (boot bypass) */
358 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
359 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
361 /* High and low operation value */
362 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
363 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
365 /* MPU speed defines */
366 #define S12M 12000000
367 #define S13M 13000000
368 #define S19M 19200000
369 #define S26M 26000000
370 #define S100M 100000000
371 #define S133M 133000000
372 #define S150M 150000000
373 #define S165M 165000000
374 #define S200M 200000000
375 #define S266M 266000000
376 #define S300M 300000000
377 #define S330M 330000000
378 #define S400M 400000000
379 #define S532M 532000000
380 #define S600M 600000000
381 #define S660M 660000000
383 /*-------------------------------------------------------------------------
384 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
385 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
386 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
387 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
389 * Filling in table based on H4 boards and 2430-SDPs variants available.
390 * There are quite a few more rates combinations which could be defined.
392 * When multiple values are defined the start up will try and choose the
393 * fastest one. If a 'fast' value is defined, then automatically, the /2
394 * one should be included as it can be used. Generally having more that
395 * one fast set does not make sense, as static timings need to be changed
396 * to change the set. The exception is the bypass setting which is
397 * availble for low power bypass.
399 * Note: This table needs to be sorted, fastest to slowest.
400 *-------------------------------------------------------------------------*/
401 static struct prcm_config rate_table[] = {
403 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
404 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
405 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
406 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
410 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
411 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
412 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
413 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
416 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
417 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
418 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
419 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
422 /* PRCM III - FAST */
423 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
424 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
425 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
426 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
429 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
430 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
431 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
432 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
436 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
437 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
438 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
439 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
442 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
443 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
444 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
445 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
448 /* PRCM III - SLOW */
449 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
450 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
451 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
452 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
455 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
456 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
457 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
458 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
461 /* PRCM-VII (boot-bypass) */
462 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
463 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
464 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
465 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
468 /* PRCM-VII (boot-bypass) */
469 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
470 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
471 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
472 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
475 /* PRCM #3 - ratio2 (ES2) - FAST */
476 {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
477 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
478 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
479 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
480 SDRC_RFR_CTRL_110MHz,
483 /* PRCM #5a - ratio1 - FAST */
484 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
485 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
486 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
487 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
488 SDRC_RFR_CTRL_133MHz,
491 /* PRCM #5b - ratio1 - FAST */
492 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
493 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
494 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
495 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
496 SDRC_RFR_CTRL_100MHz,
499 /* PRCM #3 - ratio2 (ES2) - SLOW */
500 {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
501 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
502 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
503 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
504 SDRC_RFR_CTRL_110MHz,
507 /* PRCM #5a - ratio1 - SLOW */
508 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
509 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
510 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
511 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
512 SDRC_RFR_CTRL_133MHz,
515 /* PRCM #5b - ratio1 - SLOW*/
516 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
517 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
518 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
519 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
520 SDRC_RFR_CTRL_100MHz,
523 /* PRCM-boot/bypass */
524 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
525 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
526 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
527 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
528 SDRC_RFR_CTRL_BYPASS,
531 /* PRCM-boot/bypass */
532 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
533 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
534 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
535 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
536 SDRC_RFR_CTRL_BYPASS,
539 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
542 /*-------------------------------------------------------------------------
545 * NOTE:In many cases here we are assigning a 'default' parent. In many
546 * cases the parent is selectable. The get/set parent calls will also
549 * Many some clocks say always_enabled, but they can be auto idled for
550 * power savings. They will always be available upon clock request.
552 * Several sources are given initial rates which may be wrong, this will
553 * be fixed up in the init func.
555 * Things are broadly separated below by clock domains. It is
556 * noteworthy that most periferals have dependencies on multiple clock
557 * domains. Many get their interface clocks from the L4 domain, but get
558 * functional clocks from fixed sources or other core domain derived
560 *-------------------------------------------------------------------------*/
562 /* Base external input clocks */
563 static struct clk func_32k_ck = {
564 .name = "func_32k_ck",
566 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
567 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
568 .recalc = &propagate_rate,
571 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
572 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
574 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
576 .enable = &omap2_enable_osc_ck,
577 .disable = &omap2_disable_osc_ck,
578 .recalc = &omap2_osc_clk_recalc,
581 /* With out modem likely 12MHz, with modem likely 13MHz */
582 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
583 .name = "sys_ck", /* ~ ref_clk also */
585 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
586 ALWAYS_ENABLED | RATE_PROPAGATES,
587 .recalc = &omap2_sys_clk_recalc,
590 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
593 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
594 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
595 .recalc = &propagate_rate,
599 * Analog domain root source clocks
602 /* dpll_ck, is broken out in to special cases through clksel */
603 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
607 static const struct dpll_data dpll_dd = {
608 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
609 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
610 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
613 static struct clk dpll_ck = {
615 .parent = &sys_ck, /* Can be func_32k also */
616 .dpll_data = &dpll_dd,
617 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
618 RATE_PROPAGATES | ALWAYS_ENABLED,
619 .recalc = &omap2_dpll_recalc,
620 .set_rate = &omap2_reprogram_dpll,
623 static struct clk apll96_ck = {
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
629 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
630 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
631 .enable = &omap2_clk_fixed_enable,
632 .disable = &omap2_clk_fixed_disable,
633 .recalc = &propagate_rate,
636 static struct clk apll54_ck = {
640 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
641 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
642 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
643 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
644 .enable = &omap2_clk_fixed_enable,
645 .disable = &omap2_clk_fixed_disable,
646 .recalc = &propagate_rate,
650 * PRCM digital base sources
655 static const struct clksel_rate func_54m_apll54_rates[] = {
656 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
660 static const struct clksel_rate func_54m_alt_rates[] = {
661 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
665 static const struct clksel func_54m_clksel[] = {
666 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
667 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
671 static struct clk func_54m_ck = {
672 .name = "func_54m_ck",
673 .parent = &apll54_ck, /* can also be alt_clk */
674 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
675 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
676 .init = &omap2_init_clksel_parent,
677 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
678 .clksel_mask = OMAP24XX_54M_SOURCE,
679 .clksel = func_54m_clksel,
680 .recalc = &omap2_clksel_recalc,
683 static struct clk core_ck = {
685 .parent = &dpll_ck, /* can also be 32k */
686 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
687 ALWAYS_ENABLED | RATE_PROPAGATES,
688 .recalc = &followparent_recalc,
692 static const struct clksel_rate func_96m_apll96_rates[] = {
693 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
697 static const struct clksel_rate func_96m_alt_rates[] = {
698 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
702 static const struct clksel func_96m_clksel[] = {
703 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
704 { .parent = &alt_ck, .rates = func_96m_alt_rates },
708 /* The parent of this clock is not selectable on 2420. */
709 static struct clk func_96m_ck = {
710 .name = "func_96m_ck",
711 .parent = &apll96_ck,
712 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
713 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
714 .init = &omap2_init_clksel_parent,
715 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
716 .clksel_mask = OMAP2430_96M_SOURCE,
717 .clksel = func_96m_clksel,
718 .recalc = &omap2_clksel_recalc,
719 .round_rate = &omap2_clksel_round_rate,
720 .set_rate = &omap2_clksel_set_rate
725 static const struct clksel_rate func_48m_apll96_rates[] = {
726 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
730 static const struct clksel_rate func_48m_alt_rates[] = {
731 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
735 static const struct clksel func_48m_clksel[] = {
736 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
737 { .parent = &alt_ck, .rates = func_48m_alt_rates },
741 static struct clk func_48m_ck = {
742 .name = "func_48m_ck",
743 .parent = &apll96_ck, /* 96M or Alt */
744 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
745 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
746 .init = &omap2_init_clksel_parent,
747 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
748 .clksel_mask = OMAP24XX_48M_SOURCE,
749 .clksel = func_48m_clksel,
750 .recalc = &omap2_clksel_recalc,
751 .round_rate = &omap2_clksel_round_rate,
752 .set_rate = &omap2_clksel_set_rate
755 static struct clk func_12m_ck = {
756 .name = "func_12m_ck",
757 .parent = &func_48m_ck,
759 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
760 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
761 .recalc = &omap2_fixed_divisor_recalc,
764 /* Secure timer, only available in secure mode */
765 static struct clk wdt1_osc_ck = {
766 .name = "ck_wdt1_osc",
768 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
769 .recalc = &followparent_recalc,
773 * The common_clkout* clksel_rate structs are common to
774 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
775 * sys_clkout2_* are 2420-only, so the
776 * clksel_rate flags fields are inaccurate for those clocks. This is
777 * harmless since access to those clocks are gated by the struct clk
778 * flags fields, which mark them as 2420-only.
780 static const struct clksel_rate common_clkout_src_core_rates[] = {
781 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
785 static const struct clksel_rate common_clkout_src_sys_rates[] = {
786 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
790 static const struct clksel_rate common_clkout_src_96m_rates[] = {
791 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
795 static const struct clksel_rate common_clkout_src_54m_rates[] = {
796 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
800 static const struct clksel common_clkout_src_clksel[] = {
801 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
802 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
803 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
804 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
808 static struct clk sys_clkout_src = {
809 .name = "sys_clkout_src",
810 .parent = &func_54m_ck,
811 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
813 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
814 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
815 .init = &omap2_init_clksel_parent,
816 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
817 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
818 .clksel = common_clkout_src_clksel,
819 .recalc = &omap2_clksel_recalc,
820 .round_rate = &omap2_clksel_round_rate,
821 .set_rate = &omap2_clksel_set_rate
824 static const struct clksel_rate common_clkout_rates[] = {
825 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
826 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
827 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
828 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
829 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
833 static const struct clksel sys_clkout_clksel[] = {
834 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
838 static struct clk sys_clkout = {
839 .name = "sys_clkout",
840 .parent = &sys_clkout_src,
841 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
842 PARENT_CONTROLS_CLOCK,
843 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
844 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
845 .clksel = sys_clkout_clksel,
846 .recalc = &omap2_clksel_recalc,
847 .round_rate = &omap2_clksel_round_rate,
848 .set_rate = &omap2_clksel_set_rate
851 /* In 2430, new in 2420 ES2 */
852 static struct clk sys_clkout2_src = {
853 .name = "sys_clkout2_src",
854 .parent = &func_54m_ck,
855 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
856 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
857 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
858 .init = &omap2_init_clksel_parent,
859 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
860 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
861 .clksel = common_clkout_src_clksel,
862 .recalc = &omap2_clksel_recalc,
863 .round_rate = &omap2_clksel_round_rate,
864 .set_rate = &omap2_clksel_set_rate
867 static const struct clksel sys_clkout2_clksel[] = {
868 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
872 /* In 2430, new in 2420 ES2 */
873 static struct clk sys_clkout2 = {
874 .name = "sys_clkout2",
875 .parent = &sys_clkout2_src,
876 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
877 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
878 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
879 .clksel = sys_clkout2_clksel,
880 .recalc = &omap2_clksel_recalc,
881 .round_rate = &omap2_clksel_round_rate,
882 .set_rate = &omap2_clksel_set_rate
885 static struct clk emul_ck = {
887 .parent = &func_54m_ck,
888 .flags = CLOCK_IN_OMAP242X,
889 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
890 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
891 .recalc = &followparent_recalc,
899 * INT_M_FCLK, INT_M_I_CLK
901 * - Individual clocks are hardware managed.
902 * - Base divider comes from: CM_CLKSEL_MPU
905 static const struct clksel_rate mpu_core_rates[] = {
906 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
907 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
908 { .div = 4, .val = 4, .flags = RATE_IN_242X },
909 { .div = 6, .val = 6, .flags = RATE_IN_242X },
910 { .div = 8, .val = 8, .flags = RATE_IN_242X },
914 static const struct clksel mpu_clksel[] = {
915 { .parent = &core_ck, .rates = mpu_core_rates },
919 static struct clk mpu_ck = { /* Control cpu */
922 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
923 ALWAYS_ENABLED | DELAYED_APP |
924 CONFIG_PARTICIPANT | RATE_PROPAGATES,
925 .init = &omap2_init_clksel_parent,
926 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
927 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
928 .clksel = mpu_clksel,
929 .recalc = &omap2_clksel_recalc,
930 .round_rate = &omap2_clksel_round_rate,
931 .set_rate = &omap2_clksel_set_rate
935 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
937 * 2430: IVA2.1_FCLK, IVA2.1_ICLK
938 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
940 /* XXX Okay, this is dumb. iva2_1fck and dsp_fck are the same clock.
941 * they should just be treated as such.
945 static const struct clksel_rate iva2_1_fck_core_rates[] = {
946 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
947 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
948 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
949 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
950 { .div = 6, .val = 6, .flags = RATE_IN_242X },
951 { .div = 8, .val = 8, .flags = RATE_IN_242X },
952 { .div = 12, .val = 12, .flags = RATE_IN_242X },
956 static const struct clksel iva2_1_fck_clksel[] = {
957 { .parent = &core_ck, .rates = iva2_1_fck_core_rates },
961 static struct clk iva2_1_fck = {
962 .name = "iva2_1_fck",
964 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | RATE_PROPAGATES |
966 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
967 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
968 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
969 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
970 .clksel = iva2_1_fck_clksel,
971 .recalc = &omap2_clksel_recalc,
972 .round_rate = &omap2_clksel_round_rate,
973 .set_rate = &omap2_clksel_set_rate
977 static const struct clksel_rate iva2_1_ick_core_rates[] = {
978 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
979 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
980 { .div = 3, .val = 3, .flags = RATE_IN_243X },
984 static const struct clksel iva2_1_ick_clksel[] = {
985 { .parent = &core_ck, .rates = iva2_1_ick_core_rates },
989 static struct clk iva2_1_ick = {
990 .name = "iva2_1_ick",
991 .parent = &iva2_1_fck,
992 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
993 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
994 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
995 .clksel = iva2_1_ick_clksel,
996 .recalc = &omap2_clksel_recalc,
997 .round_rate = &omap2_clksel_round_rate,
998 .set_rate = &omap2_clksel_set_rate
1002 * Won't be too specific here. The core clock comes into this block
1003 * it is divided then tee'ed. One branch goes directly to xyz enable
1004 * controls. The other branch gets further divided by 2 then possibly
1005 * routed into a synchronizer and out of clocks abc.
1007 static const struct clksel_rate dsp_fck_core_rates[] = {
1008 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1009 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1010 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1011 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1012 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1013 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1014 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1018 static const struct clksel dsp_fck_clksel[] = {
1019 { .parent = &core_ck, .rates = dsp_fck_core_rates },
1023 static struct clk dsp_fck = {
1026 .flags = CLOCK_IN_OMAP242X | DELAYED_APP |
1027 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1028 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1029 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1030 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1031 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
1032 .clksel = dsp_fck_clksel,
1033 .recalc = &omap2_clksel_recalc,
1034 .round_rate = &omap2_clksel_round_rate,
1035 .set_rate = &omap2_clksel_set_rate
1038 static const struct clksel_rate dsp_ick_core_rates[] = {
1039 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1040 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1041 { .div = 3, .val = 3, .flags = RATE_IN_243X },
1045 static const struct clksel dsp_ick_clksel[] = {
1046 { .parent = &core_ck, .rates = dsp_ick_core_rates },
1050 static struct clk dsp_ick = {
1051 .name = "dsp_ick", /* apparently ipi and isp */
1053 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1054 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1055 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1056 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1057 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1058 .clksel = dsp_ick_clksel,
1059 .recalc = &omap2_clksel_recalc,
1062 static const struct clksel_rate iva1_ifck_core_rates[] = {
1063 { .div = 1, .val = 1, .flags = RATE_IN_242X | DEFAULT_RATE },
1064 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1065 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1066 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1067 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1068 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1069 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1073 static const struct clksel iva1_ifck_clksel[] = {
1074 { .parent = &core_ck, .rates = iva1_ifck_core_rates },
1078 static struct clk iva1_ifck = {
1079 .name = "iva1_ifck",
1081 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1082 RATE_PROPAGATES | DELAYED_APP,
1083 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1084 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1085 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1086 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
1087 .clksel = iva1_ifck_clksel,
1088 .recalc = &omap2_clksel_recalc,
1089 .round_rate = &omap2_clksel_round_rate,
1090 .set_rate = &omap2_clksel_set_rate
1093 /* IVA1 mpu/int/i/f clocks are /2 of parent */
1094 static struct clk iva1_mpu_int_ifck = {
1095 .name = "iva1_mpu_int_ifck",
1096 .parent = &iva1_ifck,
1097 .flags = CLOCK_IN_OMAP242X,
1098 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1099 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1101 .recalc = &omap2_fixed_divisor_recalc,
1106 * L3 clocks are used for both interface and functional clocks to
1107 * multiple entities. Some of these clocks are completely managed
1108 * by hardware, and some others allow software control. Hardware
1109 * managed ones general are based on directly CLK_REQ signals and
1110 * various auto idle settings. The functional spec sets many of these
1111 * as 'tie-high' for their enables.
1114 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
1119 * GPMC memories and SDRC have timing and clock sensitive registers which
1120 * may very well need notification when the clock changes. Currently for low
1121 * operating points, these are taken care of in sleep.S.
1123 static const struct clksel_rate core_l3_core_rates[] = {
1124 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1125 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1126 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
1127 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1128 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1129 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1130 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1134 static const struct clksel core_l3_clksel[] = {
1135 { .parent = &core_ck, .rates = core_l3_core_rates },
1139 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1140 .name = "core_l3_ck",
1142 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1143 ALWAYS_ENABLED | DELAYED_APP |
1144 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1145 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1146 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1147 .clksel = core_l3_clksel,
1148 .recalc = &omap2_clksel_recalc,
1149 .round_rate = &omap2_clksel_round_rate,
1150 .set_rate = &omap2_clksel_set_rate
1154 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1155 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1156 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1157 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1161 static const struct clksel usb_l4_ick_clksel[] = {
1162 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1166 static struct clk usb_l4_ick = { /* FS-USB interface clock */
1167 .name = "usb_l4_ick",
1168 .parent = &core_l3_ck,
1169 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1170 DELAYED_APP | CONFIG_PARTICIPANT,
1171 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1172 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1173 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1174 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
1175 .clksel = usb_l4_ick_clksel,
1176 .recalc = &omap2_clksel_recalc,
1177 .round_rate = &omap2_clksel_round_rate,
1178 .set_rate = &omap2_clksel_set_rate
1182 * SSI is in L3 management domain, its direct parent is core not l3,
1183 * many core power domain entities are grouped into the L3 clock
1185 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
1187 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1189 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1190 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1191 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1192 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1193 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1194 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1195 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1196 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1200 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1201 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1205 static struct clk ssi_ssr_sst_fck = {
1208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1210 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1211 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1212 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1213 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
1214 .clksel = ssi_ssr_sst_fck_clksel,
1215 .recalc = &omap2_clksel_recalc,
1216 .round_rate = &omap2_clksel_round_rate,
1217 .set_rate = &omap2_clksel_set_rate
1223 * GFX_FCLK, GFX_ICLK
1224 * GFX_CG1(2d), GFX_CG2(3d)
1226 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
1227 * The 2d and 3d clocks run at a hardware determined
1228 * divided value of fclk.
1231 /* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
1233 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
1234 static const struct clksel gfx_fck_clksel[] = {
1235 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
1239 static struct clk gfx_3d_fck = {
1240 .name = "gfx_3d_fck",
1241 .parent = &core_l3_ck,
1242 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1243 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1244 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1245 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1246 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1247 .clksel = gfx_fck_clksel,
1248 .recalc = &omap2_clksel_recalc,
1249 .round_rate = &omap2_clksel_round_rate,
1250 .set_rate = &omap2_clksel_set_rate
1253 static struct clk gfx_2d_fck = {
1254 .name = "gfx_2d_fck",
1255 .parent = &core_l3_ck,
1256 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1257 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1258 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1259 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1260 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1261 .clksel = gfx_fck_clksel,
1262 .recalc = &omap2_clksel_recalc,
1263 .round_rate = &omap2_clksel_round_rate,
1264 .set_rate = &omap2_clksel_set_rate
1267 static struct clk gfx_ick = {
1268 .name = "gfx_ick", /* From l3 */
1269 .parent = &core_l3_ck,
1270 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1271 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1272 .enable_bit = OMAP_EN_GFX_SHIFT,
1273 .recalc = &followparent_recalc,
1277 * Modem clock domain (2430)
1281 * These clocks are usable in chassis mode only.
1283 static const struct clksel_rate mdm_ick_core_rates[] = {
1284 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1285 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
1286 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1287 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1291 static const struct clksel mdm_ick_clksel[] = {
1292 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1296 static struct clk mdm_ick = { /* used both as a ick and fck */
1299 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1300 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1301 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1302 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1303 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
1304 .clksel = mdm_ick_clksel,
1305 .recalc = &omap2_clksel_recalc,
1306 .round_rate = &omap2_clksel_round_rate,
1307 .set_rate = &omap2_clksel_set_rate
1310 static struct clk mdm_osc_ck = {
1311 .name = "mdm_osc_ck",
1313 .flags = CLOCK_IN_OMAP243X,
1314 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1315 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1316 .recalc = &followparent_recalc,
1320 * L4 clock management domain
1322 * This domain contains lots of interface clocks from the L4 interface, some
1323 * functional clocks. Fixed APLL functional source clocks are managed in
1326 static const struct clksel_rate l4_core_l3_rates[] = {
1327 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1328 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1332 static const struct clksel l4_clksel[] = {
1333 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1337 static struct clk l4_ck = { /* used both as an ick and fck */
1339 .parent = &core_l3_ck,
1340 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1341 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1342 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1343 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1344 .clksel = l4_clksel,
1345 .recalc = &omap2_clksel_recalc,
1346 .round_rate = &omap2_clksel_round_rate,
1347 .set_rate = &omap2_clksel_set_rate
1350 static struct clk ssi_l4_ick = {
1351 .name = "ssi_l4_ick",
1353 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1354 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1355 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1356 .recalc = &followparent_recalc,
1362 * DSS_L4_ICLK, DSS_L3_ICLK,
1363 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
1365 * DSS is both initiator and target.
1367 /* XXX Add RATE_NOT_VALIDATED */
1369 static const struct clksel_rate dss1_fck_sys_rates[] = {
1370 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1374 static const struct clksel_rate dss1_fck_core_rates[] = {
1375 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1376 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1377 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1378 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1379 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
1380 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
1381 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
1382 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
1383 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
1384 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
1388 static const struct clksel dss1_fck_clksel[] = {
1389 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
1390 { .parent = &core_ck, .rates = dss1_fck_core_rates },
1394 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1396 .parent = &l4_ck, /* really both l3 and l4 */
1397 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1398 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1399 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1400 .recalc = &followparent_recalc,
1403 static struct clk dss1_fck = {
1405 .parent = &core_ck, /* Core or sys */
1406 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1408 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1409 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1410 .init = &omap2_init_clksel_parent,
1411 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1412 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
1413 .clksel = dss1_fck_clksel,
1414 .recalc = &omap2_clksel_recalc,
1415 .round_rate = &omap2_clksel_round_rate,
1416 .set_rate = &omap2_clksel_set_rate
1419 static const struct clksel_rate dss2_fck_sys_rates[] = {
1420 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
1424 static const struct clksel_rate dss2_fck_48m_rates[] = {
1425 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1429 static const struct clksel dss2_fck_clksel[] = {
1430 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
1431 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
1435 static struct clk dss2_fck = { /* Alt clk used in power management */
1437 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1438 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1441 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1442 .init = &omap2_init_clksel_parent,
1443 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1444 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
1445 .clksel = dss2_fck_clksel,
1446 .recalc = &followparent_recalc,
1449 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1450 .name = "dss_54m_fck", /* 54m tv clk */
1451 .parent = &func_54m_ck,
1452 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1453 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1455 .recalc = &followparent_recalc,
1459 * CORE power domain ICLK & FCLK defines.
1460 * Many of the these can have more than one possible parent. Entries
1461 * here will likely have an L4 interface parent, and may have multiple
1462 * functional clock parents.
1464 static const struct clksel_rate gpt_alt_rates[] = {
1465 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
1469 static const struct clksel omap24xx_gpt_clksel[] = {
1470 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
1471 { .parent = &sys_ck, .rates = gpt_sys_rates },
1472 { .parent = &alt_ck, .rates = gpt_alt_rates },
1476 static struct clk gpt1_ick = {
1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1480 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1481 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1482 .recalc = &followparent_recalc,
1485 static struct clk gpt1_fck = {
1487 .parent = &func_32k_ck,
1488 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1489 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1490 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1491 .init = &omap2_init_clksel_parent,
1492 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
1493 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
1494 .clksel = omap24xx_gpt_clksel,
1495 .recalc = &omap2_clksel_recalc,
1496 .round_rate = &omap2_clksel_round_rate,
1497 .set_rate = &omap2_clksel_set_rate
1500 static struct clk gpt2_ick = {
1503 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1504 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1505 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1506 .recalc = &followparent_recalc,
1509 static struct clk gpt2_fck = {
1511 .parent = &func_32k_ck,
1512 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1515 .init = &omap2_init_clksel_parent,
1516 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1517 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
1518 .clksel = omap24xx_gpt_clksel,
1519 .recalc = &omap2_clksel_recalc,
1522 static struct clk gpt3_ick = {
1525 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1526 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1527 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1528 .recalc = &followparent_recalc,
1531 static struct clk gpt3_fck = {
1533 .parent = &func_32k_ck,
1534 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1536 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1537 .init = &omap2_init_clksel_parent,
1538 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1539 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
1540 .clksel = omap24xx_gpt_clksel,
1541 .recalc = &omap2_clksel_recalc,
1544 static struct clk gpt4_ick = {
1547 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1548 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1549 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1550 .recalc = &followparent_recalc,
1553 static struct clk gpt4_fck = {
1555 .parent = &func_32k_ck,
1556 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1557 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1558 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1559 .init = &omap2_init_clksel_parent,
1560 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1561 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
1562 .clksel = omap24xx_gpt_clksel,
1563 .recalc = &omap2_clksel_recalc,
1566 static struct clk gpt5_ick = {
1569 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1571 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1572 .recalc = &followparent_recalc,
1575 static struct clk gpt5_fck = {
1577 .parent = &func_32k_ck,
1578 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1580 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1581 .init = &omap2_init_clksel_parent,
1582 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1583 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
1584 .clksel = omap24xx_gpt_clksel,
1585 .recalc = &omap2_clksel_recalc,
1588 static struct clk gpt6_ick = {
1591 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1592 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1593 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1594 .recalc = &followparent_recalc,
1597 static struct clk gpt6_fck = {
1599 .parent = &func_32k_ck,
1600 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1601 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1602 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1603 .init = &omap2_init_clksel_parent,
1604 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1605 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
1606 .clksel = omap24xx_gpt_clksel,
1607 .recalc = &omap2_clksel_recalc,
1610 static struct clk gpt7_ick = {
1613 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1614 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1615 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1616 .recalc = &followparent_recalc,
1619 static struct clk gpt7_fck = {
1621 .parent = &func_32k_ck,
1622 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1623 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1624 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1625 .init = &omap2_init_clksel_parent,
1626 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1627 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1628 .clksel = omap24xx_gpt_clksel,
1629 .recalc = &omap2_clksel_recalc,
1632 static struct clk gpt8_ick = {
1635 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1636 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1637 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1638 .recalc = &followparent_recalc,
1641 static struct clk gpt8_fck = {
1643 .parent = &func_32k_ck,
1644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1645 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1646 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1647 .init = &omap2_init_clksel_parent,
1648 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1649 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1650 .clksel = omap24xx_gpt_clksel,
1651 .recalc = &omap2_clksel_recalc,
1654 static struct clk gpt9_ick = {
1657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1658 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1659 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1660 .recalc = &followparent_recalc,
1663 static struct clk gpt9_fck = {
1665 .parent = &func_32k_ck,
1666 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1667 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1668 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1669 .init = &omap2_init_clksel_parent,
1670 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1671 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1672 .clksel = omap24xx_gpt_clksel,
1673 .recalc = &omap2_clksel_recalc,
1676 static struct clk gpt10_ick = {
1677 .name = "gpt10_ick",
1679 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1681 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1682 .recalc = &followparent_recalc,
1685 static struct clk gpt10_fck = {
1686 .name = "gpt10_fck",
1687 .parent = &func_32k_ck,
1688 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1690 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1691 .init = &omap2_init_clksel_parent,
1692 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1693 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1694 .clksel = omap24xx_gpt_clksel,
1695 .recalc = &omap2_clksel_recalc,
1698 static struct clk gpt11_ick = {
1699 .name = "gpt11_ick",
1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1703 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1704 .recalc = &followparent_recalc,
1707 static struct clk gpt11_fck = {
1708 .name = "gpt11_fck",
1709 .parent = &func_32k_ck,
1710 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1711 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1712 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1713 .init = &omap2_init_clksel_parent,
1714 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1715 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1716 .clksel = omap24xx_gpt_clksel,
1717 .recalc = &omap2_clksel_recalc,
1720 static struct clk gpt12_ick = {
1721 .name = "gpt12_ick",
1723 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1724 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1725 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1726 .recalc = &followparent_recalc,
1729 static struct clk gpt12_fck = {
1730 .name = "gpt12_fck",
1731 .parent = &func_32k_ck,
1732 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1733 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1734 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1735 .init = &omap2_init_clksel_parent,
1736 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1737 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1738 .clksel = omap24xx_gpt_clksel,
1739 .recalc = &omap2_clksel_recalc,
1742 static struct clk mcbsp1_ick = {
1743 .name = "mcbsp1_ick",
1745 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1746 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1747 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1748 .recalc = &followparent_recalc,
1751 static struct clk mcbsp1_fck = {
1752 .name = "mcbsp1_fck",
1753 .parent = &func_96m_ck,
1754 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1756 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1757 .recalc = &followparent_recalc,
1760 static struct clk mcbsp2_ick = {
1761 .name = "mcbsp2_ick",
1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1765 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1766 .recalc = &followparent_recalc,
1769 static struct clk mcbsp2_fck = {
1770 .name = "mcbsp2_fck",
1771 .parent = &func_96m_ck,
1772 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1773 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1774 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1775 .recalc = &followparent_recalc,
1778 static struct clk mcbsp3_ick = {
1779 .name = "mcbsp3_ick",
1781 .flags = CLOCK_IN_OMAP243X,
1782 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1783 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1784 .recalc = &followparent_recalc,
1787 static struct clk mcbsp3_fck = {
1788 .name = "mcbsp3_fck",
1789 .parent = &func_96m_ck,
1790 .flags = CLOCK_IN_OMAP243X,
1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1792 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1793 .recalc = &followparent_recalc,
1796 static struct clk mcbsp4_ick = {
1797 .name = "mcbsp4_ick",
1799 .flags = CLOCK_IN_OMAP243X,
1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1801 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1802 .recalc = &followparent_recalc,
1805 static struct clk mcbsp4_fck = {
1806 .name = "mcbsp4_fck",
1807 .parent = &func_96m_ck,
1808 .flags = CLOCK_IN_OMAP243X,
1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1810 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1811 .recalc = &followparent_recalc,
1814 static struct clk mcbsp5_ick = {
1815 .name = "mcbsp5_ick",
1817 .flags = CLOCK_IN_OMAP243X,
1818 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1819 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1820 .recalc = &followparent_recalc,
1823 static struct clk mcbsp5_fck = {
1824 .name = "mcbsp5_fck",
1825 .parent = &func_96m_ck,
1826 .flags = CLOCK_IN_OMAP243X,
1827 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1828 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1829 .recalc = &followparent_recalc,
1832 static struct clk mcspi1_ick = {
1833 .name = "mcspi_ick",
1836 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1837 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1838 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1839 .recalc = &followparent_recalc,
1842 static struct clk mcspi1_fck = {
1843 .name = "mcspi_fck",
1845 .parent = &func_48m_ck,
1846 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1848 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1849 .recalc = &followparent_recalc,
1852 static struct clk mcspi2_ick = {
1853 .name = "mcspi_ick",
1856 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1857 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1858 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1859 .recalc = &followparent_recalc,
1862 static struct clk mcspi2_fck = {
1863 .name = "mcspi_fck",
1865 .parent = &func_48m_ck,
1866 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1867 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1868 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1869 .recalc = &followparent_recalc,
1872 static struct clk mcspi3_ick = {
1873 .name = "mcspi_ick",
1876 .flags = CLOCK_IN_OMAP243X,
1877 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1878 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1879 .recalc = &followparent_recalc,
1882 static struct clk mcspi3_fck = {
1883 .name = "mcspi_fck",
1885 .parent = &func_48m_ck,
1886 .flags = CLOCK_IN_OMAP243X,
1887 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1888 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1889 .recalc = &followparent_recalc,
1892 static struct clk uart1_ick = {
1893 .name = "uart1_ick",
1895 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1896 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1897 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1898 .recalc = &followparent_recalc,
1901 static struct clk uart1_fck = {
1902 .name = "uart1_fck",
1903 .parent = &func_48m_ck,
1904 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1906 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1907 .recalc = &followparent_recalc,
1910 static struct clk uart2_ick = {
1911 .name = "uart2_ick",
1913 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1914 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1915 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1916 .recalc = &followparent_recalc,
1919 static struct clk uart2_fck = {
1920 .name = "uart2_fck",
1921 .parent = &func_48m_ck,
1922 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1923 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1924 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1925 .recalc = &followparent_recalc,
1928 static struct clk uart3_ick = {
1929 .name = "uart3_ick",
1931 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1932 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1933 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1934 .recalc = &followparent_recalc,
1937 static struct clk uart3_fck = {
1938 .name = "uart3_fck",
1939 .parent = &func_48m_ck,
1940 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1941 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1942 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1943 .recalc = &followparent_recalc,
1946 static struct clk gpios_ick = {
1947 .name = "gpios_ick",
1949 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1950 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1951 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1952 .recalc = &followparent_recalc,
1955 static struct clk gpios_fck = {
1956 .name = "gpios_fck",
1957 .parent = &func_32k_ck,
1958 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1959 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1960 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1961 .recalc = &followparent_recalc,
1964 static struct clk mpu_wdt_ick = {
1965 .name = "mpu_wdt_ick",
1967 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1968 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1969 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1970 .recalc = &followparent_recalc,
1973 static struct clk mpu_wdt_fck = {
1974 .name = "mpu_wdt_fck",
1975 .parent = &func_32k_ck,
1976 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1977 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1978 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1979 .recalc = &followparent_recalc,
1982 static struct clk sync_32k_ick = {
1983 .name = "sync_32k_ick",
1985 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
1986 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1987 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1988 .recalc = &followparent_recalc,
1990 static struct clk wdt1_ick = {
1993 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1994 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1995 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1996 .recalc = &followparent_recalc,
1998 static struct clk omapctrl_ick = {
1999 .name = "omapctrl_ick",
2001 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2002 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2003 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2004 .recalc = &followparent_recalc,
2006 static struct clk icr_ick = {
2009 .flags = CLOCK_IN_OMAP243X,
2010 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2011 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2012 .recalc = &followparent_recalc,
2015 static struct clk cam_ick = {
2018 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2020 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2021 .recalc = &followparent_recalc,
2024 static struct clk cam_fck = {
2026 .parent = &func_96m_ck,
2027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2028 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2029 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2030 .recalc = &followparent_recalc,
2033 static struct clk mailboxes_ick = {
2034 .name = "mailboxes_ick",
2036 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2037 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2038 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2039 .recalc = &followparent_recalc,
2042 static struct clk wdt4_ick = {
2045 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2046 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2047 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2048 .recalc = &followparent_recalc,
2051 static struct clk wdt4_fck = {
2053 .parent = &func_32k_ck,
2054 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2055 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2056 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2057 .recalc = &followparent_recalc,
2060 static struct clk wdt3_ick = {
2063 .flags = CLOCK_IN_OMAP242X,
2064 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2065 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2066 .recalc = &followparent_recalc,
2069 static struct clk wdt3_fck = {
2071 .parent = &func_32k_ck,
2072 .flags = CLOCK_IN_OMAP242X,
2073 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2074 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2075 .recalc = &followparent_recalc,
2078 static struct clk mspro_ick = {
2079 .name = "mspro_ick",
2081 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2082 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2083 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2084 .recalc = &followparent_recalc,
2087 static struct clk mspro_fck = {
2088 .name = "mspro_fck",
2089 .parent = &func_96m_ck,
2090 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2091 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2092 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2093 .recalc = &followparent_recalc,
2096 static struct clk mmc_ick = {
2099 .flags = CLOCK_IN_OMAP242X,
2100 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2101 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2102 .recalc = &followparent_recalc,
2105 static struct clk mmc_fck = {
2107 .parent = &func_96m_ck,
2108 .flags = CLOCK_IN_OMAP242X,
2109 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2110 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2111 .recalc = &followparent_recalc,
2114 static struct clk fac_ick = {
2117 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2118 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2119 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2120 .recalc = &followparent_recalc,
2123 static struct clk fac_fck = {
2125 .parent = &func_12m_ck,
2126 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2127 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2128 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2129 .recalc = &followparent_recalc,
2132 static struct clk eac_ick = {
2135 .flags = CLOCK_IN_OMAP242X,
2136 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2137 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2138 .recalc = &followparent_recalc,
2141 static struct clk eac_fck = {
2143 .parent = &func_96m_ck,
2144 .flags = CLOCK_IN_OMAP242X,
2145 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2146 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2147 .recalc = &followparent_recalc,
2150 static struct clk hdq_ick = {
2153 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2154 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2155 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2156 .recalc = &followparent_recalc,
2159 static struct clk hdq_fck = {
2161 .parent = &func_12m_ck,
2162 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2163 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2164 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2165 .recalc = &followparent_recalc,
2168 static struct clk i2c2_ick = {
2172 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2173 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2174 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2175 .recalc = &followparent_recalc,
2178 static struct clk i2c2_fck = {
2181 .parent = &func_12m_ck,
2182 .flags = CLOCK_IN_OMAP242X,
2183 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2184 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2185 .recalc = &followparent_recalc,
2188 static struct clk i2chs2_fck = {
2189 .name = "i2chs_fck",
2191 .parent = &func_96m_ck,
2192 .flags = CLOCK_IN_OMAP243X,
2193 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2194 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2195 .recalc = &followparent_recalc,
2198 static struct clk i2c1_ick = {
2202 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2203 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2204 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2205 .recalc = &followparent_recalc,
2208 static struct clk i2c1_fck = {
2211 .parent = &func_12m_ck,
2212 .flags = CLOCK_IN_OMAP242X,
2213 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2214 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2215 .recalc = &followparent_recalc,
2218 static struct clk i2chs1_fck = {
2219 .name = "i2chs_fck",
2221 .parent = &func_96m_ck,
2222 .flags = CLOCK_IN_OMAP243X,
2223 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2224 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2225 .recalc = &followparent_recalc,
2228 static struct clk gpmc_fck = {
2230 .parent = &core_l3_ck,
2231 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2232 .recalc = &followparent_recalc,
2235 static struct clk sdma_fck = {
2237 .parent = &core_l3_ck,
2238 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2239 .recalc = &followparent_recalc,
2242 static struct clk sdma_ick = {
2245 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2246 .recalc = &followparent_recalc,
2249 static struct clk vlynq_ick = {
2250 .name = "vlynq_ick",
2251 .parent = &core_l3_ck,
2252 .flags = CLOCK_IN_OMAP242X,
2253 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2254 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2255 .recalc = &followparent_recalc,
2258 static const struct clksel_rate vlynq_fck_96m_rates[] = {
2259 { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
2263 static const struct clksel_rate vlynq_fck_core_rates[] = {
2264 { .div = 1, .val = 1, .flags = RATE_IN_242X },
2265 { .div = 2, .val = 2, .flags = RATE_IN_242X },
2266 { .div = 3, .val = 3, .flags = RATE_IN_242X },
2267 { .div = 4, .val = 4, .flags = RATE_IN_242X },
2268 { .div = 6, .val = 6, .flags = RATE_IN_242X },
2269 { .div = 8, .val = 8, .flags = RATE_IN_242X },
2270 { .div = 9, .val = 9, .flags = RATE_IN_242X },
2271 { .div = 12, .val = 12, .flags = RATE_IN_242X },
2272 { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
2273 { .div = 18, .val = 18, .flags = RATE_IN_242X },
2277 static const struct clksel vlynq_fck_clksel[] = {
2278 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
2279 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
2283 static struct clk vlynq_fck = {
2284 .name = "vlynq_fck",
2285 .parent = &func_96m_ck,
2286 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
2287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2288 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2289 .init = &omap2_init_clksel_parent,
2290 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
2291 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
2292 .clksel = vlynq_fck_clksel,
2293 .recalc = &omap2_clksel_recalc,
2294 .round_rate = &omap2_clksel_round_rate,
2295 .set_rate = &omap2_clksel_set_rate
2298 static struct clk sdrc_ick = {
2301 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2302 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
2303 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2304 .recalc = &followparent_recalc,
2307 static struct clk des_ick = {
2310 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2311 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2312 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2313 .recalc = &followparent_recalc,
2316 static struct clk sha_ick = {
2319 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2320 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2321 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2322 .recalc = &followparent_recalc,
2325 static struct clk rng_ick = {
2328 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2330 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2331 .recalc = &followparent_recalc,
2334 static struct clk aes_ick = {
2337 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2338 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2339 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2340 .recalc = &followparent_recalc,
2343 static struct clk pka_ick = {
2346 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2347 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2348 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2349 .recalc = &followparent_recalc,
2352 static struct clk usb_fck = {
2354 .parent = &func_48m_ck,
2355 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2356 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2357 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2358 .recalc = &followparent_recalc,
2361 static struct clk usbhs_ick = {
2362 .name = "usbhs_ick",
2363 .parent = &core_l3_ck,
2364 .flags = CLOCK_IN_OMAP243X,
2365 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2366 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2367 .recalc = &followparent_recalc,
2370 static struct clk mmchs1_ick = {
2371 .name = "mmchs1_ick",
2373 .flags = CLOCK_IN_OMAP243X,
2374 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2375 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2376 .recalc = &followparent_recalc,
2379 static struct clk mmchs1_fck = {
2380 .name = "mmchs1_fck",
2381 .parent = &func_96m_ck,
2382 .flags = CLOCK_IN_OMAP243X,
2383 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2384 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2385 .recalc = &followparent_recalc,
2388 static struct clk mmchs2_ick = {
2389 .name = "mmchs2_ick",
2391 .flags = CLOCK_IN_OMAP243X,
2392 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2393 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2394 .recalc = &followparent_recalc,
2397 static struct clk mmchs2_fck = {
2398 .name = "mmchs2_fck",
2399 .parent = &func_96m_ck,
2400 .flags = CLOCK_IN_OMAP243X,
2401 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2402 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2403 .recalc = &followparent_recalc,
2406 static struct clk gpio5_ick = {
2407 .name = "gpio5_ick",
2409 .flags = CLOCK_IN_OMAP243X,
2410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2411 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2412 .recalc = &followparent_recalc,
2415 static struct clk gpio5_fck = {
2416 .name = "gpio5_fck",
2417 .parent = &func_32k_ck,
2418 .flags = CLOCK_IN_OMAP243X,
2419 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2420 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2421 .recalc = &followparent_recalc,
2424 static struct clk mdm_intc_ick = {
2425 .name = "mdm_intc_ick",
2427 .flags = CLOCK_IN_OMAP243X,
2428 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2429 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2430 .recalc = &followparent_recalc,
2433 static struct clk mmchsdb1_fck = {
2434 .name = "mmchsdb1_fck",
2435 .parent = &func_32k_ck,
2436 .flags = CLOCK_IN_OMAP243X,
2437 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2438 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2439 .recalc = &followparent_recalc,
2442 static struct clk mmchsdb2_fck = {
2443 .name = "mmchsdb2_fck",
2444 .parent = &func_32k_ck,
2445 .flags = CLOCK_IN_OMAP243X,
2446 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2447 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2448 .recalc = &followparent_recalc,
2452 * This clock is a composite clock which does entire set changes then
2453 * forces a rebalance. It keys on the MPU speed, but it really could
2454 * be any key speed part of a set in the rate table.
2456 * to really change a set, you need memory table sets which get changed
2457 * in sram, pre-notifiers & post notifiers, changing the top set, without
2458 * having low level display recalc's won't work... this is why dpm notifiers
2459 * work, isr's off, walk a list of clocks already _off_ and not messing with
2462 * This clock should have no parent. It embodies the entire upper level
2463 * active set. A parent will mess up some of the init also.
2465 static struct clk virt_prcm_set = {
2466 .name = "virt_prcm_set",
2467 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2468 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
2469 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2470 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2471 .set_rate = &omap2_select_table_rate,
2472 .round_rate = &omap2_round_to_table_rate,
2475 static struct clk *onchip_24xx_clks[] __initdata = {
2476 /* external root sources */
2481 /* internal analog sources */
2485 /* internal prcm root sources */
2497 /* mpu domain clocks */
2499 /* dsp domain clocks */
2500 &iva2_1_fck, /* 2430 */
2502 &dsp_ick, /* 2420 */
2506 /* GFX domain clocks */
2510 /* Modem domain clocks */
2513 /* DSS domain clocks */
2518 /* L3 domain clocks */
2522 /* L4 domain clocks */
2523 &l4_ck, /* used as both core_l4 and wu_l4 */
2525 /* virtual meta-group clock */
2527 /* general l4 interface ck, multi-parent functional clk */