arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  */
   9
  10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  11 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  12
  13 #include <asm/arch/control.h>
  14
  15 #include "clock.h"
  16 #include "cm.h"
  17 #include "cm_regbits_34xx.h"
  18 #include "prm.h"
  19 #include "prm_regbits_34xx.h"
  20
  21 static void omap3_dpll_recalc(struct clk *clk);
  22 static void omap3_clkoutx2_recalc(struct clk *clk);
  23
  24 /*
  25  * DPLL1 supplies clock to the MPU.
  26  * DPLL2 supplies clock to the IVA2.
  27  * DPLL3 supplies CORE domain clocks.
  28  * DPLL4 supplies peripheral clocks.
  29  */
  30
  31 /* PRM CLOCKS */
  32
  33 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  34 static struct clk omap_32k_fck = {
  35         .name           = "omap_32k_fck",
  36         .rate           = 32768,
  37         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  38                                 ALWAYS_ENABLED,
  39         .recalc         = &propagate_rate,
  40 };
  41
  42 static struct clk secure_32k_fck = {
  43         .name           = "secure_32k_fck",
  44         .rate           = 32768,
  45         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  46                                 ALWAYS_ENABLED,
  47         .recalc         = &propagate_rate,
  48 };
  49
  50 /* Virtual source clocks for osc_sys_ck */
  51 static struct clk virt_12m_ck = {
  52         .name           = "virt_12m_ck",
  53         .rate           = 12000000,
  54         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  55                                 ALWAYS_ENABLED,
  56         .recalc         = &propagate_rate,
  57 };
  58
  59 static struct clk virt_13m_ck = {
  60         .name           = "virt_13m_ck",
  61         .rate           = 13000000,
  62         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  63                                 ALWAYS_ENABLED,
  64         .recalc         = &propagate_rate,
  65 };
  66
  67 static struct clk virt_16_8m_ck = {
  68         .name           = "virt_16_8m_ck",
  69         .rate           = 16800000,
  70         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
  71                                 ALWAYS_ENABLED,
  72         .recalc         = &propagate_rate,
  73 };
  74
  75 static struct clk virt_19_2m_ck = {
  76         .name           = "virt_19_2m_ck",
  77         .rate           = 19200000,
  78         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  79                                 ALWAYS_ENABLED,
  80         .recalc         = &propagate_rate,
  81 };
  82
  83 static struct clk virt_26m_ck = {
  84         .name           = "virt_26m_ck",
  85         .rate           = 26000000,
  86         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  87                                 ALWAYS_ENABLED,
  88         .recalc         = &propagate_rate,
  89 };
  90
  91 static struct clk virt_38_4m_ck = {
  92         .name           = "virt_38_4m_ck",
  93         .rate           = 38400000,
  94         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  95                                 ALWAYS_ENABLED,
  96         .recalc         = &propagate_rate,
  97 };
  98
  99 static const struct clksel_rate osc_sys_12m_rates[] = {
 100         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 101         { .div = 0 }
 102 };
 103
 104 static const struct clksel_rate osc_sys_13m_rates[] = {
 105         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 106         { .div = 0 }
 107 };
 108
 109 /* 3430ES2 only */
 110 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 111         { .div = 1, .val = 5, .flags = RATE_IN_343X | DEFAULT_RATE },
 112         { .div = 0 }
 113 };
 114
 115 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 116         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 117         { .div = 0 }
 118 };
 119
 120 static const struct clksel_rate osc_sys_26m_rates[] = {
 121         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 122         { .div = 0 }
 123 };
 124
 125 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 126         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 127         { .div = 0 }
 128 };
 129
 130 static const struct clksel osc_sys_clksel[] = {
 131         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 132         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 133         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 134         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 135         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 136         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 137         { .parent = NULL },
 138 };
 139
 140 /* Oscillator clock */
 141 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 142 static struct clk osc_sys_ck = {
 143         .name           = "osc_sys_ck",
 144         .init           = &omap2_init_clksel_parent,
 145         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 146         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 147         .clksel         = osc_sys_clksel,
 148         /* REVISIT: deal with autoextclkmode? */
 149         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 150                                 ALWAYS_ENABLED,
 151         .recalc         = &omap2_clksel_recalc,
 152 };
 153
 154 static const struct clksel_rate div2_rates[] = {
 155         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 156         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 157         { .div = 0 }
 158 };
 159
 160 static const struct clksel sys_clksel[] = {
 161         { .parent = &osc_sys_ck, .rates = div2_rates },
 162         { .parent = NULL }
 163 };
 164
 165 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 166 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 167 static struct clk sys_ck = {
 168         .name           = "sys_ck",
 169         .parent         = &osc_sys_ck,
 170         .init           = &omap2_init_clksel_parent,
 171         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 172         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 173         .clksel         = sys_clksel,
 174         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 175         .recalc         = &omap2_clksel_recalc,
 176 };
 177
 178 static struct clk sys_altclk = {
 179         .name           = "sys_altclk",
 180         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 181         .recalc         = &propagate_rate,
 182 };
 183
 184 /* Optional external clock input for some McBSPs */
 185 static struct clk mcbsp_clks = {
 186         .name           = "mcbsp_clks",
 187         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 188         .recalc         = &propagate_rate,
 189 };
 190
 191 /* PRM EXTERNAL CLOCK OUTPUT */
 192
 193 static struct clk sys_clkout1 = {
 194         .name           = "sys_clkout1",
 195         .parent         = &osc_sys_ck,
 196         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 197         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 198         .flags          = CLOCK_IN_OMAP343X,
 199         .recalc         = &followparent_recalc,
 200 };
 201
 202 /* DPLLS */
 203
 204 /* CM CLOCKS */
 205
 206 /* DPLL1 */
 207 /* MPU clock source */
 208 /* Type: DPLL */
 209 static const struct dpll_data dpll1_dd = {
 210         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 211         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 212         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 213         .div2_reg       = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 214         .div2_mask      = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 215         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 216         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 217         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 218         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 219         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 220 };
 221
 222 static struct clk dpll1_ck = {
 223         .name           = "dpll1_ck",
 224         .parent         = &sys_ck,
 225         .dpll_data      = &dpll1_dd,
 226         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 227         .recalc         = &omap3_dpll_recalc,
 228 };
 229
 230 /*
 231  * REVISIT: This clock is never specifically defined in the 3430 TRM,
 232  * although it is referenced - so this is a guess
 233  */
 234 static struct clk emu_mpu_alwon_ck = {
 235         .name           = "emu_mpu_alwon_ck",
 236         .parent         = &dpll1_ck,
 237         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 238                                 PARENT_CONTROLS_CLOCK,
 239         .recalc         = &followparent_recalc,
 240 };
 241
 242 /* DPLL2 */
 243 /* IVA2 clock source */
 244 /* Type: DPLL */
 245
 246 static const struct dpll_data dpll2_dd = {
 247         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 248         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 249         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 250         .div2_reg       = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
 251         .div2_mask      = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 252         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 253         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 254         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 255         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 256         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 257 };
 258
 259 static struct clk dpll2_ck = {
 260         .name           = "dpll2_ck",
 261         .parent         = &sys_ck,
 262         .dpll_data      = &dpll2_dd,
 263         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 264         .recalc         = &omap3_dpll_recalc,
 265 };
 266
 267 /* DPLL3 */
 268 /* Source clock for all interfaces and for some device fclks */
 269 /* Type: DPLL */
 270 static const struct dpll_data dpll3_dd = {
 271         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 272         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 273         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 274         .div2_reg       = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 275         .div2_mask      = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 276         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 277         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 278         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 279         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 280         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 281 };
 282
 283 static struct clk dpll3_ck = {
 284         .name           = "dpll3_ck",
 285         .parent         = &sys_ck,
 286         .dpll_data      = &dpll3_dd,
 287         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 288         .recalc         = &omap3_dpll_recalc,
 289 };
 290
 291 static const struct clksel_rate div16_dpll_rates[] = {
 292         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 293         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 294         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 295         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 296         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 297         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 298         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 299         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 300         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 301         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 302         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 303         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 304         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 305         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 306         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 307         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 308         { .div = 0 }
 309 };
 310
 311 static const struct clksel div2_dpll3m2_clksel[] = {
 312         { .parent = &dpll3_ck, .rates = div2_rates },
 313         { .parent = NULL }
 314 };
 315
 316 /*
 317  * REVISIT: Not sure what to do about clksel & these M2 divider clocks.
 318  * Shouldn't they be changed in SRAM?
 319  * This should probably remain a 'read-only' clksel clock.
 320  */
 321 static struct clk dpll3_m2_ck = {
 322         .name           = "dpll3_m2_ck",
 323         .parent         = &dpll3_ck,
 324         .init           = &omap2_init_clksel_parent,
 325         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 326         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 327         .clksel         = div2_dpll3m2_clksel,
 328         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 329                                 PARENT_CONTROLS_CLOCK,
 330         .recalc         = &omap2_clksel_recalc,
 331 };
 332
 333 static struct clk core_ck = {
 334         .name           = "core_ck",
 335         .parent         = &dpll3_m2_ck,
 336         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 337                                 PARENT_CONTROLS_CLOCK,
 338         .recalc         = &followparent_recalc,
 339 };
 340
 341 /*
 342  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 343  * DPLL isn't bypassed
 344  */
 345 static struct clk dpll3_x2_ck = {
 346         .name           = "dpll3_x2_ck",
 347         .parent         = &core_ck,
 348         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 349                                 PARENT_CONTROLS_CLOCK,
 350         .recalc         = &omap3_clkoutx2_recalc,
 351 };
 352
 353 static struct clk dpll3_m2x2_ck = {
 354         .name           = "dpll3_m2x2_ck",
 355         .parent         = &dpll3_x2_ck,
 356         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 357                                 PARENT_CONTROLS_CLOCK,
 358         .recalc         = &followparent_recalc,
 359 };
 360
 361 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 362 static struct clk dpll3_m3x2_ck = {
 363         .name           = "dpll3_m3x2_ck",
 364         .parent         = &dpll3_x2_ck,
 365         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 366         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 367         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 368         .recalc         = &followparent_recalc,
 369 };
 370
 371 static const struct clksel div16_dpll3_clksel[] = {
 372         { .parent = &dpll3_x2_ck, .rates = div16_dpll_rates },
 373         { .parent = NULL }
 374 };
 375
 376 static struct clk emu_core_alwon_ck = {
 377         .name           = "emu_core_alwon_ck",
 378         .parent         = &dpll3_x2_ck,
 379         .init           = &omap2_init_clksel_parent,
 380         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 381         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 382         .clksel         = div16_dpll3_clksel,
 383         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 384         .recalc         = &followparent_recalc,
 385 };
 386
 387 /* DPLL4 */
 388 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 389 /* Type: DPLL */
 390 static const struct dpll_data dpll4_dd = {
 391         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 392         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 393         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 394         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 395         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 396         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 397         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 398         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 399 };
 400
 401 static struct clk dpll4_ck = {
 402         .name           = "dpll4_ck",
 403         .parent         = &sys_ck,
 404         .dpll_data      = &dpll4_dd,
 405         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 406         .recalc         = &omap3_dpll_recalc,
 407 };
 408
 409 /*
 410  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 411  * DPLL isn't bypassed
 412  */
 413 static struct clk dpll4_x2_ck = {
 414         .name           = "dpll4_x2_ck",
 415         .parent         = &dpll4_ck,
 416         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 417                                 PARENT_CONTROLS_CLOCK,
 418         .recalc         = &omap3_clkoutx2_recalc,
 419 };
 420
 421 static const struct clksel div16_dpll4_clksel[] = {
 422         { .parent = &dpll4_x2_ck, .rates = div16_dpll_rates },
 423         { .parent = NULL }
 424 };
 425
 426 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 427 static struct clk dpll4_m2x2_ck = {
 428         .name           = "dpll4_m2x2_ck",
 429         .parent         = &dpll4_x2_ck,
 430         .init           = &omap2_init_clksel_parent,
 431         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 432         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 433         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 434         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 435         .clksel         = div16_dpll4_clksel,
 436         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 437         .recalc         = &omap2_clksel_recalc,
 438 };
 439
 440 static struct clk omap_96m_alwon_fck = {
 441         .name           = "omap_96m_alwon_fck",
 442         .parent         = &dpll4_m2x2_ck,
 443         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 444                                  PARENT_CONTROLS_CLOCK,
 445         .recalc         = &followparent_recalc,
 446 };
 447
 448 static struct clk omap_96m_fck = {
 449         .name           = "omap_96m_fck",
 450         .parent         = &omap_96m_alwon_fck,
 451         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 452                                 PARENT_CONTROLS_CLOCK,
 453         .recalc         = &followparent_recalc,
 454 };
 455
 456 static struct clk cm_96m_fck = {
 457         .name           = "cm_96m_fck",
 458         .parent         = &dpll4_m2x2_ck,
 459         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 460                                 PARENT_CONTROLS_CLOCK,
 461         .recalc         = &followparent_recalc,
 462 };
 463
 464 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 465 static struct clk dpll4_m3x2_ck = {
 466         .name           = "dpll4_m3x2_ck",
 467         .parent         = &dpll4_x2_ck,
 468         .init           = &omap2_init_clksel_parent,
 469         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 470         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 471         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 472         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 473         .clksel         = div16_dpll4_clksel,
 474         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 475         .recalc         = &omap2_clksel_recalc,
 476 };
 477
 478 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 479         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 480         { .div = 0 }
 481 };
 482
 483 static const struct clksel_rate omap_54m_alt_rates[] = {
 484         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 485         { .div = 0 }
 486 };
 487
 488 static const struct clksel omap_54m_clksel[] = {
 489         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 490         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 491         { .parent = NULL }
 492 };
 493
 494 static struct clk omap_54m_fck = {
 495         .name           = "omap_54m_fck",
 496         .init           = &omap2_init_clksel_parent,
 497         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 498         .clksel_mask    = OMAP3430_SOURCE_54M,
 499         .clksel         = omap_54m_clksel,
 500         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 501                                 PARENT_CONTROLS_CLOCK,
 502         .recalc         = &omap2_clksel_recalc,
 503 };
 504
 505 static const struct clksel_rate omap_48m_96md2_rates[] = {
 506         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 507         { .div = 0 }
 508 };
 509
 510 static const struct clksel_rate omap_48m_alt_rates[] = {
 511         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 512         { .div = 0 }
 513 };
 514
 515 static const struct clksel omap_48m_clksel[] = {
 516         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 517         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 518         { .parent = NULL }
 519 };
 520
 521 static struct clk omap_48m_fck = {
 522         .name           = "omap_48m_fck",
 523         .init           = &omap2_init_clksel_parent,
 524         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 525         .clksel_mask    = OMAP3430_SOURCE_48M,
 526         .clksel         = omap_48m_clksel,
 527         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 528                                 PARENT_CONTROLS_CLOCK,
 529         .recalc         = &omap2_clksel_recalc,
 530 };
 531
 532 static struct clk omap_12m_fck = {
 533         .name           = "omap_12m_fck",
 534         .parent         = &omap_48m_fck,
 535         .fixed_div      = 4,
 536         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 537                                 PARENT_CONTROLS_CLOCK,
 538         .recalc         = &omap2_fixed_divisor_recalc,
 539 };
 540
 541 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 542 static struct clk dpll4_m4x2_ck = {
 543         .name           = "dpll4_m4x2_ck",
 544         .parent         = &dpll4_x2_ck,
 545         .init           = &omap2_init_clksel_parent,
 546         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 547         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 548         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 549         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 550         .clksel         = div16_dpll4_clksel,
 551         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 552         .recalc         = &omap2_clksel_recalc,
 553 };
 554
 555 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 556 static struct clk dpll4_m5x2_ck = {
 557         .name           = "dpll4_m5x2_ck",
 558         .parent         = &dpll4_x2_ck,
 559         .init           = &omap2_init_clksel_parent,
 560         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 561         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 562         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 563         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 564         .clksel         = div16_dpll4_clksel,
 565         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 566         .recalc         = &omap2_clksel_recalc,
 567 };
 568
 569 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 570 static struct clk dpll4_m6x2_ck = {
 571         .name           = "dpll4_m6x2_ck",
 572         .parent         = &dpll4_x2_ck,
 573         .init           = &omap2_init_clksel_parent,
 574         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 575         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 576         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 577         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 578         .clksel         = div16_dpll4_clksel,
 579         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 580         .recalc         = &omap2_clksel_recalc,
 581 };
 582
 583 static struct clk emu_per_alwon_ck = {
 584         .name           = "emu_per_alwon_ck",
 585         .parent         = &dpll4_m6x2_ck,
 586         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 587                                 PARENT_CONTROLS_CLOCK,
 588         .recalc         = &followparent_recalc,
 589 };
 590
 591
 592 /* CM EXTERNAL CLOCK OUTPUTS */
 593
 594 static const struct clksel_rate clkout2_src_core_rates[] = {
 595         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 596         { .div = 0 }
 597 };
 598
 599 static const struct clksel_rate clkout2_src_sys_rates[] = {
 600         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 601         { .div = 0 }
 602 };
 603
 604 static const struct clksel_rate clkout2_src_96m_rates[] = {
 605         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 606         { .div = 0 }
 607 };
 608
 609 static const struct clksel_rate clkout2_src_54m_rates[] = {
 610         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 611         { .div = 0 }
 612 };
 613
 614 static const struct clksel clkout2_src_clksel[] = {
 615         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 616         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 617         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 618         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 619         { .parent = NULL }
 620 };
 621
 622 static struct clk clkout2_src_ck = {
 623         .name           = "clkout2_src_ck",
 624         .init           = &omap2_init_clksel_parent,
 625         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 626         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 627         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 628         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 629         .clksel         = clkout2_src_clksel,
 630         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 631         .recalc         = &omap2_clksel_recalc,
 632 };
 633
 634 static const struct clksel_rate sys_clkout2_rates[] = {
 635         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 636         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 637         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 638         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 639         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 640         { .div = 0 },
 641 };
 642
 643 static const struct clksel sys_clkout2_clksel[] = {
 644         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 645         { .parent = NULL },
 646 };
 647
 648 static struct clk sys_clkout2 = {
 649         .name           = "sys_clkout2",
 650         .init           = &omap2_init_clksel_parent,
 651         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 652         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 653         .clksel         = sys_clkout2_clksel,
 654         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 655         .recalc         = &omap2_clksel_recalc,
 656 };
 657
 658 /* CM OUTPUT CLOCKS */
 659
 660 static struct clk corex2_fck = {
 661         .name           = "corex2_fck",
 662         .parent         = &dpll3_m2x2_ck,
 663         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 664                                 PARENT_CONTROLS_CLOCK,
 665         .recalc         = &followparent_recalc,
 666 };
 667
 668 /* DPLL power domain clock controls */
 669
 670 static const struct clksel div2_core_clksel[] = {
 671         { .parent = &core_ck, .rates = div2_rates },
 672         { .parent = NULL }
 673 };
 674
 675 /* TRM s. 4.7.7.4 lists the input for these two clocks as CORE_CK,
 676    but presuming that is an error, or at least an overgeneralization */
 677 /* REVISIT: Are these in DPLL power domain or CM power domain?  docs
 678    may be inconsistent here? */
 679 static struct clk dpll1_fck = {
 680         .name           = "dpll1_fck",
 681         .parent         = &core_ck,
 682         .init           = &omap2_init_clksel_parent,
 683         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 684         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
 685         .clksel         = div2_core_clksel,
 686         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 687                                 PARENT_CONTROLS_CLOCK,
 688         .recalc         = &omap2_clksel_recalc,
 689 };
 690
 691 static struct clk dpll2_fck = {
 692         .name           = "dpll2_fck",
 693         .parent         = &core_ck,
 694         .init           = &omap2_init_clksel_parent,
 695         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 696         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
 697         .clksel         = div2_core_clksel,
 698         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 699                                 PARENT_CONTROLS_CLOCK,
 700         .recalc         = &omap2_clksel_recalc,
 701 };
 702
 703 /* Common interface clocks */
 704
 705 static struct clk l3_ick = {
 706         .name           = "l3_ick",
 707         .parent         = &core_ck,
 708         .init           = &omap2_init_clksel_parent,
 709         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 710         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
 711         .clksel         = div2_core_clksel,
 712         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 713                                 PARENT_CONTROLS_CLOCK,
 714         .recalc         = &omap2_clksel_recalc,
 715 };
 716
 717 static const struct clksel div2_l3_clksel[] = {
 718         { .parent = &l3_ick, .rates = div2_rates },
 719         { .parent = NULL }
 720 };
 721
 722 static struct clk l4_ick = {
 723         .name           = "l4_ick",
 724         .parent         = &l3_ick,
 725         .init           = &omap2_init_clksel_parent,
 726         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 727         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
 728         .clksel         = div2_l3_clksel,
 729         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 730                                 PARENT_CONTROLS_CLOCK,
 731         .recalc         = &omap2_clksel_recalc,
 732
 733 };
 734
 735 static const struct clksel div2_l4_clksel[] = {
 736         { .parent = &l4_ick, .rates = div2_rates },
 737         { .parent = NULL }
 738 };
 739
 740 static struct clk rm_ick = {
 741         .name           = "rm_ick",
 742         .parent         = &l4_ick,
 743         .init           = &omap2_init_clksel_parent,
 744         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
 745         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
 746         .clksel         = div2_l4_clksel,
 747         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 748         .recalc         = &omap2_clksel_recalc,
 749 };
 750
 751 /* GFX power domain */
 752
 753 /* GFX clocks are in 3430ES1 only.  3430ES2 and later uses the SGX instead */
 754
 755 static const struct clksel gfx_l3_clksel[] = {
 756         { .parent = &l3_ick, .rates = gfx_l3_rates },
 757         { .parent = NULL }
 758 };
 759
 760 static struct clk gfx_l3_fck = {
 761         .name           = "gfx_l3_fck",
 762         .parent         = &l3_ick,
 763         .init           = &omap2_init_clksel_parent,
 764         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 765         .enable_bit     = OMAP_EN_GFX_SHIFT,
 766         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 767         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 768         .clksel         = gfx_l3_clksel,
 769         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
 770         .recalc         = &omap2_clksel_recalc,
 771 };
 772
 773 static struct clk gfx_l3_ick = {
 774         .name           = "gfx_l3_ick",
 775         .parent         = &l3_ick,
 776         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 777         .enable_bit     = OMAP_EN_GFX_SHIFT,
 778         .flags          = CLOCK_IN_OMAP3430ES1,
 779         .recalc         = &followparent_recalc,
 780 };
 781
 782 static struct clk gfx_cg1_ck = {
 783         .name           = "gfx_cg1_ck",
 784         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
 785         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 786         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
 787         .flags          = CLOCK_IN_OMAP3430ES1,
 788         .recalc         = &followparent_recalc,
 789 };
 790
 791 static struct clk gfx_cg2_ck = {
 792         .name           = "gfx_cg2_ck",
 793         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
 794         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 795         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
 796         .flags          = CLOCK_IN_OMAP3430ES1,
 797         .recalc         = &followparent_recalc,
 798 };
 799
 800 /* CORE power domain */
 801
 802 static struct clk d2d_26m_fck = {
 803         .name           = "d2d_26m_fck",
 804         .parent         = &sys_ck,
 805         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 806         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
 807         .flags          = CLOCK_IN_OMAP3430ES1,
 808         .recalc         = &followparent_recalc,
 809 };
 810
 811 static const struct clksel omap343x_gpt_clksel[] = {
 812         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
 813         { .parent = &sys_ck,       .rates = gpt_sys_rates },
 814         { .parent = NULL}
 815 };
 816
 817 static struct clk gpt10_fck = {
 818         .name           = "gpt10_fck",
 819         .parent         = &sys_ck,
 820         .init           = &omap2_init_clksel_parent,
 821         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 822         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
 823         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 824         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
 825         .clksel         = omap343x_gpt_clksel,
 826         .flags          = CLOCK_IN_OMAP343X,
 827         .recalc         = &omap2_clksel_recalc,
 828 };
 829
 830 static struct clk gpt11_fck = {
 831         .name           = "gpt11_fck",
 832         .parent         = &sys_ck,
 833         .init           = &omap2_init_clksel_parent,
 834         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 835         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
 836         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 837         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
 838         .clksel         = omap343x_gpt_clksel,
 839         .flags          = CLOCK_IN_OMAP343X,
 840         .recalc         = &omap2_clksel_recalc,
 841 };
 842
 843 /* CORE 96M FCLK-derived clocks */
 844
 845 static struct clk core_96m_fck = {
 846         .name           = "core_96m_fck",
 847         .parent         = &omap_96m_fck,
 848         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 849                                 PARENT_CONTROLS_CLOCK,
 850         .recalc         = &followparent_recalc,
 851 };
 852
 853 static struct clk mmchs2_fck = {
 854         .name           = "mmchs_fck",
 855         .id             = 2,
 856         .parent         = &core_96m_fck,
 857         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 858         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
 859         .flags          = CLOCK_IN_OMAP343X,
 860         .recalc         = &followparent_recalc,
 861 };
 862
 863 static struct clk mspro_fck = {
 864         .name           = "mspro_fck",
 865         .parent         = &core_96m_fck,
 866         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 867         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
 868         .flags          = CLOCK_IN_OMAP343X,
 869         .recalc         = &followparent_recalc,
 870 };
 871
 872 static struct clk mmchs1_fck = {
 873         .name           = "mmchs_fck",
 874         .id             = 1,
 875         .parent         = &core_96m_fck,
 876         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 877         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
 878         .flags          = CLOCK_IN_OMAP343X,
 879         .recalc         = &followparent_recalc,
 880 };
 881
 882 static struct clk i2c3_fck = {
 883         .name           = "i2c_fck",
 884         .id             = 3,
 885         .parent         = &core_96m_fck,
 886         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 887         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
 888         .flags          = CLOCK_IN_OMAP343X,
 889         .recalc         = &followparent_recalc,
 890 };
 891
 892 static struct clk i2c2_fck = {
 893         .name           = "i2c_fck",
 894         .id             = 2,
 895         .parent         = &core_96m_fck,
 896         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 897         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
 898         .flags          = CLOCK_IN_OMAP343X,
 899         .recalc         = &followparent_recalc,
 900 };
 901
 902 static struct clk i2c1_fck = {
 903         .name           = "i2c_fck",
 904         .id             = 1,
 905         .parent         = &core_96m_fck,
 906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 907         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
 908         .flags          = CLOCK_IN_OMAP343X,
 909         .recalc         = &followparent_recalc,
 910 };
 911
 912 /*
 913  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
 914  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
 915  */
 916 static const struct clksel_rate common_mcbsp_96m_rates[] = {
 917         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 918         { .div = 0 }
 919 };
 920
 921 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
 922         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 923         { .div = 0 }
 924 };
 925
 926 static const struct clksel mcbsp_15_clksel[] = {
 927         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
 928         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
 929         { .parent = NULL }
 930 };
 931
 932 static struct clk mcbsp5_fck = {
 933         .name           = "mcbsp5_fck",
 934         .init           = &omap2_init_clksel_parent,
 935         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 936         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
 937         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
 938         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
 939         .clksel         = mcbsp_15_clksel,
 940         .flags          = CLOCK_IN_OMAP343X,
 941         .recalc         = &omap2_clksel_recalc,
 942 };
 943
 944 static struct clk mcbsp1_fck = {
 945         .name           = "mcbsp1_fck",
 946         .init           = &omap2_init_clksel_parent,
 947         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 948         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
 949         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
 950         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
 951         .clksel         = mcbsp_15_clksel,
 952         .flags          = CLOCK_IN_OMAP343X,
 953         .recalc         = &omap2_clksel_recalc,
 954 };
 955
 956 /* CORE_48M_FCK-derived clocks */
 957
 958 static struct clk core_48m_fck = {
 959         .name           = "core_48m_fck",
 960         .parent         = &omap_48m_fck,
 961         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 962                                 PARENT_CONTROLS_CLOCK,
 963         .recalc         = &followparent_recalc,
 964 };
 965
 966 static struct clk mcspi4_fck = {
 967         .name           = "mcspi4_fck",
 968         .parent         = &core_48m_fck,
 969         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 970         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
 971         .flags          = CLOCK_IN_OMAP343X,
 972         .recalc         = &followparent_recalc,
 973 };
 974
 975 static struct clk mcspi3_fck = {
 976         .name           = "mcspi3_fck",
 977         .parent         = &core_48m_fck,
 978         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 979         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
 980         .flags          = CLOCK_IN_OMAP343X,
 981         .recalc         = &followparent_recalc,
 982 };
 983
 984 static struct clk mcspi2_fck = {
 985         .name           = "mcspi2_fck",
 986         .parent         = &core_48m_fck,
 987         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 988         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
 989         .flags          = CLOCK_IN_OMAP343X,
 990         .recalc         = &followparent_recalc,
 991 };
 992
 993 static struct clk mcspi1_fck = {
 994         .name           = "mcspi1_fck",
 995         .parent         = &core_48m_fck,
 996         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 997         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
 998         .flags          = CLOCK_IN_OMAP343X,
 999         .recalc         = &followparent_recalc,
1000 };
1001
1002 static struct clk uart2_fck = {
1003         .name           = "uart2_fck",
1004         .parent         = &core_48m_fck,
1005         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1006         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1007         .flags          = CLOCK_IN_OMAP343X,
1008         .recalc         = &followparent_recalc,
1009 };
1010
1011 static struct clk uart1_fck = {
1012         .name           = "uart1_fck",
1013         .parent         = &core_48m_fck,
1014         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1015         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1016         .flags          = CLOCK_IN_OMAP343X,
1017         .recalc         = &followparent_recalc,
1018 };
1019
1020 static struct clk fshostusb_fck = {
1021         .name           = "fshostusb_fck",
1022         .parent         = &core_48m_fck,
1023         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1024         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1025         .flags          = CLOCK_IN_OMAP3430ES1,
1026         .recalc         = &followparent_recalc,
1027 };
1028
1029 /* CORE_12M_FCK based clocks */
1030
1031 static struct clk core_12m_fck = {
1032         .name           = "core_12m_fck",
1033         .parent         = &omap_12m_fck,
1034         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1035                                 PARENT_CONTROLS_CLOCK,
1036         .recalc         = &followparent_recalc,
1037 };
1038
1039 static struct clk hdq_fck = {
1040         .name           = "hdq_fck",
1041         .parent         = &core_12m_fck,
1042         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1043         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1044         .flags          = CLOCK_IN_OMAP343X,
1045         .recalc         = &followparent_recalc,
1046 };
1047
1048 /* DPLL3-derived clock */
1049
1050 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1051         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1052         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1053         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1054         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1055         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1056         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1057         { .div = 0 }
1058 };
1059
1060 static const struct clksel ssi_ssr_clksel[] = {
1061         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1062         { .parent = NULL }
1063 };
1064
1065 static struct clk ssi_ssr_fck = {
1066         .name           = "ssi_ssr_fck",
1067         .init           = &omap2_init_clksel_parent,
1068         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1069         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1070         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1071         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1072         .clksel         = ssi_ssr_clksel,
1073         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1074         .recalc         = &omap2_clksel_recalc,
1075 };
1076
1077 static struct clk ssi_sst_fck = {
1078         .name           = "ssi_sst_fck",
1079         .parent         = &ssi_ssr_fck,
1080         .fixed_div      = 2,
1081         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1082         .recalc         = &omap2_fixed_divisor_recalc,
1083 };
1084
1085
1086
1087 /* CORE_L3_ICK based clocks */
1088
1089 static struct clk core_l3_ick = {
1090         .name           = "core_l3_ick",
1091         .parent         = &l3_ick,
1092         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1093                                 PARENT_CONTROLS_CLOCK,
1094         .recalc         = &followparent_recalc,
1095 };
1096
1097 static struct clk hsotgusb_ick = {
1098         .name           = "hsotgusb_ick",
1099         .parent         = &core_l3_ick,
1100         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1101         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1102         .flags          = CLOCK_IN_OMAP343X,
1103         .recalc         = &followparent_recalc,
1104 };
1105
1106 static struct clk sdrc_ick = {
1107         .name           = "sdrc_ick",
1108         .parent         = &core_l3_ick,
1109         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1110         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1111         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1112         .recalc         = &followparent_recalc,
1113 };
1114
1115 static struct clk gpmc_fck = {
1116         .name           = "gpmc_fck",
1117         .parent         = &core_l3_ick,
1118         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1119         .recalc         = &followparent_recalc,
1120 };
1121
1122 /* SECURITY_L3_ICK based clocks */
1123
1124 static struct clk security_l3_ick = {
1125         .name           = "security_l3_ick",
1126         .parent         = &l3_ick,
1127         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1128                                 PARENT_CONTROLS_CLOCK,
1129         .recalc         = &followparent_recalc,
1130 };
1131
1132 static struct clk pka_ick = {
1133         .name           = "pka_ick",
1134         .parent         = &security_l3_ick,
1135         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1136         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1137         .flags          = CLOCK_IN_OMAP343X,
1138         .recalc         = &followparent_recalc,
1139 };
1140
1141 /* CORE_L4_ICK based clocks */
1142
1143 static struct clk core_l4_ick = {
1144         .name           = "core_l4_ick",
1145         .parent         = &l4_ick,
1146         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1147                                 PARENT_CONTROLS_CLOCK,
1148         .recalc         = &followparent_recalc,
1149 };
1150
1151 /* Intersystem Communication Registers - chassis mode only */
1152 static struct clk icr_ick = {
1153         .name           = "icr_ick",
1154         .parent         = &core_l4_ick,
1155         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1156         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1157         .flags          = CLOCK_IN_OMAP343X,
1158         .recalc         = &followparent_recalc,
1159 };
1160
1161 static struct clk aes2_ick = {
1162         .name           = "aes2_ick",
1163         .parent         = &core_l4_ick,
1164         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1165         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1166         .flags          = CLOCK_IN_OMAP343X,
1167         .recalc         = &followparent_recalc,
1168 };
1169
1170 static struct clk sha12_ick = {
1171         .name           = "sha12_ick",
1172         .parent         = &core_l4_ick,
1173         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1174         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1175         .flags          = CLOCK_IN_OMAP343X,
1176         .recalc         = &followparent_recalc,
1177 };
1178
1179 static struct clk des2_ick = {
1180         .name           = "des2_ick",
1181         .parent         = &core_l4_ick,
1182         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1183         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1184         .flags          = CLOCK_IN_OMAP343X,
1185         .recalc         = &followparent_recalc,
1186 };
1187
1188 static struct clk mmchs2_ick = {
1189         .name           = "mmchs_ick",
1190         .id             = 2,
1191         .parent         = &core_l4_ick,
1192         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1193         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1194         .flags          = CLOCK_IN_OMAP343X,
1195         .recalc         = &followparent_recalc,
1196 };
1197
1198 static struct clk mmchs1_ick = {
1199         .name           = "mmchs_ick",
1200         .id             = 1,
1201         .parent         = &core_l4_ick,
1202         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1203         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1204         .flags          = CLOCK_IN_OMAP343X,
1205         .recalc         = &followparent_recalc,
1206 };
1207
1208 static struct clk mspro_ick = {
1209         .name           = "mspro_ick",
1210         .parent         = &core_l4_ick,
1211         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1212         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1213         .flags          = CLOCK_IN_OMAP343X,
1214         .recalc         = &followparent_recalc,
1215 };
1216
1217 static struct clk hdq_ick = {
1218         .name           = "hdq_ick",
1219         .parent         = &core_l4_ick,
1220         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1221         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1222         .flags          = CLOCK_IN_OMAP343X,
1223         .recalc         = &followparent_recalc,
1224 };
1225
1226 static struct clk mcspi4_ick = {
1227         .name           = "mcspi4_ick",
1228         .parent         = &core_l4_ick,
1229         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1230         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1231         .flags          = CLOCK_IN_OMAP343X,
1232         .recalc         = &followparent_recalc,
1233 };
1234
1235 static struct clk mcspi3_ick = {
1236         .name           = "mcspi3_ick",
1237         .parent         = &core_l4_ick,
1238         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1239         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1240         .flags          = CLOCK_IN_OMAP343X,
1241         .recalc         = &followparent_recalc,
1242 };
1243
1244 static struct clk mcspi2_ick = {
1245         .name           = "mcspi2_ick",
1246         .parent         = &core_l4_ick,
1247         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1248         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1249         .flags          = CLOCK_IN_OMAP343X,
1250         .recalc         = &followparent_recalc,
1251 };
1252
1253 static struct clk mcspi1_ick = {
1254         .name           = "mcspi1_ick",
1255         .parent         = &core_l4_ick,
1256         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1257         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1258         .flags          = CLOCK_IN_OMAP343X,
1259         .recalc         = &followparent_recalc,
1260 };
1261
1262 static struct clk i2c3_ick = {
1263         .name           = "i2c_ick",
1264         .id             = 3,
1265         .parent         = &core_l4_ick,
1266         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1267         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1268         .flags          = CLOCK_IN_OMAP343X,
1269         .recalc         = &followparent_recalc,
1270 };
1271
1272 static struct clk i2c2_ick = {
1273         .name           = "i2c_ick",
1274         .id             = 2,
1275         .parent         = &core_l4_ick,
1276         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1277         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1278         .flags          = CLOCK_IN_OMAP343X,
1279         .recalc         = &followparent_recalc,
1280 };
1281
1282 static struct clk i2c1_ick = {
1283         .name           = "i2c_ick",
1284         .id             = 1,
1285         .parent         = &core_l4_ick,
1286         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1287         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1288         .flags          = CLOCK_IN_OMAP343X,
1289         .recalc         = &followparent_recalc,
1290 };
1291
1292 static struct clk uart2_ick = {
1293         .name           = "uart2_ick",
1294         .parent         = &core_l4_ick,
1295         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1296         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1297         .flags          = CLOCK_IN_OMAP343X,
1298         .recalc         = &followparent_recalc,
1299 };
1300
1301 static struct clk uart1_ick = {
1302         .name           = "uart1_ick",
1303         .parent         = &core_l4_ick,
1304         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1305         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1306         .flags          = CLOCK_IN_OMAP343X,
1307         .recalc         = &followparent_recalc,
1308 };
1309
1310 static struct clk gpt11_ick = {
1311         .name           = "gpt11_ick",
1312         .parent         = &core_l4_ick,
1313         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1314         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1315         .flags          = CLOCK_IN_OMAP343X,
1316         .recalc         = &followparent_recalc,
1317 };
1318
1319 static struct clk gpt10_ick = {
1320         .name           = "gpt10_ick",
1321         .parent         = &core_l4_ick,
1322         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1323         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1324         .flags          = CLOCK_IN_OMAP343X,
1325         .recalc         = &followparent_recalc,
1326 };
1327
1328 static struct clk mcbsp5_ick = {
1329         .name           = "mcbsp5_ick",
1330         .parent         = &core_l4_ick,
1331         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1332         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1333         .flags          = CLOCK_IN_OMAP343X,
1334         .recalc         = &followparent_recalc,
1335 };
1336
1337 static struct clk mcbsp1_ick = {
1338         .name           = "mcbsp1_ick",
1339         .parent         = &core_l4_ick,
1340         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1341         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1342         .flags          = CLOCK_IN_OMAP343X,
1343         .recalc         = &followparent_recalc,
1344 };
1345
1346 static struct clk fac_ick = {
1347         .name           = "fac_ick",
1348         .parent         = &core_l4_ick,
1349         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1350         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1351         .flags          = CLOCK_IN_OMAP3430ES1,
1352         .recalc         = &followparent_recalc,
1353 };
1354
1355 static struct clk mailboxes_ick = {
1356         .name           = "mailboxes_ick",
1357         .parent         = &core_l4_ick,
1358         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1359         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1360         .flags          = CLOCK_IN_OMAP343X,
1361         .recalc         = &followparent_recalc,
1362 };
1363
1364 static struct clk omapctrl_ick = {
1365         .name           = "omapctrl_ick",
1366         .parent         = &core_l4_ick,
1367         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1368         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1369         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1370         .recalc         = &followparent_recalc,
1371 };
1372
1373 /* SSI_L4_ICK based clocks */
1374
1375 static struct clk ssi_l4_ick = {
1376         .name           = "ssi_l4_ick",
1377         .parent         = &l4_ick,
1378         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1379         .recalc         = &followparent_recalc,
1380 };
1381
1382 static struct clk ssi_ick = {
1383         .name           = "ssi_ick",
1384         .parent         = &ssi_l4_ick,
1385         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1386         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1387         .flags          = CLOCK_IN_OMAP343X,
1388         .recalc         = &followparent_recalc,
1389 };
1390
1391 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1392  * but l4_ick makes more sense to me */
1393
1394 static const struct clksel usb_l4_clksel[] = {
1395         { .parent = &l4_ick, .rates = div2_rates },
1396         { .parent = NULL },
1397 };
1398
1399 static struct clk usb_l4_ick = {
1400         .name           = "usb_l4_ick",
1401         .parent         = &l4_ick,
1402         .init           = &omap2_init_clksel_parent,
1403         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1404         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1405         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1406         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1407         .clksel         = usb_l4_clksel,
1408         .flags          = CLOCK_IN_OMAP3430ES1,
1409         .recalc         = &omap2_clksel_recalc,
1410 };
1411
1412 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1413
1414 /* SECURITY_L4_ICK2 based clocks */
1415
1416 static struct clk security_l4_ick2 = {
1417         .name           = "security_l4_ick2",
1418         .parent         = &l4_ick,
1419         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1420                                 PARENT_CONTROLS_CLOCK,
1421         .recalc         = &followparent_recalc,
1422 };
1423
1424 static struct clk aes1_ick = {
1425         .name           = "aes1_ick",
1426         .parent         = &security_l4_ick2,
1427         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1428         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1429         .flags          = CLOCK_IN_OMAP343X,
1430         .recalc         = &followparent_recalc,
1431 };
1432
1433 static struct clk rng_ick = {
1434         .name           = "rng_ick",
1435         .parent         = &security_l4_ick2,
1436         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1437         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
1438         .flags          = CLOCK_IN_OMAP343X,
1439         .recalc         = &followparent_recalc,
1440 };
1441
1442 static struct clk sha11_ick = {
1443         .name           = "sha11_ick",
1444         .parent         = &security_l4_ick2,
1445         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1446         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
1447         .flags          = CLOCK_IN_OMAP343X,
1448         .recalc         = &followparent_recalc,
1449 };
1450
1451 static struct clk des1_ick = {
1452         .name           = "des1_ick",
1453         .parent         = &security_l4_ick2,
1454         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1455         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
1456         .flags          = CLOCK_IN_OMAP343X,
1457         .recalc         = &followparent_recalc,
1458 };
1459
1460 /* DSS */
1461
1462 static struct clk dss1_alwon_fck = {
1463         .name           = "dss1_alwon_fck",
1464         .parent         = &dpll4_m4x2_ck,
1465         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1466         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1467         .flags          = CLOCK_IN_OMAP343X,
1468         .recalc         = &followparent_recalc,
1469 };
1470
1471 static struct clk dss_tv_fck = {
1472         .name           = "dss_tv_fck",
1473         .parent         = &omap_54m_fck,
1474         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1475         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1476         .flags          = CLOCK_IN_OMAP343X,
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 static struct clk dss_96m_fck = {
1481         .name           = "dss_96m_fck",
1482         .parent         = &omap_96m_fck,
1483         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1484         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1485         .flags          = CLOCK_IN_OMAP343X,
1486         .recalc         = &followparent_recalc,
1487 };
1488
1489 static struct clk dss2_alwon_fck = {
1490         .name           = "dss2_alwon_fck",
1491         .parent         = &sys_ck,
1492         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1493         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
1494         .flags          = CLOCK_IN_OMAP343X,
1495         .recalc         = &followparent_recalc,
1496 };
1497
1498 static struct clk dss_ick = {
1499         /* Handles both L3 and L4 clocks */
1500         .name           = "dss_ick",
1501         .parent         = &l4_ick,
1502         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1503         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1504         .flags          = CLOCK_IN_OMAP343X,
1505         .recalc         = &followparent_recalc,
1506 };
1507
1508 /* CAM */
1509
1510 static struct clk cam_mclk = {
1511         .name           = "cam_mclk",
1512         .parent         = &dpll4_m5x2_ck,
1513         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1514         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1515         .flags          = CLOCK_IN_OMAP343X,
1516         .recalc         = &followparent_recalc,
1517 };
1518
1519 static struct clk cam_l3_ick = {
1520         .name           = "cam_l3_ick",
1521         .parent         = &l3_ick,
1522         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1523         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1524         .flags          = CLOCK_IN_OMAP343X,
1525         .recalc         = &followparent_recalc,
1526 };
1527
1528 static struct clk cam_l4_ick = {
1529         .name           = "cam_l4_ick",
1530         .parent         = &l4_ick,
1531         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
1532         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1533         .flags          = CLOCK_IN_OMAP343X,
1534         .recalc         = &followparent_recalc,
1535 };
1536
1537 /* WKUP */
1538
1539 static struct clk gpt1_fck = {
1540         .name           = "gpt1_fck",
1541         .init           = &omap2_init_clksel_parent,
1542         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1543         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1544         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1545         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
1546         .clksel         = omap343x_gpt_clksel,
1547         .flags          = CLOCK_IN_OMAP343X,
1548         .recalc         = &omap2_clksel_recalc,
1549 };
1550
1551 static struct clk wkup_32k_fck = {
1552         .name           = "wkup_32k_fck",
1553         .parent         = &omap_32k_fck,
1554         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
1555         .recalc         = &followparent_recalc,
1556 };
1557
1558 static struct clk gpio1_fck = {
1559         .name           = "gpio1_fck",
1560         .parent         = &wkup_32k_fck,
1561         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1562         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1563         .flags          = CLOCK_IN_OMAP343X,
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk wdt2_fck = {
1568         .name           = "wdt2_fck",
1569         .parent         = &wkup_32k_fck,
1570         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1571         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
1572         .flags          = CLOCK_IN_OMAP343X,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk wkup_l4_ick = {
1577         .name           = "wkup_l4_ick",
1578         .parent         = &sys_ck,
1579         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
1580         .recalc         = &followparent_recalc,
1581 };
1582
1583 static struct clk wdt2_ick = {
1584         .name           = "wdt2_ick",
1585         .parent         = &wkup_l4_ick,
1586         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1587         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
1588         .flags          = CLOCK_IN_OMAP343X,
1589         .recalc         = &followparent_recalc,
1590 };
1591
1592 static struct clk wdt1_ick = {
1593         .name           = "wdt1_ick",
1594         .parent         = &wkup_l4_ick,
1595         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1596         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
1597         .flags          = CLOCK_IN_OMAP343X,
1598         .recalc         = &followparent_recalc,
1599 };
1600
1601 static struct clk gpio1_ick = {
1602         .name           = "gpio1_ick",
1603         .parent         = &wkup_l4_ick,
1604         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1605         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1606         .flags          = CLOCK_IN_OMAP343X,
1607         .recalc         = &followparent_recalc,
1608 };
1609
1610 static struct clk omap_32ksync_ick = {
1611         .name           = "omap_32ksync_ick",
1612         .parent         = &wkup_l4_ick,
1613         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1614         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
1615         .flags          = CLOCK_IN_OMAP343X,
1616         .recalc         = &followparent_recalc,
1617 };
1618
1619 static struct clk gpt12_ick = {
1620         .name           = "gpt12_ick",
1621         .parent         = &wkup_l4_ick,
1622         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1623         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
1624         .flags          = CLOCK_IN_OMAP343X,
1625         .recalc         = &followparent_recalc,
1626 };
1627
1628 static struct clk gpt1_ick = {
1629         .name           = "gpt1_ick",
1630         .parent         = &wkup_l4_ick,
1631         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1632         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1633         .flags          = CLOCK_IN_OMAP343X,
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637
1638
1639 /* PER clock domain */
1640
1641 static struct clk per_96m_fck = {
1642         .name           = "per_96m_fck",
1643         .parent         = &omap_96m_alwon_fck,
1644         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1645                                 PARENT_CONTROLS_CLOCK,
1646         .recalc         = &followparent_recalc,
1647 };
1648
1649 static struct clk per_48m_fck = {
1650         .name           = "per_48m_fck",
1651         .parent         = &omap_48m_fck,
1652         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1653                                 PARENT_CONTROLS_CLOCK,
1654         .recalc         = &followparent_recalc,
1655 };
1656
1657 static struct clk uart3_fck = {
1658         .name           = "uart3_fck",
1659         .parent         = &per_48m_fck,
1660         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1661         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
1662         .flags          = CLOCK_IN_OMAP343X,
1663         .recalc         = &followparent_recalc,
1664 };
1665
1666 static struct clk gpt2_fck = {
1667         .name           = "gpt2_fck",
1668         .init           = &omap2_init_clksel_parent,
1669         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1670         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1671         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1672         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
1673         .clksel         = omap343x_gpt_clksel,
1674         .flags          = CLOCK_IN_OMAP343X,
1675         .recalc         = &omap2_clksel_recalc,
1676 };
1677
1678 static struct clk gpt3_fck = {
1679         .name           = "gpt3_fck",
1680         .init           = &omap2_init_clksel_parent,
1681         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1682         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1683         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1684         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
1685         .clksel         = omap343x_gpt_clksel,
1686         .flags          = CLOCK_IN_OMAP343X,
1687         .recalc         = &omap2_clksel_recalc,
1688 };
1689
1690 static struct clk gpt4_fck = {
1691         .name           = "gpt4_fck",
1692         .init           = &omap2_init_clksel_parent,
1693         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1694         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1695         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1696         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
1697         .clksel         = omap343x_gpt_clksel,
1698         .flags          = CLOCK_IN_OMAP343X,
1699         .recalc         = &omap2_clksel_recalc,
1700 };
1701
1702 static struct clk gpt5_fck = {
1703         .name           = "gpt5_fck",
1704         .init           = &omap2_init_clksel_parent,
1705         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1706         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1707         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1708         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
1709         .clksel         = omap343x_gpt_clksel,
1710         .flags          = CLOCK_IN_OMAP343X,
1711         .recalc         = &omap2_clksel_recalc,
1712 };
1713
1714 static struct clk gpt6_fck = {
1715         .name           = "gpt6_fck",
1716         .init           = &omap2_init_clksel_parent,
1717         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1718         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1719         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1720         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
1721         .clksel         = omap343x_gpt_clksel,
1722         .flags          = CLOCK_IN_OMAP343X,
1723         .recalc         = &omap2_clksel_recalc,
1724 };
1725
1726 static struct clk gpt7_fck = {
1727         .name           = "gpt7_fck",
1728         .init           = &omap2_init_clksel_parent,
1729         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1730         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1731         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1732         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
1733         .clksel         = omap343x_gpt_clksel,
1734         .flags          = CLOCK_IN_OMAP343X,
1735         .recalc         = &omap2_clksel_recalc,
1736 };
1737
1738 static struct clk gpt8_fck = {
1739         .name           = "gpt8_fck",
1740         .init           = &omap2_init_clksel_parent,
1741         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1742         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1743         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1744         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
1745         .clksel         = omap343x_gpt_clksel,
1746         .flags          = CLOCK_IN_OMAP343X,
1747         .recalc         = &omap2_clksel_recalc,
1748 };
1749
1750 static struct clk gpt9_fck = {
1751         .name           = "gpt9_fck",
1752         .init           = &omap2_init_clksel_parent,
1753         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1754         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1755         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1756         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
1757         .clksel         = omap343x_gpt_clksel,
1758         .flags          = CLOCK_IN_OMAP343X,
1759         .recalc         = &omap2_clksel_recalc,
1760 };
1761
1762 static struct clk per_32k_alwon_fck = {
1763         .name           = "per_32k_alwon_fck",
1764         .parent         = &omap_32k_fck,
1765         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
1766         .recalc         = &followparent_recalc,
1767 };
1768
1769 static struct clk gpio6_fck = {
1770         .name           = "gpio6_fck",
1771         .parent         = &per_32k_alwon_fck,
1772         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1773         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1774         .flags          = CLOCK_IN_OMAP343X,
1775         .recalc         = &followparent_recalc,
1776 };
1777
1778 static struct clk gpio5_fck = {
1779         .name           = "gpio5_fck",
1780         .parent         = &per_32k_alwon_fck,
1781         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1782         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1783         .flags          = CLOCK_IN_OMAP343X,
1784         .recalc         = &followparent_recalc,
1785 };
1786
1787 static struct clk gpio4_fck = {
1788         .name           = "gpio4_fck",
1789         .parent         = &per_32k_alwon_fck,
1790         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1791         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1792         .flags          = CLOCK_IN_OMAP343X,
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk gpio3_fck = {
1797         .name           = "gpio3_fck",
1798         .parent         = &per_32k_alwon_fck,
1799         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1800         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1801         .flags          = CLOCK_IN_OMAP343X,
1802         .recalc         = &followparent_recalc,
1803 };
1804
1805 static struct clk gpio2_fck = {
1806         .name           = "gpio2_fck",
1807         .parent         = &per_32k_alwon_fck,
1808         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1809         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1810         .flags          = CLOCK_IN_OMAP343X,
1811         .recalc         = &followparent_recalc,
1812 };
1813
1814 static struct clk wdt3_fck = {
1815         .name           = "wdt3_fck",
1816         .parent         = &per_32k_alwon_fck,
1817         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1818         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
1819         .flags          = CLOCK_IN_OMAP343X,
1820         .recalc         = &followparent_recalc,
1821 };
1822
1823 static struct clk per_l4_ick = {
1824         .name           = "per_l4_ick",
1825         .parent         = &l4_ick,
1826         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1827                                 PARENT_CONTROLS_CLOCK,
1828         .recalc         = &followparent_recalc,
1829 };
1830
1831 static struct clk gpio6_ick = {
1832         .name           = "gpio6_ick",
1833         .parent         = &per_l4_ick,
1834         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1835         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1836         .flags          = CLOCK_IN_OMAP343X,
1837         .recalc         = &followparent_recalc,
1838 };
1839
1840 static struct clk gpio5_ick = {
1841         .name           = "gpio5_ick",
1842         .parent         = &per_l4_ick,
1843         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1844         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1845         .flags          = CLOCK_IN_OMAP343X,
1846         .recalc         = &followparent_recalc,
1847 };
1848
1849 static struct clk gpio4_ick = {
1850         .name           = "gpio4_ick",
1851         .parent         = &per_l4_ick,
1852         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1853         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1854         .flags          = CLOCK_IN_OMAP343X,
1855         .recalc         = &followparent_recalc,
1856 };
1857
1858 static struct clk gpio3_ick = {
1859         .name           = "gpio3_ick",
1860         .parent         = &per_l4_ick,
1861         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1862         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1863         .flags          = CLOCK_IN_OMAP343X,
1864         .recalc         = &followparent_recalc,
1865 };
1866
1867 static struct clk gpio2_ick = {
1868         .name           = "gpio2_ick",
1869         .parent         = &per_l4_ick,
1870         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1871         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1872         .flags          = CLOCK_IN_OMAP343X,
1873         .recalc         = &followparent_recalc,
1874 };
1875
1876 static struct clk wdt3_ick = {
1877         .name           = "wdt3_ick",
1878         .parent         = &per_l4_ick,
1879         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1880         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
1881         .flags          = CLOCK_IN_OMAP343X,
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 static struct clk uart3_ick = {
1886         .name           = "uart3_ick",
1887         .parent         = &per_l4_ick,
1888         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1889         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
1890         .flags          = CLOCK_IN_OMAP343X,
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk gpt9_ick = {
1895         .name           = "gpt9_ick",
1896         .parent         = &per_l4_ick,
1897         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1898         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1899         .flags          = CLOCK_IN_OMAP343X,
1900         .recalc         = &followparent_recalc,
1901 };
1902
1903 static struct clk gpt8_ick = {
1904         .name           = "gpt8_ick",
1905         .parent         = &per_l4_ick,
1906         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1907         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1908         .flags          = CLOCK_IN_OMAP343X,
1909         .recalc         = &followparent_recalc,
1910 };
1911
1912 static struct clk gpt7_ick = {
1913         .name           = "gpt7_ick",
1914         .parent         = &per_l4_ick,
1915         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1916         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1917         .flags          = CLOCK_IN_OMAP343X,
1918         .recalc         = &followparent_recalc,
1919 };
1920
1921 static struct clk gpt6_ick = {
1922         .name           = "gpt6_ick",
1923         .parent         = &per_l4_ick,
1924         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1925         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1926         .flags          = CLOCK_IN_OMAP343X,
1927         .recalc         = &followparent_recalc,
1928 };
1929
1930 static struct clk gpt5_ick = {
1931         .name           = "gpt5_ick",
1932         .parent         = &per_l4_ick,
1933         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1934         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1935         .flags          = CLOCK_IN_OMAP343X,
1936         .recalc         = &followparent_recalc,
1937 };
1938
1939 static struct clk gpt4_ick = {
1940         .name           = "gpt4_ick",
1941         .parent         = &per_l4_ick,
1942         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1943         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1944         .flags          = CLOCK_IN_OMAP343X,
1945         .recalc         = &followparent_recalc,
1946 };
1947
1948 static struct clk gpt3_ick = {
1949         .name           = "gpt3_ick",
1950         .parent         = &per_l4_ick,
1951         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1952         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1953         .flags          = CLOCK_IN_OMAP343X,
1954         .recalc         = &followparent_recalc,
1955 };
1956
1957 static struct clk gpt2_ick = {
1958         .name           = "gpt2_ick",
1959         .parent         = &per_l4_ick,
1960         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1961         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1962         .flags          = CLOCK_IN_OMAP343X,
1963         .recalc         = &followparent_recalc,
1964 };
1965
1966 static struct clk mcbsp2_ick = {
1967         .name           = "mcbsp2_ick",
1968         .parent         = &per_l4_ick,
1969         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1970         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
1971         .flags          = CLOCK_IN_OMAP343X,
1972         .recalc         = &followparent_recalc,
1973 };
1974
1975 static struct clk mcbsp3_ick = {
1976         .name           = "mcbsp3_ick",
1977         .parent         = &per_l4_ick,
1978         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1979         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
1980         .flags          = CLOCK_IN_OMAP343X,
1981         .recalc         = &followparent_recalc,
1982 };
1983
1984 static struct clk mcbsp4_ick = {
1985         .name           = "mcbsp4_ick",
1986         .parent         = &per_l4_ick,
1987         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1988         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
1989         .flags          = CLOCK_IN_OMAP343X,
1990         .recalc         = &followparent_recalc,
1991 };
1992
1993 static const struct clksel mcbsp_234_clksel[] = {
1994         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
1995         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1996         { .parent = NULL }
1997 };
1998
1999 static struct clk mcbsp2_fck = {
2000         .name           = "mcbsp2_fck",
2001         .init           = &omap2_init_clksel_parent,
2002         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2003         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2004         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2005         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2006         .clksel         = mcbsp_234_clksel,
2007         .flags          = CLOCK_IN_OMAP343X,
2008         .recalc         = &omap2_clksel_recalc,
2009 };
2010
2011 static struct clk mcbsp3_fck = {
2012         .name           = "mcbsp3_fck",
2013         .init           = &omap2_init_clksel_parent,
2014         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2015         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2016         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2017         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2018         .clksel         = mcbsp_234_clksel,
2019         .flags          = CLOCK_IN_OMAP343X,
2020         .recalc         = &omap2_clksel_recalc,
2021 };
2022
2023 static struct clk mcbsp4_fck = {
2024         .name           = "mcbsp4_fck",
2025         .init           = &omap2_init_clksel_parent,
2026         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2027         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2028         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2029         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2030         .clksel         = mcbsp_234_clksel,
2031         .flags          = CLOCK_IN_OMAP343X,
2032         .recalc         = &omap2_clksel_recalc,
2033 };
2034
2035 /* EMU clocks */
2036
2037 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2038
2039 static const struct clksel_rate emu_src_sys_rates[] = {
2040         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2041         { .div = 0 },
2042 };
2043
2044 static const struct clksel_rate emu_src_core_rates[] = {
2045         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2046         { .div = 0 },
2047 };
2048
2049 static const struct clksel_rate emu_src_per_rates[] = {
2050         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2051         { .div = 0 },
2052 };
2053
2054 static const struct clksel_rate emu_src_mpu_rates[] = {
2055         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2056         { .div = 0 },
2057 };
2058
2059 static const struct clksel emu_src_clksel[] = {
2060         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2061         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2062         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2063         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2064         { .parent = NULL },
2065 };
2066
2067 /*
2068  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2069  * to switch the source of some of the EMU clocks.
2070  * XXX Are there CLKEN bits for these EMU clks?
2071  */
2072 static struct clk emu_src_ck = {
2073         .name           = "emu_src_ck",
2074         .init           = &omap2_init_clksel_parent,
2075         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2076         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2077         .clksel         = emu_src_clksel,
2078         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2079         .recalc         = &omap2_clksel_recalc,
2080 };
2081
2082 static const struct clksel_rate pclk_emu_rates[] = {
2083         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2084         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2085         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2086         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2087         { .div = 0 },
2088 };
2089
2090 static const struct clksel pclk_emu_clksel[] = {
2091         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2092         { .parent = NULL },
2093 };
2094
2095 static struct clk pclk_fck = {
2096         .name           = "pclk_fck",
2097         .init           = &omap2_init_clksel_parent,
2098         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2099         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2100         .clksel         = pclk_emu_clksel,
2101         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2102         .recalc         = &omap2_clksel_recalc,
2103 };
2104
2105 static const struct clksel_rate pclkx2_emu_rates[] = {
2106         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2107         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2108         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2109         { .div = 0 },
2110 };
2111
2112 static const struct clksel pclkx2_emu_clksel[] = {
2113         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2114         { .parent = NULL },
2115 };
2116
2117 static struct clk pclkx2_fck = {
2118         .name           = "pclkx2_fck",
2119         .init           = &omap2_init_clksel_parent,
2120         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2121         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2122         .clksel         = pclkx2_emu_clksel,
2123         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2124         .recalc         = &omap2_clksel_recalc,
2125 };
2126
2127 static const struct clksel atclk_emu_clksel[] = {
2128         { .parent = &emu_src_ck, .rates = div2_rates },
2129         { .parent = NULL },
2130 };
2131
2132 static struct clk atclk_fck = {
2133         .name           = "atclk_fck",
2134         .init           = &omap2_init_clksel_parent,
2135         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2136         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2137         .clksel         = atclk_emu_clksel,
2138         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2139         .recalc         = &omap2_clksel_recalc,
2140 };
2141
2142 static struct clk traceclk_src_fck = {
2143         .name           = "traceclk_src_fck",
2144         .init           = &omap2_init_clksel_parent,
2145         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2146         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2147         .clksel         = emu_src_clksel,
2148         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2149         .recalc         = &omap2_clksel_recalc,
2150 };
2151
2152 static const struct clksel_rate traceclk_rates[] = {
2153         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2154         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2155         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2156         { .div = 0 },
2157 };
2158
2159 static const struct clksel traceclk_clksel[] = {
2160         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2161         { .parent = NULL },
2162 };
2163
2164 static struct clk traceclk_fck = {
2165         .name           = "traceclk_fck",
2166         .init           = &omap2_init_clksel_parent,
2167         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2168         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2169         .clksel         = traceclk_clksel,
2170         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2171         .recalc         = &omap2_clksel_recalc,
2172 };
2173
2174 /* SR clocks */
2175
2176 /* SmartReflex fclk (VDD1) */
2177 static struct clk sr1_fck = {
2178         .name           = "sr1_fck",
2179         .parent         = &sys_ck,
2180         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2181         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2182         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2183         .recalc         = &followparent_recalc,
2184 };
2185
2186 /* SmartReflex fclk (VDD2) */
2187 static struct clk sr2_fck = {
2188         .name           = "sr2_fck",
2189         .parent         = &sys_ck,
2190         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2191         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2192         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2193         .recalc         = &followparent_recalc,
2194 };
2195
2196 static struct clk sr_l4_ick = {
2197         .name           = "sr_l4_ick",
2198         .parent         = &l4_ick,
2199         .flags          = CLOCK_IN_OMAP343X,
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 /* SECURE_32K_FCK clocks */
2204
2205 static struct clk gpt12_fck = {
2206         .name           = "gpt12_fck",
2207         .parent         = &secure_32k_fck,
2208         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2209         .recalc         = &followparent_recalc,
2210 };
2211
2212 static struct clk wdt1_fck = {
2213         .name           = "wdt1_fck",
2214         .parent         = &secure_32k_fck,
2215         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2216         .recalc         = &followparent_recalc,
2217 };
2218
2219
2220 static struct clk *onchip_34xx_clks[] __initdata = {
2221         &omap_32k_fck,
2222         &virt_12m_ck,
2223         &virt_13m_ck,
2224         &virt_16_8m_ck,
2225         &virt_19_2m_ck,
2226         &virt_26m_ck,
2227         &virt_38_4m_ck,
2228         &osc_sys_ck,
2229         &sys_ck,
2230         &sys_altclk,
2231         &sys_clkout1,
2232         &dpll1_ck,
2233         &emu_mpu_alwon_ck,
2234         &dpll2_ck,
2235         &dpll3_ck,
2236         &core_ck,
2237         &dpll3_x2_ck,
2238         &dpll3_m2_ck,
2239         &dpll3_m2x2_ck,
2240         &dpll3_m3x2_ck,
2241         &emu_core_alwon_ck,
2242         &dpll4_ck,
2243         &dpll4_x2_ck,
2244         &omap_96m_alwon_fck,
2245         &omap_96m_fck,
2246         &cm_96m_fck,
2247         &omap_54m_fck,
2248         &omap_48m_fck,
2249         &omap_12m_fck,
2250         &dpll4_m2x2_ck,
2251         &dpll4_m3x2_ck,
2252         &dpll4_m4x2_ck,
2253         &dpll4_m5x2_ck,
2254         &dpll4_m6x2_ck,
2255         &emu_per_alwon_ck,
2256         &clkout2_src_ck,
2257         &sys_clkout2,
2258         &corex2_fck,
2259         &dpll1_fck,
2260         &dpll2_fck,
2261         &l3_ick,
2262         &l4_ick,
2263         &rm_ick,
2264         &gfx_l3_fck,
2265         &gfx_l3_ick,
2266         &gfx_cg1_ck,
2267         &gfx_cg2_ck,
2268         &d2d_26m_fck,
2269         &gpt10_fck,
2270         &gpt11_fck,
2271         &core_96m_fck,
2272         &mmchs2_fck,
2273         &mspro_fck,
2274         &mmchs1_fck,
2275         &i2c3_fck,
2276         &i2c2_fck,
2277         &i2c1_fck,
2278         &mcbsp5_fck,
2279         &mcbsp1_fck,
2280         &core_48m_fck,
2281         &mcspi4_fck,
2282         &mcspi3_fck,
2283         &mcspi2_fck,
2284         &mcspi1_fck,
2285         &uart2_fck,
2286         &uart1_fck,
2287         &fshostusb_fck,
2288         &core_12m_fck,
2289         &hdq_fck,
2290         &ssi_ssr_fck,
2291         &ssi_sst_fck,
2292         &core_l3_ick,
2293         &hsotgusb_ick,
2294         &sdrc_ick,
2295         &gpmc_fck,
2296         &security_l3_ick,
2297         &pka_ick,
2298         &core_l4_ick,
2299         &icr_ick,
2300         &aes2_ick,
2301         &sha12_ick,
2302         &des2_ick,
2303         &mmchs2_ick,
2304         &mmchs1_ick,
2305         &mspro_ick,
2306         &hdq_ick,
2307         &mcspi4_ick,
2308         &mcspi3_ick,
2309         &mcspi2_ick,
2310         &mcspi1_ick,
2311         &i2c3_ick,
2312         &i2c2_ick,
2313         &i2c1_ick,
2314         &uart2_ick,
2315         &uart1_ick,
2316         &gpt11_ick,
2317         &gpt10_ick,
2318         &mcbsp5_ick,
2319         &mcbsp1_ick,
2320         &fac_ick,
2321         &mailboxes_ick,
2322         &omapctrl_ick,
2323         &ssi_l4_ick,
2324         &ssi_ick,
2325         &usb_l4_ick,
2326         &security_l4_ick2,
2327         &aes1_ick,
2328         &rng_ick,
2329         &sha11_ick,
2330         &des1_ick,
2331         &dss1_alwon_fck,
2332         &dss_tv_fck,
2333         &dss_96m_fck,
2334         &dss2_alwon_fck,
2335         &dss_ick,
2336         &cam_mclk,
2337         &cam_l3_ick,
2338         &cam_l4_ick,
2339         &gpt1_fck,
2340         &wkup_32k_fck,
2341         &gpio1_fck,
2342         &wdt2_fck,
2343         &wkup_l4_ick,
2344         &wdt2_ick,
2345         &wdt1_ick,
2346         &gpio1_ick,
2347         &omap_32ksync_ick,
2348         &gpt12_ick,
2349         &gpt1_ick,
2350         &per_96m_fck,
2351         &per_48m_fck,
2352         &uart3_fck,
2353         &gpt2_fck,
2354         &gpt3_fck,
2355         &gpt4_fck,
2356         &gpt5_fck,
2357         &gpt6_fck,
2358         &gpt7_fck,
2359         &gpt8_fck,
2360         &gpt9_fck,
2361         &per_32k_alwon_fck,
2362         &gpio6_fck,
2363         &gpio5_fck,
2364         &gpio4_fck,
2365         &gpio3_fck,
2366         &gpio2_fck,
2367         &wdt3_fck,
2368         &per_l4_ick,
2369         &gpio6_ick,
2370         &gpio5_ick,
2371         &gpio4_ick,
2372         &gpio3_ick,
2373         &gpio2_ick,
2374         &wdt3_ick,
2375         &uart3_ick,
2376         &gpt9_ick,
2377         &gpt8_ick,
2378         &gpt7_ick,
2379         &gpt6_ick,
2380         &gpt5_ick,
2381         &gpt4_ick,
2382         &gpt3_ick,
2383         &gpt2_ick,
2384         &mcbsp2_ick,
2385         &mcbsp3_ick,
2386         &mcbsp4_ick,
2387         &mcbsp2_fck,
2388         &mcbsp3_fck,
2389         &mcbsp4_fck,
2390         &emu_src_ck,
2391         &pclk_fck,
2392         &pclkx2_fck,
2393         &atclk_fck,
2394         &traceclk_src_fck,
2395         &traceclk_fck,
2396         &sr1_fck,
2397         &sr2_fck,
2398         &sr_l4_ick,
2399         &secure_32k_fck,
2400         &gpt12_fck,
2401         &wdt1_fck,
2402 };
2403
2404 #endif