4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008 Nokia Corporation
7 * Written by Paul Walmsley
10 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
11 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
13 #include <mach/clockdomain.h>
16 * OMAP2/3-common clockdomains
18 * Even though the 2420 has a single PRCM module from the
19 * interconnect's perspective, internally it does appear to have
20 * separate PRM and CM clockdomains. The usual test case is
21 * sys_clkout/sys_clkout2.
24 static struct clockdomain prm_clkdm = {
26 .pwrdm = { .name = "wkup_pwrdm" },
27 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
30 static struct clockdomain cm_clkdm = {
32 .pwrdm = { .name = "core_pwrdm" },
33 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
37 * virt_opp_clkdm is intended solely for use with virtual OPP clocks,
38 * e.g., virt_prcm_set, until OPP handling is rationalized.
40 static struct clockdomain virt_opp_clkdm = {
41 .name = "virt_opp_clkdm",
42 .pwrdm = { .name = "wkup_pwrdm" },
43 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
47 * 2420-only clockdomains
50 #if defined(CONFIG_ARCH_OMAP2420)
52 static struct clockdomain mpu_2420_clkdm = {
54 .pwrdm = { .name = "mpu_pwrdm" },
55 .flags = CLKDM_CAN_HWSUP,
56 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
57 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
60 static struct clockdomain iva1_2420_clkdm = {
62 .pwrdm = { .name = "dsp_pwrdm" },
63 .flags = CLKDM_CAN_HWSUP_SWSUP,
64 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
65 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
68 #endif /* CONFIG_ARCH_OMAP2420 */
72 * 2430-only clockdomains
75 #if defined(CONFIG_ARCH_OMAP2430)
77 static struct clockdomain mpu_2430_clkdm = {
79 .pwrdm = { .name = "mpu_pwrdm" },
80 .flags = CLKDM_CAN_HWSUP_SWSUP,
81 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
82 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
85 static struct clockdomain mdm_clkdm = {
87 .pwrdm = { .name = "mdm_pwrdm" },
88 .flags = CLKDM_CAN_HWSUP_SWSUP,
89 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
90 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
93 #endif /* CONFIG_ARCH_OMAP2430 */
97 * 24XX-only clockdomains
100 #if defined(CONFIG_ARCH_OMAP24XX)
102 static struct clockdomain dsp_clkdm = {
104 .pwrdm = { .name = "dsp_pwrdm" },
105 .flags = CLKDM_CAN_HWSUP_SWSUP,
106 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
107 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
110 static struct clockdomain gfx_24xx_clkdm = {
112 .pwrdm = { .name = "gfx_pwrdm" },
113 .flags = CLKDM_CAN_HWSUP_SWSUP,
114 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
115 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
118 static struct clockdomain core_l3_24xx_clkdm = {
119 .name = "core_l3_clkdm",
120 .pwrdm = { .name = "core_pwrdm" },
121 .flags = CLKDM_CAN_HWSUP,
122 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
123 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
126 static struct clockdomain core_l4_24xx_clkdm = {
127 .name = "core_l4_clkdm",
128 .pwrdm = { .name = "core_pwrdm" },
129 .flags = CLKDM_CAN_HWSUP,
130 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
131 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
134 static struct clockdomain dss_24xx_clkdm = {
136 .pwrdm = { .name = "core_pwrdm" },
137 .flags = CLKDM_CAN_HWSUP,
138 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
139 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
142 #endif /* CONFIG_ARCH_OMAP24XX */
149 #if defined(CONFIG_ARCH_OMAP34XX)
151 static struct clockdomain mpu_34xx_clkdm = {
153 .pwrdm = { .name = "mpu_pwrdm" },
154 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
155 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
156 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
159 static struct clockdomain neon_clkdm = {
160 .name = "neon_clkdm",
161 .pwrdm = { .name = "neon_pwrdm" },
162 .flags = CLKDM_CAN_HWSUP_SWSUP,
163 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
167 static struct clockdomain iva2_clkdm = {
168 .name = "iva2_clkdm",
169 .pwrdm = { .name = "iva2_pwrdm" },
170 .flags = CLKDM_CAN_HWSUP_SWSUP,
171 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
172 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
175 static struct clockdomain gfx_3430es1_clkdm = {
177 .pwrdm = { .name = "gfx_pwrdm" },
178 .flags = CLKDM_CAN_HWSUP_SWSUP,
179 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
180 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
183 static struct clockdomain sgx_clkdm = {
185 .pwrdm = { .name = "sgx_pwrdm" },
186 .flags = CLKDM_CAN_HWSUP_SWSUP,
187 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
188 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
192 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
193 * then that information was removed from the 34xx ES2+ TRM. It is
194 * unclear whether the core is still there, but the clockdomain logic
195 * is there, and must be programmed to an appropriate state if the
196 * CORE clockdomain is to become inactive.
198 static struct clockdomain d2d_clkdm = {
200 .pwrdm = { .name = "core_pwrdm" },
201 .flags = CLKDM_CAN_HWSUP,
202 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
203 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
206 static struct clockdomain core_l3_34xx_clkdm = {
207 .name = "core_l3_clkdm",
208 .pwrdm = { .name = "core_pwrdm" },
209 .flags = CLKDM_CAN_HWSUP,
210 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
211 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
214 static struct clockdomain core_l4_34xx_clkdm = {
215 .name = "core_l4_clkdm",
216 .pwrdm = { .name = "core_pwrdm" },
217 .flags = CLKDM_CAN_HWSUP,
218 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
219 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
222 static struct clockdomain dss_34xx_clkdm = {
224 .pwrdm = { .name = "dss_pwrdm" },
225 .flags = CLKDM_CAN_HWSUP_SWSUP,
226 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
227 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
230 static struct clockdomain cam_clkdm = {
232 .pwrdm = { .name = "cam_pwrdm" },
233 .flags = CLKDM_CAN_HWSUP_SWSUP,
234 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
235 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
238 static struct clockdomain usbhost_clkdm = {
239 .name = "usbhost_clkdm",
240 .pwrdm = { .name = "usbhost_pwrdm" },
241 .flags = CLKDM_CAN_HWSUP_SWSUP,
242 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
243 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
246 static struct clockdomain per_clkdm = {
248 .pwrdm = { .name = "per_pwrdm" },
249 .flags = CLKDM_CAN_HWSUP_SWSUP,
250 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
251 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
254 static struct clockdomain emu_clkdm = {
256 .pwrdm = { .name = "emu_pwrdm" },
257 .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
258 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
259 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
262 static struct clockdomain dpll1_clkdm = {
263 .name = "dpll1_clkdm",
264 .pwrdm = { .name = "dpll1_pwrdm" },
265 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
268 static struct clockdomain dpll2_clkdm = {
269 .name = "dpll2_clkdm",
270 .pwrdm = { .name = "dpll2_pwrdm" },
271 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
274 static struct clockdomain dpll3_clkdm = {
275 .name = "dpll3_clkdm",
276 .pwrdm = { .name = "dpll3_pwrdm" },
277 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
280 static struct clockdomain dpll4_clkdm = {
281 .name = "dpll4_clkdm",
282 .pwrdm = { .name = "dpll4_pwrdm" },
283 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
286 static struct clockdomain dpll5_clkdm = {
287 .name = "dpll5_clkdm",
288 .pwrdm = { .name = "dpll5_pwrdm" },
289 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
292 #endif /* CONFIG_ARCH_OMAP34XX */
295 * Clockdomain-powerdomain hwsup dependencies (34XX only)
298 static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
300 .pwrdm = { .name = "mpu_pwrdm" },
301 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
304 .pwrdm = { .name = "iva2_pwrdm" },
305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
308 .pwrdm = { .name = NULL },
316 static struct clockdomain *clockdomains_omap[] = {
322 #ifdef CONFIG_ARCH_OMAP2420
327 #ifdef CONFIG_ARCH_OMAP2430
332 #ifdef CONFIG_ARCH_OMAP24XX
340 #ifdef CONFIG_ARCH_OMAP34XX