2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
16 #include <linux/ioport.h>
17 #include <linux/spinlock.h>
20 #include <asm/mach-types.h>
21 #include <asm/arch/gpmc.h>
25 #define GPMC_BASE 0x6800a000
26 #define GPMC_REVISION 0x00
27 #define GPMC_SYSCONFIG 0x10
28 #define GPMC_SYSSTATUS 0x14
29 #define GPMC_IRQSTATUS 0x18
30 #define GPMC_IRQENABLE 0x1c
31 #define GPMC_TIMEOUT_CONTROL 0x40
32 #define GPMC_ERR_ADDRESS 0x44
33 #define GPMC_ERR_TYPE 0x48
34 #define GPMC_CONFIG 0x50
35 #define GPMC_STATUS 0x54
36 #define GPMC_PREFETCH_CONFIG1 0x1e0
37 #define GPMC_PREFETCH_CONFIG2 0x1e4
38 #define GPMC_PREFETCH_CONTROL 0x1e8
39 #define GPMC_PREFETCH_STATUS 0x1f0
40 #define GPMC_ECC_CONFIG 0x1f4
41 #define GPMC_ECC_CONTROL 0x1f8
42 #define GPMC_ECC_SIZE_CONFIG 0x1fc
45 #define GPMC_CS_SIZE 0x30
48 #define GPMC_MEM_START 0x00000000
49 #define GPMC_MEM_END 0x3FFFFFFF
50 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
52 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
53 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
55 static struct resource gpmc_mem_root;
56 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
57 static spinlock_t gpmc_mem_lock = SPIN_LOCK_UNLOCKED;
58 static unsigned gpmc_cs_map;
60 static void __iomem *gpmc_base =
61 (void __iomem *) IO_ADDRESS(GPMC_BASE);
62 static void __iomem *gpmc_cs_base =
63 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
65 static struct clk *gpmc_l3_clk;
67 static void gpmc_write_reg(int idx, u32 val)
69 __raw_writel(val, gpmc_base + idx);
72 static u32 gpmc_read_reg(int idx)
74 return __raw_readl(gpmc_base + idx);
77 void gpmc_cs_write_reg(int cs, int idx, u32 val)
79 void __iomem *reg_addr;
81 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
82 __raw_writel(val, reg_addr);
85 u32 gpmc_cs_read_reg(int cs, int idx)
87 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
90 /* TODO: Add support for gpmc_fck to clock framework and use it */
91 unsigned long gpmc_get_fclk_period(void)
94 return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
97 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
99 unsigned long tick_ps;
101 /* Calculate in picosecs to yield more exact results */
102 tick_ps = gpmc_get_fclk_period();
104 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
108 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
109 int time, const char *name)
111 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
116 int ticks, mask, nr_bits;
121 ticks = gpmc_ns_to_ticks(time);
122 nr_bits = end_bit - st_bit + 1;
123 if (ticks >= 1 << nr_bits) {
125 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
126 cs, name, time, ticks, 1 << nr_bits);
131 mask = (1 << nr_bits) - 1;
132 l = gpmc_cs_read_reg(cs, reg);
135 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
136 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
137 (l >> st_bit) & mask, time);
139 l &= ~(mask << st_bit);
140 l |= ticks << st_bit;
141 gpmc_cs_write_reg(cs, reg, l);
147 #define GPMC_SET_ONE(reg, st, end, field) \
148 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
149 t->field, #field) < 0) \
152 #define GPMC_SET_ONE(reg, st, end, field) \
153 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
157 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
162 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
163 div = l / gpmc_get_fclk_period();
172 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
177 div = gpmc_cs_calc_divider(cs, t->sync_clk);
181 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
182 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
183 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
185 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
186 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
187 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
189 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
190 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
191 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
192 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
194 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
195 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
196 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
198 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
200 /* caller is expected to have initialized CONFIG1 to cover
201 * at least sync vs async
203 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
204 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
206 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
207 cs, (div * gpmc_get_fclk_period()) / 1000, div);
211 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
217 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
222 mask = (1 << GPMC_SECTION_SHIFT) - size;
223 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
225 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
227 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
228 l |= 1 << 6; /* CSVALID */
229 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
232 static void gpmc_cs_disable_mem(int cs)
236 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
237 l &= ~(1 << 6); /* CSVALID */
238 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
241 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
246 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
247 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
248 mask = (l >> 8) & 0x0f;
249 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
252 static int gpmc_cs_mem_enabled(int cs)
256 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
260 static void gpmc_cs_set_reserved(int cs, int reserved)
262 gpmc_cs_map &= ~(1 << cs);
263 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
266 static int gpmc_cs_reserved(int cs)
268 return gpmc_cs_map & (1 << cs);
271 static unsigned long gpmc_mem_align(unsigned long size)
275 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
276 order = GPMC_CHUNK_SHIFT - 1;
285 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
287 struct resource *res = &gpmc_cs_mem[cs];
290 size = gpmc_mem_align(size);
291 spin_lock(&gpmc_mem_lock);
293 res->end = base + size - 1;
294 r = request_resource(&gpmc_mem_root, res);
295 spin_unlock(&gpmc_mem_lock);
300 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
302 struct resource *res = &gpmc_cs_mem[cs];
305 if (cs > GPMC_CS_NUM)
308 size = gpmc_mem_align(size);
309 if (size > (1 << GPMC_SECTION_SHIFT))
312 spin_lock(&gpmc_mem_lock);
313 if (gpmc_cs_reserved(cs)) {
317 if (gpmc_cs_mem_enabled(cs))
318 r = adjust_resource(res, res->start & ~(size - 1), size);
320 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
325 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
327 gpmc_cs_set_reserved(cs, 1);
329 spin_unlock(&gpmc_mem_lock);
333 void gpmc_cs_free(int cs)
335 spin_lock(&gpmc_mem_lock);
336 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
337 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
339 spin_unlock(&gpmc_mem_lock);
342 gpmc_cs_disable_mem(cs);
343 release_resource(&gpmc_cs_mem[cs]);
344 gpmc_cs_set_reserved(cs, 0);
345 spin_unlock(&gpmc_mem_lock);
348 void __init gpmc_mem_init(void)
351 unsigned long boot_rom_space = 0;
353 /* never allocate the first page, to facilitate bug detection;
354 * even if we didn't boot from ROM.
356 boot_rom_space = BOOT_ROM_SPACE;
357 /* In apollon the CS0 is mapped as 0x0000 0000 */
358 if (machine_is_omap_apollon())
360 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
361 gpmc_mem_root.end = GPMC_MEM_END;
363 /* Reserve all regions that has been set up by bootloader */
364 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
367 if (!gpmc_cs_mem_enabled(cs))
369 gpmc_cs_get_memconf(cs, &base, &size);
370 if (gpmc_cs_insert_mem(cs, base, size) < 0)
375 void __init gpmc_init(void)
379 gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
380 BUG_ON(IS_ERR(gpmc_l3_clk));
382 l = gpmc_read_reg(GPMC_REVISION);
383 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
384 /* Set smart idle mode and automatic L3 clock gating */
385 l = gpmc_read_reg(GPMC_SYSCONFIG);
387 l |= (0x02 << 3) | (1 << 0);
388 gpmc_write_reg(GPMC_SYSCONFIG, l);