2 * linux/arch/arm/mach-omap2/irq.c
4 * Interrupt handler for OMAP2 boards.
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <asm/hardware.h>
17 #include <asm/mach/irq.h>
21 #define INTC_REVISION 0x0000
22 #define INTC_SYSCONFIG 0x0010
23 #define INTC_SYSSTATUS 0x0014
24 #define INTC_CONTROL 0x0048
25 #define INTC_MIR_CLEAR0 0x0088
26 #define INTC_MIR_SET0 0x008c
29 * OMAP2 has a number of different interrupt controllers, each interrupt
30 * controller is identified as its own "bank". Register definitions are
31 * fairly consistent for each bank, but not all registers are implemented
32 * for each bank.. when in doubt, consult the TRM.
34 static struct omap_irq_bank {
35 unsigned long base_reg;
37 } __attribute__ ((aligned(4))) irq_banks[] = {
45 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
46 static void omap_ack_irq(unsigned int irq)
48 __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
51 static void omap_mask_irq(unsigned int irq)
53 int offset = (irq >> 5) << 5;
57 } else if (irq >= 32) {
61 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
64 static void omap_unmask_irq(unsigned int irq)
66 int offset = (irq >> 5) << 5;
70 } else if (irq >= 32) {
74 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
77 static void omap_mask_ack_irq(unsigned int irq)
83 static struct irq_chip omap_irq_chip = {
85 .ack = omap_mask_ack_irq,
86 .mask = omap_mask_irq,
87 .unmask = omap_unmask_irq,
90 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
94 tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
95 printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
96 "(revision %ld.%ld) with %d interrupts\n",
97 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
99 tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
100 tmp |= 1 << 1; /* soft reset */
101 __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
103 while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
104 /* Wait for reset to complete */;
106 /* Enable autoidle */
107 __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
110 void __init omap_init_irq(void)
112 unsigned long nr_irqs = 0;
113 unsigned int nr_banks = 0;
116 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
117 struct omap_irq_bank *bank = irq_banks + i;
119 if (cpu_is_omap24xx()) {
120 bank->base_reg = IO_ADDRESS(OMAP24XX_IC_BASE);
122 if (cpu_is_omap34xx()) {
123 bank->base_reg = IO_ADDRESS(OMAP34XX_IC_BASE);
125 omap_irq_bank_init_one(bank);
127 nr_irqs += bank->nr_irqs;
131 printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
132 nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
134 for (i = 0; i < nr_irqs; i++) {
135 set_irq_chip(i, &omap_irq_chip);
136 set_irq_handler(i, handle_level_irq);
137 set_irq_flags(i, IRQF_VALID);