2 * linux/arch/arm/mach-omap2/memory.c
4 * Memory timing related functions for OMAP24XX
6 * Copyright (C) 2005 Texas Instruments Inc.
7 * Richard Woodruff <r-woodruff2@ti.com>
9 * Copyright (C) 2005 Nokia Corporation
10 * Tony Lindgren <tony@atomide.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/sram.h>
30 #include "prcm-regs.h"
33 #define SMS_BASE 0x68008000
34 #define SMS_SYSCONFIG 0x010
36 #define SDRC_BASE 0x68009000
37 #define SDRC_SYSCONFIG 0x010
38 #define SDRC_SYSSTATUS 0x014
40 static const u32 sms_base = IO_ADDRESS(SMS_BASE);
41 static const u32 sdrc_base = IO_ADDRESS(SDRC_BASE);
44 static inline void sms_write_reg(int idx, u32 val)
46 __raw_writel(val, sms_base + idx);
49 static inline u32 sms_read_reg(int idx)
51 return __raw_readl(sms_base + idx);
54 static inline void sdrc_write_reg(int idx, u32 val)
56 __raw_writel(val, sdrc_base + idx);
59 static inline u32 sdrc_read_reg(int idx)
61 return __raw_readl(sdrc_base + idx);
65 static struct memory_timings mem_timings;
67 u32 omap2_memory_get_slow_dll_ctrl(void)
69 return mem_timings.slow_dll_ctrl;
72 u32 omap2_memory_get_fast_dll_ctrl(void)
74 return mem_timings.fast_dll_ctrl;
77 u32 omap2_memory_get_type(void)
79 return mem_timings.m_type;
82 void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
84 unsigned long dll_cnt;
87 mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
89 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
90 * In the case of 2422, its ok to use CS1 instead of CS0.
92 if (cpu_is_omap2422())
93 mem_timings.base_cs = 1;
95 mem_timings.base_cs = 0;
97 if (mem_timings.m_type != M_DDR)
100 /* With DDR we need to determine the low frequency DLL value */
101 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
102 mem_timings.dll_mode = M_UNLOCK;
104 mem_timings.dll_mode = M_LOCK;
106 if (mem_timings.base_cs == 0) {
107 fast_dll = SDRC_DLLA_CTRL;
108 dll_cnt = SDRC_DLLA_STATUS & 0xff00;
110 fast_dll = SDRC_DLLB_CTRL;
111 dll_cnt = SDRC_DLLB_STATUS & 0xff00;
113 if (force_lock_to_unlock_mode) {
115 fast_dll |= dll_cnt; /* Current lock mode */
117 /* set fast timings with DLL filter disabled */
118 mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
120 /* No disruptions, DDR will be offline & C-ABI not followed */
121 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
122 mem_timings.fast_dll_ctrl,
124 force_lock_to_unlock_mode);
125 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
127 /* Turn status into unlock ctrl */
128 mem_timings.slow_dll_ctrl |=
129 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
131 /* 90 degree phase for anything below 133Mhz + disable DLL filter */
132 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
135 void __init omap2_init_memory(void)
139 l = sms_read_reg(SMS_SYSCONFIG);
142 sms_write_reg(SMS_SYSCONFIG, l);
144 l = sdrc_read_reg(SDRC_SYSCONFIG);
147 sdrc_write_reg(SDRC_SYSCONFIG, l);