2 * linux/arch/arm/mach-omap2/pm.c
4 * OMAP2 Power Management Routines
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 * Copyright (C) 2006 Nokia Corporation
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * Amit Kucheria <amit.kucheria@nokia.com>
14 * Igor Stoppa <igor.stoppa@nokia.com>
16 * Based on pm.c for omap1
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
24 #include <linux/sched.h>
25 #include <linux/proc_fs.h>
26 #include <linux/interrupt.h>
27 #include <linux/sysfs.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
34 #include <asm/atomic.h>
35 #include <asm/mach/time.h>
36 #include <asm/mach/irq.h>
37 #include <asm/mach-types.h>
39 #include <asm/arch/irqs.h>
40 #include <asm/arch/clock.h>
41 #include <asm/arch/sram.h>
42 #include <asm/arch/pm.h>
43 #include <asm/arch/mux.h>
44 #include <asm/arch/dma.h>
45 #include <asm/arch/board.h>
46 #include <asm/arch/gpio.h>
49 #include "prm_regbits_24xx.h"
51 #include "cm_regbits_24xx.h"
54 static void (*omap2_sram_idle)(void);
55 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
56 static void (*saved_idle)(void);
58 static u32 omap2_read_32k_sync_counter(void)
60 return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
63 #ifdef CONFIG_PM_DEBUG
64 int omap2_pm_debug = 0;
66 static int serial_console_clock_disabled;
67 static int serial_console_uart;
68 static unsigned int serial_console_next_disable;
70 static struct clk *console_iclk, *console_fclk;
72 static void serial_console_kick(void)
74 serial_console_next_disable = omap2_read_32k_sync_counter();
75 /* Keep the clocks on for 4 secs */
76 serial_console_next_disable += 4 * 32768;
79 static void serial_wait_tx(void)
81 static const unsigned long uart_bases[3] = {
82 0x4806a000, 0x4806c000, 0x4806e000
84 unsigned long lsr_reg;
87 /* Wait for TX FIFO and THR to get empty */
88 lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
89 while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
92 serial_console_kick();
95 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
97 switch (serial_console_uart) {
110 static void serial_console_sleep(int enable)
112 if (console_iclk == NULL || console_fclk == NULL)
116 BUG_ON(serial_console_clock_disabled);
117 if (clk_get_usecount(console_fclk) == 0)
119 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
122 clk_disable(console_iclk);
123 clk_disable(console_fclk);
124 serial_console_clock_disabled = 1;
126 int serial_wakeup = 0;
129 switch (serial_console_uart) {
131 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
132 if (l & OMAP24XX_ST_UART1)
136 l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
137 if (l & OMAP24XX_ST_UART2)
141 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
142 if (l & OMAP24XX_ST_UART3)
147 serial_console_kick();
148 if (!serial_console_clock_disabled)
150 clk_enable(console_iclk);
151 clk_enable(console_fclk);
152 serial_console_clock_disabled = 0;
156 static void pm_init_serial_console(void)
158 const struct omap_serial_console_config *conf;
162 conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
163 struct omap_serial_console_config);
166 if (conf->console_uart > 3 || conf->console_uart < 1)
168 serial_console_uart = conf->console_uart;
169 sprintf(name, "uart%d_fck", conf->console_uart);
170 console_fclk = clk_get(NULL, name);
171 if (IS_ERR(console_fclk))
174 console_iclk = clk_get(NULL, name);
175 if (IS_ERR(console_fclk))
177 if (console_fclk == NULL || console_iclk == NULL) {
178 serial_console_uart = 0;
181 switch (serial_console_uart) {
183 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
184 l |= OMAP24XX_ST_UART1;
185 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
188 l = prm_read_mod_reg(CORE_MOD, PM_WKEN1);
189 l |= OMAP24XX_ST_UART2;
190 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
193 l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKEN2);
194 l |= OMAP24XX_ST_UART3;
195 prm_write_mod_reg(l, CORE_MOD, OMAP24XX_PM_WKEN2);
200 #define DUMP_PRM_MOD_REG(mod, reg) \
201 regs[reg_count].name = #mod "." #reg; \
202 regs[reg_count++].val = prm_read_mod_reg(mod, reg)
203 #define DUMP_CM_MOD_REG(mod, reg) \
204 regs[reg_count].name = #mod "." #reg; \
205 regs[reg_count++].val = cm_read_mod_reg(mod, reg)
206 #define DUMP_PRM_REG(reg) \
207 regs[reg_count].name = #reg; \
208 regs[reg_count++].val = prm_read_reg(reg)
209 #define DUMP_CM_REG(reg) \
210 regs[reg_count].name = #reg; \
211 regs[reg_count++].val = cm_read_reg(reg)
212 #define DUMP_INTC_REG(reg, off) \
213 regs[reg_count].name = #reg; \
214 regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
216 static void omap2_pm_dump(int mode, int resume, unsigned int us)
222 int reg_count = 0, i;
223 const char *s1 = NULL, *s2 = NULL;
228 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
229 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
230 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
231 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
232 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
236 DUMP_INTC_REG(INTC_MIR0, 0x0084);
237 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
238 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
241 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
242 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN2);
243 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
244 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
245 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
246 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
247 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN_PLL);
248 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
249 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
250 DUMP_PRM_MOD_REG(CORE_REG, PM_PWSTST);
251 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
255 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
256 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
257 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
258 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
259 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
260 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
261 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
262 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
263 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
264 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
267 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
268 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
269 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
270 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
272 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
273 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
274 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
294 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
295 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
296 jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
299 printk("--- Going to %s %s\n", s1, s2);
302 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
303 for (i = 0; i < reg_count; i++)
304 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
308 static inline void serial_console_sleep(int enable) {}
309 static inline void pm_init_serial_console(void) {}
310 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
311 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
313 #define omap2_pm_debug 0
317 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
319 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
321 return sprintf(buf, "%hu\n", enable_dyn_sleep);
324 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
328 unsigned short value;
329 if (sscanf(buf, "%hu", &value) != 1 ||
330 (value != 0 && value != 1)) {
331 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
334 enable_dyn_sleep = value;
338 static struct subsys_attribute sleep_while_idle_attr = {
340 .name = __stringify(sleep_while_idle),
343 .show = omap_pm_sleep_while_idle_show,
344 .store = omap_pm_sleep_while_idle_store,
347 static struct clk *osc_ck, *emul_ck;
349 #define CONTROL_DEVCONF __REG32(0x48000274)
351 static int omap2_fclks_active(void)
355 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
356 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
357 serial_console_fclk_mask(&f1, &f2);
363 static int omap2_irq_pending(void)
365 u32 pending_reg = IO_ADDRESS(0x480fe098);
368 for (i = 0; i < 4; i++) {
369 if (__raw_readl(pending_reg))
376 static atomic_t sleep_block = ATOMIC_INIT(0);
378 void omap2_block_sleep(void)
380 atomic_inc(&sleep_block);
383 void omap2_allow_sleep(void)
387 i = atomic_dec_return(&sleep_block);
391 static void omap2_enter_full_retention(void)
395 /* There is 1 reference hold for all children of the oscillator
396 * clock, the following will remove it. If no one else uses the
397 * oscillator itself it will be disabled if/when we enter retention
402 /* Clear old wake-up events */
403 /* REVISIT: These write to reserved bits? */
404 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
405 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
406 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
408 /* Try to enter retention */
409 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
410 MPU_MOD, PM_PWSTCTRL);
412 /* Workaround to kill USB */
413 CONTROL_DEVCONF |= 0x00008000;
415 omap2_gpio_prepare_for_retention();
417 if (omap2_pm_debug) {
418 omap2_pm_dump(0, 0, 0);
419 sleep_time = omap2_read_32k_sync_counter();
422 /* One last check for pending IRQs to avoid extra latency due
423 * to sleeping unnecessarily. */
424 if (omap2_irq_pending())
427 serial_console_sleep(1);
428 /* Jump to SRAM suspend code */
429 omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
431 serial_console_sleep(0);
433 if (omap2_pm_debug) {
434 unsigned long long tmp;
437 resume_time = omap2_read_32k_sync_counter();
438 tmp = resume_time - sleep_time;
440 omap2_pm_dump(0, 1, tmp / 32768);
442 omap2_gpio_resume_after_retention();
448 static int omap2_i2c_active(void)
452 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
453 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
456 static int sti_console_enabled;
458 static int omap2_allow_mpu_retention(void)
462 if (atomic_read(&sleep_block))
465 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
466 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
467 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
468 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
469 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
471 /* Check for UART3. */
472 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
473 if (l & OMAP24XX_EN_UART3)
475 if (sti_console_enabled)
481 static void omap2_enter_mpu_retention(void)
486 /* Putting MPU into the WFI state while a transfer is active
487 * seems to cause the I2C block to timeout. Why? Good question. */
488 if (omap2_i2c_active())
491 /* The peripherals seem not to be able to wake up the MPU when
492 * it is in retention mode. */
493 if (omap2_allow_mpu_retention()) {
494 /* REVISIT: These write to reserved bits? */
495 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
496 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
497 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
499 /* Try to enter MPU retention */
500 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
502 MPU_MOD, PM_PWSTCTRL);
504 /* Block MPU retention */
506 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
510 if (omap2_pm_debug) {
511 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
512 sleep_time = omap2_read_32k_sync_counter();
517 if (omap2_pm_debug) {
518 unsigned long long tmp;
521 resume_time = omap2_read_32k_sync_counter();
522 tmp = resume_time - sleep_time;
524 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
528 static int omap2_can_sleep(void)
530 if (!enable_dyn_sleep)
532 if (omap2_fclks_active())
534 if (atomic_read(&sleep_block) > 0)
536 if (clk_get_usecount(osc_ck) > 1)
538 if (omap_dma_running())
544 static void omap2_pm_idle(void)
549 if (!omap2_can_sleep()) {
550 /* timer_dyn_reprogram() takes about 100-200 us to complete.
551 * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
552 * transfer to complete), the increased latency is too much.
554 * omap2_block_sleep() and omap2_allow_sleep() can be used
557 if (atomic_read(&sleep_block) == 0) {
558 timer_dyn_reprogram();
559 if (omap2_irq_pending())
562 omap2_enter_mpu_retention();
567 * Since an interrupt may set up a timer, we don't want to
568 * reprogram the hardware timer with interrupts enabled.
569 * Re-enable interrupts only after returning from idle.
571 timer_dyn_reprogram();
573 if (omap2_irq_pending())
576 omap2_enter_full_retention();
583 static int omap2_pm_prepare(suspend_state_t state)
587 /* We cannot sleep in idle until we have resumed */
588 saved_idle = pm_idle;
592 case PM_SUSPEND_STANDBY:
602 static int omap2_pm_suspend(void)
606 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
607 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
610 mir1 = omap_readl(0x480fe0a4);
611 omap_writel(1 << 5, 0x480fe0ac);
613 omap2_enter_full_retention();
615 omap_writel(mir1, 0x480fe0a4);
616 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
621 static int omap2_pm_enter(suspend_state_t state)
626 case PM_SUSPEND_STANDBY:
628 ret = omap2_pm_suspend();
637 static int omap2_pm_finish(suspend_state_t state)
639 pm_idle = saved_idle;
643 static struct pm_ops omap_pm_ops = {
644 .prepare = omap2_pm_prepare,
645 .enter = omap2_pm_enter,
646 .finish = omap2_pm_finish,
647 .valid = pm_valid_only_mem,
650 static void __init prcm_setup_regs(void)
654 /* Enable autoidle */
655 prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
657 /* Set all domain wakeup dependencies */
658 prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
659 prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
660 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
662 l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
663 /* Enable retention for all memory blocks */
664 l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
665 OMAP24XX_MEM1RETSTATE;
667 /* Set power state to RETENTION */
668 l &= ~OMAP_POWERSTATE_MASK;
669 l |= 0x01 << OMAP_POWERSTATE_SHIFT;
670 prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
672 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
674 MPU_MOD, PM_PWSTCTRL);
676 /* Power down DSP and GFX */
677 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
678 OMAP24XX_DSP_MOD, PM_PWSTCTRL);
679 prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
680 GFX_MOD, PM_PWSTCTRL);
682 /* Enable clock auto control for all domains */
683 cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
684 cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
685 OMAP24XX_AUTOSTATE_L3,
686 CORE_MOD, CM_CLKSTCTRL);
687 cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
688 cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
689 OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
691 /* Enable clock autoidle for all domains */
692 cm_write_mod_reg(OMAP24XX_AUTO_CAM |
693 OMAP24XX_AUTO_MAILBOXES |
696 OMAP24XX_AUTO_MSPRO |
701 OMAP24XX_AUTO_UART2 |
702 OMAP24XX_AUTO_UART1 |
705 OMAP24XX_AUTO_MCSPI2 |
706 OMAP24XX_AUTO_MCSPI1 |
707 OMAP24XX_AUTO_MCBSP2 |
708 OMAP24XX_AUTO_MCBSP1 |
709 OMAP24XX_AUTO_GPT12 |
710 OMAP24XX_AUTO_GPT11 |
711 OMAP24XX_AUTO_GPT10 |
720 OMAP2420_AUTO_VLYNQ |
722 CORE_MOD, CM_AUTOIDLE1);
723 cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
726 CORE_MOD, CM_AUTOIDLE2);
727 cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
730 CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
731 cm_write_mod_reg(OMAP24XX_AUTO_PKA |
736 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
738 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
740 /* Put DPLL and both APLLs into autoidle mode */
741 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
742 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
743 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
744 PLL_MOD, CM_AUTOIDLE);
746 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
748 OMAP24XX_AUTO_MPU_WDT |
749 OMAP24XX_AUTO_GPIOS |
750 OMAP24XX_AUTO_32KSYNC |
752 WKUP_MOD, CM_AUTOIDLE);
754 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
756 prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
758 /* Configure automatic voltage transition */
759 prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
760 prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
761 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
762 OMAP24XX_MEMRETCTRL |
763 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
764 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
765 OMAP24XX_PRCM_VOLTCTRL);
767 /* Enable wake-up events */
768 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
772 int __init omap2_pm_init(void)
776 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
777 l = prm_read_reg(OMAP24XX_PRCM_REVISION);
778 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
780 osc_ck = clk_get(NULL, "osc_ck");
781 if (IS_ERR(osc_ck)) {
782 printk(KERN_ERR "could not get osc_ck\n");
786 if (cpu_is_omap242x()) {
787 emul_ck = clk_get(NULL, "emul_ck");
788 if (IS_ERR(emul_ck)) {
789 printk(KERN_ERR "could not get emul_ck\n");
797 pm_init_serial_console();
799 /* Hack to prevent MPU retention when STI console is enabled. */
801 const struct omap_sti_console_config *sti;
803 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
804 struct omap_sti_console_config);
805 if (sti != NULL && sti->enable)
806 sti_console_enabled = 1;
810 * We copy the assembler sleep/wakeup routines to SRAM.
811 * These routines need to be in SRAM as that's the only
812 * memory the MPU can see when it wakes up.
814 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
815 omap24xx_idle_loop_suspend_sz);
816 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
817 omap24xx_cpu_suspend_sz);
819 pm_set_ops(&omap_pm_ops);
820 pm_idle = omap2_pm_idle;
822 l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
824 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
829 late_initcall(omap2_pm_init);