arch/arm/mach-omap2/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/pm.c
   3  *
   4  * OMAP2 Power Management Routines
   5  *
   6  * Copyright (C) 2005 Texas Instruments, Inc.
   7  * Copyright (C) 2006 Nokia Corporation
   8  *
   9  * Written by:
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Tony Lindgren
  12  * Juha Yrjola
  13  * Amit Kucheria <amit.kucheria@nokia.com>
  14  * Igor Stoppa <igor.stoppa@nokia.com>
  15  *
  16  * Based on pm.c for omap1
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 #include <linux/pm.h>
  24 #include <linux/sched.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/sysfs.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/clk.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/atomic.h>
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <asm/arch/irqs.h>
  40 #include <asm/arch/clock.h>
  41 #include <asm/arch/sram.h>
  42 #include <asm/arch/pm.h>
  43 #include <asm/arch/mux.h>
  44 #include <asm/arch/dma.h>
  45 #include <asm/arch/board.h>
  46 #include <asm/arch/gpio.h>
  47
  48 #include "prm.h"
  49 #include "prm_regbits_24xx.h"
  50 #include "cm.h"
  51 #include "cm_regbits_24xx.h"
  52 #include "sdrc.h"
  53
  54 static void (*omap2_sram_idle)(void);
  55 static void (*omap2_sram_suspend)(void __iomem *dllctrl);
  56 static void (*saved_idle)(void);
  57
  58 static u32 omap2_read_32k_sync_counter(void)
  59 {
  60         return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
  61 }
  62
  63 #ifdef CONFIG_PM_DEBUG
  64 int omap2_pm_debug = 0;
  65
  66 static int serial_console_clock_disabled;
  67 static int serial_console_uart;
  68 static unsigned int serial_console_next_disable;
  69
  70 static struct clk *console_iclk, *console_fclk;
  71
  72 static void serial_console_kick(void)
  73 {
  74         serial_console_next_disable = omap2_read_32k_sync_counter();
  75         /* Keep the clocks on for 4 secs */
  76         serial_console_next_disable += 4 * 32768;
  77 }
  78
  79 static void serial_wait_tx(void)
  80 {
  81         static const unsigned long uart_bases[3] = {
  82                 0x4806a000, 0x4806c000, 0x4806e000
  83         };
  84         unsigned long lsr_reg;
  85         int looped = 0;
  86
  87         /* Wait for TX FIFO and THR to get empty */
  88         lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
  89         while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
  90                 looped = 1;
  91         if (looped)
  92                 serial_console_kick();
  93 }
  94
  95 static void serial_console_fclk_mask(u32 *f1, u32 *f2)
  96 {
  97         switch (serial_console_uart)  {
  98         case 1:
  99                 *f1 &= ~(1 << 21);
 100                 break;
 101         case 2:
 102                 *f1 &= ~(1 << 22);
 103                 break;
 104         case 3:
 105                 *f2 &= ~(1 << 2);
 106                 break;
 107         }
 108 }
 109
 110 static void serial_console_sleep(int enable)
 111 {
 112         if (console_iclk == NULL || console_fclk == NULL)
 113                 return;
 114
 115         if (enable) {
 116                 BUG_ON(serial_console_clock_disabled);
 117                 if (clk_get_usecount(console_fclk) == 0)
 118                         return;
 119                 if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
 120                         return;
 121                 serial_wait_tx();
 122                 clk_disable(console_iclk);
 123                 clk_disable(console_fclk);
 124                 serial_console_clock_disabled = 1;
 125         } else {
 126                 int serial_wakeup = 0;
 127                 u32 l;
 128
 129                 switch (serial_console_uart)  {
 130                 case 1:
 131                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 132                         if (l & OMAP24XX_ST_UART1)
 133                                 serial_wakeup = 1;
 134                         break;
 135                 case 2:
 136                         l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
 137                         if (l & OMAP24XX_ST_UART2)
 138                                 serial_wakeup = 1;
 139                         break;
 140                 case 3:
 141                         l = prm_read_mod_reg(CORE_MOD, PM_WKST2);
 142                         if (l & OMAP24XX_ST_UART3)
 143                                 serial_wakeup = 1;
 144                         break;
 145                 }
 146                 if (serial_wakeup)
 147                         serial_console_kick();
 148                 if (!serial_console_clock_disabled)
 149                         return;
 150                 clk_enable(console_iclk);
 151                 clk_enable(console_fclk);
 152                 serial_console_clock_disabled = 0;
 153         }
 154 }
 155
 156 static void pm_init_serial_console(void)
 157 {
 158         const struct omap_serial_console_config *conf;
 159         char name[16];
 160         u32 l;
 161
 162         conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
 163                                struct omap_serial_console_config);
 164         if (conf == NULL)
 165                 return;
 166         if (conf->console_uart > 3 || conf->console_uart < 1)
 167                 return;
 168         serial_console_uart = conf->console_uart;
 169         sprintf(name, "uart%d_fck", conf->console_uart);
 170         console_fclk = clk_get(NULL, name);
 171         if (IS_ERR(console_fclk))
 172                 console_fclk = NULL;
 173         name[6] = 'i';
 174         console_iclk = clk_get(NULL, name);
 175         if (IS_ERR(console_fclk))
 176                 console_iclk = NULL;
 177         if (console_fclk == NULL || console_iclk == NULL) {
 178                 serial_console_uart = 0;
 179                 return;
 180         }
 181         switch (serial_console_uart) {
 182         case 1:
 183                 l = prcm_read_mod_reg(CORE_MOD, PM_WKEN1);
 184                 l |= OMAP24XX_ST_UART1;
 185                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 186                 break;
 187         case 2:
 188                 l = prcm_read_mod_reg(CORE_MOD, PM_WKEN1);
 189                 l |= OMAP24XX_ST_UART2;
 190                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 191                 break;
 192         case 3:
 193                 l = prcm_read_mod_reg(CORE_MOD, PM_WKEN2);
 194                 l |= OMAP24XX_ST_UART3;
 195                 prm_write_mod_reg(l, CORE_MOD, PM_WKEN2);
 196                 break;
 197         }
 198 }
 199
 200 #define DUMP_PRM_MOD_REG(mod, reg)    \
 201         regs[reg_count].name = #mod "." #reg; \
 202         regs[reg_count++].val = prm_read_mod_reg(mod, reg)
 203 #define DUMP_CM_MOD_REG(mod, reg)     \
 204         regs[reg_count].name = #mod "." #reg; \
 205         regs[reg_count++].val = cm_read_mod_reg(mod, reg)
 206 #define DUMP_PRM_REG(reg) \
 207         regs[reg_count].name = #reg; \
 208         regs[reg_count++].val = prm_read_reg(reg)
 209 #define DUMP_CM_REG(reg) \
 210         regs[reg_count].name = #reg; \
 211         regs[reg_count++].val = cm_read_reg(reg)
 212 #define DUMP_INTC_REG(reg, off) \
 213         regs[reg_count].name = #reg; \
 214         regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
 215
 216 static void omap2_pm_dump(int mode, int resume, unsigned int us)
 217 {
 218         struct reg {
 219                 const char *name;
 220                 u32 val;
 221         } regs[32];
 222         int reg_count = 0, i;
 223         const char *s1 = NULL, *s2 = NULL;
 224
 225         if (!resume) {
 226 #if 0
 227                 /* MPU */
 228                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
 229                 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
 230                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
 231                 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
 232                 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
 233 #endif
 234 #if 0
 235                 /* INTC */
 236                 DUMP_INTC_REG(INTC_MIR0, 0x0084);
 237                 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
 238                 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 239 #endif
 240 #if 0
 241                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
 242                 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN2);
 243                 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
 244                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
 245                 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
 246                 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
 247                 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN_PLL);
 248                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
 249                 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
 250                 DUMP_PRM_MOD_REG(CORE_REG, PM_PWSTST);
 251                 DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
 252 #endif
 253 #if 0
 254                 /* DSP */
 255                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
 256                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
 257                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
 258                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 259                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
 260                 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 261                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
 262                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
 263                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 264                 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
 265 #endif
 266         } else {
 267                 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
 268                 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST2);
 269                 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
 270                 DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
 271 #if 1
 272                 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 273                 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
 274                 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
 275 #endif
 276         }
 277
 278         switch (mode) {
 279         case 0:
 280                 s1 = "full";
 281                 s2 = "retention";
 282                 break;
 283         case 1:
 284                 s1 = "MPU";
 285                 s2 = "retention";
 286                 break;
 287         case 2:
 288                 s1 = "MPU";
 289                 s2 = "idle";
 290                 break;
 291         }
 292
 293         if (!resume)
 294 #if defined(CONFIG_NO_IDLE_HZ) || defined(CONFIG_NO_HZ)
 295                 printk("--- Going to %s %s (next timer after %u ms)\n", s1, s2,
 296                        jiffies_to_msecs(next_timer_interrupt() - jiffies));
 297 #else
 298                 printk("--- Going to %s %s\n", s1, s2);
 299 #endif
 300         else
 301                 printk("--- Woke up (slept for %u.%03u ms)\n", us / 1000, us % 1000);
 302         for (i = 0; i < reg_count; i++)
 303                 printk("%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 304 }
 305
 306 #else
 307 static inline void serial_console_sleep(int enable) {}
 308 static inline void pm_init_serial_console(void) {}
 309 static inline void omap2_pm_dump(int mode, int resume, unsigned int us) {}
 310 static inline void serial_console_fclk_mask(u32 *f1, u32 *f2) {}
 311
 312 #define omap2_pm_debug 0
 313
 314 #endif
 315
 316 static unsigned short enable_dyn_sleep = 0; /* disabled till drivers are fixed */
 317
 318 static ssize_t omap_pm_sleep_while_idle_show(struct kset * subsys, char *buf)
 319 {
 320         return sprintf(buf, "%hu\n", enable_dyn_sleep);
 321 }
 322
 323 static ssize_t omap_pm_sleep_while_idle_store(struct kset * subsys,
 324                                               const char * buf,
 325                                               size_t n)
 326 {
 327         unsigned short value;
 328         if (sscanf(buf, "%hu", &value) != 1 ||
 329             (value != 0 && value != 1)) {
 330                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
 331                 return -EINVAL;
 332         }
 333         enable_dyn_sleep = value;
 334         return n;
 335 }
 336
 337 static struct subsys_attribute sleep_while_idle_attr = {
 338         .attr   = {
 339                 .name = __stringify(sleep_while_idle),
 340                 .mode = 0644,
 341         },
 342         .show   = omap_pm_sleep_while_idle_show,
 343         .store  = omap_pm_sleep_while_idle_store,
 344 };
 345
 346 static struct clk *osc_ck, *emul_ck;
 347
 348 #define CONTROL_DEVCONF         __REG32(0x48000274)
 349
 350 static int omap2_fclks_active(void)
 351 {
 352         u32 f1, f2;
 353
 354         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 355         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 356         serial_console_fclk_mask(&f1, &f2);
 357         if (f1 | f2)
 358                 return 1;
 359         return 0;
 360 }
 361
 362 static int omap2_irq_pending(void)
 363 {
 364         u32 pending_reg = IO_ADDRESS(0x480fe098);
 365         int i;
 366
 367         for (i = 0; i < 4; i++) {
 368                 if (__raw_readl(pending_reg))
 369                         return 1;
 370                 pending_reg += 0x20;
 371         }
 372         return 0;
 373 }
 374
 375 static atomic_t sleep_block = ATOMIC_INIT(0);
 376
 377 void omap2_block_sleep(void)
 378 {
 379         atomic_inc(&sleep_block);
 380 }
 381
 382 void omap2_allow_sleep(void)
 383 {
 384         int i;
 385
 386         i = atomic_dec_return(&sleep_block);
 387         BUG_ON(i < 0);
 388 }
 389
 390 static void omap2_enter_full_retention(void)
 391 {
 392         u32 sleep_time = 0;
 393
 394         /* There is 1 reference hold for all children of the oscillator
 395          * clock, the following will remove it. If no one else uses the
 396          * oscillator itself it will be disabled if/when we enter retention
 397          * mode.
 398          */
 399         clk_disable(osc_ck);
 400
 401         /* Clear old wake-up events */
 402         /* REVISIT: These write to reserved bits? */
 403         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 404         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 405         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 406
 407         /* Try to enter retention */
 408         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
 409                           MPU_MOD, PM_PWSTCTRL);
 410
 411         /* Workaround to kill USB */
 412         CONTROL_DEVCONF |= 0x00008000;
 413
 414         omap2_gpio_prepare_for_retention();
 415
 416         if (omap2_pm_debug) {
 417                 omap2_pm_dump(0, 0, 0);
 418                 sleep_time = omap2_read_32k_sync_counter();
 419         }
 420
 421         /* One last check for pending IRQs to avoid extra latency due
 422          * to sleeping unnecessarily. */
 423         if (omap2_irq_pending())
 424                 goto no_sleep;
 425
 426         serial_console_sleep(1);
 427         /* Jump to SRAM suspend code */
 428         omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 429 no_sleep:
 430         serial_console_sleep(0);
 431
 432         if (omap2_pm_debug) {
 433                 unsigned long long tmp;
 434                 u32 resume_time;
 435
 436                 resume_time = omap2_read_32k_sync_counter();
 437                 tmp = resume_time - sleep_time;
 438                 tmp *= 1000000;
 439                 omap2_pm_dump(0, 1, tmp / 32768);
 440         }
 441         omap2_gpio_resume_after_retention();
 442
 443         clk_enable(osc_ck);
 444
 445 }
 446
 447 static int omap2_i2c_active(void)
 448 {
 449         u32 l;
 450
 451         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 452         return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 453 }
 454
 455 static int sti_console_enabled;
 456
 457 static int omap2_allow_mpu_retention(void)
 458 {
 459         u32 l;
 460
 461         if (atomic_read(&sleep_block))
 462                 return 0;
 463
 464         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 465         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 466         if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
 467                  OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
 468                  OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 469                 return 0;
 470         /* Check for UART3. */
 471         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 472         if (l & OMAP24XX_EN_UART3)
 473                 return 0;
 474         if (sti_console_enabled)
 475                 return 0;
 476
 477         return 1;
 478 }
 479
 480 static void omap2_enter_mpu_retention(void)
 481 {
 482         u32 sleep_time = 0;
 483         int only_idle = 0;
 484
 485         /* Putting MPU into the WFI state while a transfer is active
 486          * seems to cause the I2C block to timeout. Why? Good question. */
 487         if (omap2_i2c_active())
 488                 return;
 489
 490         /* The peripherals seem not to be able to wake up the MPU when
 491          * it is in retention mode. */
 492         if (omap2_allow_mpu_retention()) {
 493                 /* REVISIT: These write to reserved bits? */
 494                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 495                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 496                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 497
 498                 /* Try to enter MPU retention */
 499                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 500                                   OMAP_LOGICRETSTATE,
 501                                   MPU_MOD, PM_PWSTCTRL);
 502         } else {
 503                 /* Block MPU retention */
 504
 505                 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 506                 only_idle = 1;
 507         }
 508
 509         if (omap2_pm_debug) {
 510                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 511                 sleep_time = omap2_read_32k_sync_counter();
 512         }
 513
 514         omap2_sram_idle();
 515
 516         if (omap2_pm_debug) {
 517                 unsigned long long tmp;
 518                 u32 resume_time;
 519
 520                 resume_time = omap2_read_32k_sync_counter();
 521                 tmp = resume_time - sleep_time;
 522                 tmp *= 1000000;
 523                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
 524         }
 525 }
 526
 527 static int omap2_can_sleep(void)
 528 {
 529         if (!enable_dyn_sleep)
 530                 return 0;
 531         if (omap2_fclks_active())
 532                 return 0;
 533         if (atomic_read(&sleep_block) > 0)
 534                 return 0;
 535         if (clk_get_usecount(osc_ck) > 1)
 536                 return 0;
 537         if (omap_dma_running())
 538                 return 0;
 539
 540         return 1;
 541 }
 542
 543 static void omap2_pm_idle(void)
 544 {
 545         local_irq_disable();
 546         local_fiq_disable();
 547
 548         if (!omap2_can_sleep()) {
 549                 /* timer_dyn_reprogram() takes about 100-200 us to complete.
 550                  * In some contexts (e.g. when waiting for a GPMC-SDRAM DMA
 551                  * transfer to complete), the increased latency is too much.
 552                  *
 553                  * omap2_block_sleep() and omap2_allow_sleep() can be used
 554                  * to indicate this.
 555                  */
 556                 if (atomic_read(&sleep_block) == 0) {
 557                         timer_dyn_reprogram();
 558                         if (omap2_irq_pending())
 559                                 goto out;
 560                 }
 561                 omap2_enter_mpu_retention();
 562                 goto out;
 563         }
 564
 565         /*
 566          * Since an interrupt may set up a timer, we don't want to
 567          * reprogram the hardware timer with interrupts enabled.
 568          * Re-enable interrupts only after returning from idle.
 569          */
 570         timer_dyn_reprogram();
 571
 572         if (omap2_irq_pending())
 573                 goto out;
 574
 575         omap2_enter_full_retention();
 576
 577 out:
 578         local_fiq_enable();
 579         local_irq_enable();
 580 }
 581
 582 static int omap2_pm_prepare(suspend_state_t state)
 583 {
 584         int error = 0;
 585
 586         /* We cannot sleep in idle until we have resumed */
 587         saved_idle = pm_idle;
 588         pm_idle = NULL;
 589
 590         switch (state) {
 591         case PM_SUSPEND_STANDBY:
 592         case PM_SUSPEND_MEM:
 593                 break;
 594         default:
 595                 return -EINVAL;
 596         }
 597
 598         return error;
 599 }
 600
 601 static int omap2_pm_suspend(void)
 602 {
 603         u32 wken_wkup, mir1;
 604
 605         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 606         prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 607
 608         /* Mask GPT1 */
 609         mir1 = omap_readl(0x480fe0a4);
 610         omap_writel(1 << 5, 0x480fe0ac);
 611
 612         omap2_enter_full_retention();
 613
 614         omap_writel(mir1, 0x480fe0a4);
 615         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 616
 617         return 0;
 618 }
 619
 620 static int omap2_pm_enter(suspend_state_t state)
 621 {
 622         int ret = 0;
 623
 624         switch (state) {
 625         case PM_SUSPEND_STANDBY:
 626         case PM_SUSPEND_MEM:
 627                 ret = omap2_pm_suspend();
 628                 break;
 629         default:
 630                 ret = -EINVAL;
 631         }
 632
 633         return ret;
 634 }
 635
 636 static int omap2_pm_finish(suspend_state_t state)
 637 {
 638         pm_idle = saved_idle;
 639         return 0;
 640 }
 641
 642 static struct pm_ops omap_pm_ops = {
 643         .prepare        = omap2_pm_prepare,
 644         .enter          = omap2_pm_enter,
 645         .finish         = omap2_pm_finish,
 646         .valid          = pm_valid_only_mem,
 647 };
 648
 649 static void __init prcm_setup_regs(void)
 650 {
 651         u32 l;
 652
 653         /* Enable autoidle */
 654         prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 655
 656         /* Set all domain wakeup dependencies */
 657         prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
 658         prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
 659         prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 660
 661         l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 662         /* Enable retention for all memory blocks */
 663         l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
 664                 OMAP24XX_MEM1RETSTATE;
 665
 666         /* Set power state to RETENTION */
 667         l &= ~OMAP_POWERSTATE_MASK;
 668         l |= 0x01 << OMAP_POWERSTATE_SHIFT;
 669         prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
 670
 671         prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 672                           OMAP_LOGICRETSTATE,
 673                           MPU_MOD, PM_PWSTCTRL);
 674
 675         /* Power down DSP and GFX */
 676         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 677                           OMAP24XX_DSP_MOD, PM_PWSTCTRL);
 678         prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
 679                           GFX_MOD, PM_PWSTCTRL);
 680
 681         /* Enable clock auto control for all domains */
 682         cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
 683         cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
 684                          OMAP24XX_AUTOSTATE_L3,
 685                          CORE_MOD, CM_CLKSTCTRL);
 686         cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
 687         cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
 688                          OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 689
 690         /* Enable clock autoidle for all domains */
 691         cm_write_mod_reg(OMAP24XX_AUTO_CAM |
 692                          OMAP24XX_AUTO_MAILBOXES |
 693                          OMAP24XX_AUTO_WDT4 |
 694                          OMAP2420_AUTO_WDT3 |
 695                          OMAP24XX_AUTO_MSPRO |
 696                          OMAP2420_AUTO_MMC |
 697                          OMAP24XX_AUTO_FAC |
 698                          OMAP2420_AUTO_EAC |
 699                          OMAP24XX_AUTO_HDQ |
 700                          OMAP24XX_AUTO_UART2 |
 701                          OMAP24XX_AUTO_UART1 |
 702                          OMAP24XX_AUTO_I2C2 |
 703                          OMAP24XX_AUTO_I2C1 |
 704                          OMAP24XX_AUTO_MCSPI2 |
 705                          OMAP24XX_AUTO_MCSPI1 |
 706                          OMAP24XX_AUTO_MCBSP2 |
 707                          OMAP24XX_AUTO_MCBSP1 |
 708                          OMAP24XX_AUTO_GPT12 |
 709                          OMAP24XX_AUTO_GPT11 |
 710                          OMAP24XX_AUTO_GPT10 |
 711                          OMAP24XX_AUTO_GPT9 |
 712                          OMAP24XX_AUTO_GPT8 |
 713                          OMAP24XX_AUTO_GPT7 |
 714                          OMAP24XX_AUTO_GPT6 |
 715                          OMAP24XX_AUTO_GPT5 |
 716                          OMAP24XX_AUTO_GPT4 |
 717                          OMAP24XX_AUTO_GPT3 |
 718                          OMAP24XX_AUTO_GPT2 |
 719                          OMAP2420_AUTO_VLYNQ |
 720                          OMAP24XX_AUTO_DSS,
 721                          CORE_MOD, CM_AUTOIDLE1);
 722         cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
 723                          OMAP24XX_AUTO_SSI |
 724                          OMAP24XX_AUTO_USB,
 725                          CORE_MOD, CM_AUTOIDLE2);
 726         cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
 727                          OMAP24XX_AUTO_GPMC |
 728                          OMAP24XX_AUTO_SDMA,
 729                          CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
 730         cm_write_mod_reg(OMAP24XX_AUTO_PKA |
 731                          OMAP24XX_AUTO_AES |
 732                          OMAP24XX_AUTO_RNG |
 733                          OMAP24XX_AUTO_SHA |
 734                          OMAP24XX_AUTO_DES,
 735                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 736
 737         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 738
 739         /* Put DPLL and both APLLs into autoidle mode */
 740         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 741                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 742                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 743                          PLL_MOD, CM_AUTOIDLE);
 744
 745         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
 746                          OMAP24XX_AUTO_WDT1 |
 747                          OMAP24XX_AUTO_MPU_WDT |
 748                          OMAP24XX_AUTO_GPIOS |
 749                          OMAP24XX_AUTO_32KSYNC |
 750                          OMAP24XX_AUTO_GPT1,
 751                          WKUP_MOD, CM_AUTOIDLE);
 752
 753         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 754          * stabilisation */
 755         prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 756
 757         /* Configure automatic voltage transition */
 758         prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
 759         prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
 760                       (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 761                       OMAP24XX_MEMRETCTRL |
 762                       (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 763                       (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 764                       OMAP24XX_PRCM_VOLTCTRL);
 765
 766         /* Enable wake-up events */
 767         prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
 768                           WKUP_MOD, PM_WKEN);
 769 }
 770
 771 int __init omap2_pm_init(void)
 772 {
 773         u32 l;
 774
 775         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 776         l = prm_read_reg(OMAP24XX_PRCM_REVISION);
 777         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 778
 779         osc_ck = clk_get(NULL, "osc_ck");
 780         if (IS_ERR(osc_ck)) {
 781                 printk(KERN_ERR "could not get osc_ck\n");
 782                 return -ENODEV;
 783         }
 784
 785         emul_ck = clk_get(NULL, "emul_ck");
 786         if (IS_ERR(emul_ck)) {
 787                 printk(KERN_ERR "could not get emul_ck\n");
 788                 clk_put(osc_ck);
 789                 return -ENODEV;
 790         }
 791
 792         prcm_setup_regs();
 793
 794         pm_init_serial_console();
 795
 796         /* Hack to prevent MPU retention when STI console is enabled. */
 797         {
 798                 const struct omap_sti_console_config *sti;
 799
 800                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 801                                       struct omap_sti_console_config);
 802                 if (sti != NULL && sti->enable)
 803                         sti_console_enabled = 1;
 804         }
 805
 806         /*
 807          * We copy the assembler sleep/wakeup routines to SRAM.
 808          * These routines need to be in SRAM as that's the only
 809          * memory the MPU can see when it wakes up.
 810          */
 811         omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 812                                          omap24xx_idle_loop_suspend_sz);
 813         omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 814                                             omap24xx_cpu_suspend_sz);
 815
 816         pm_set_ops(&omap_pm_ops);
 817         pm_idle = omap2_pm_idle;
 818
 819         l = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
 820         if (l)
 821                 printk(KERN_ERR "subsys_create_file failed: %d\n", l);
 822
 823         return 0;
 824 }
 825
 826 late_initcall(omap2_pm_init);