2 * linux/arch/arm/mach-omap2/pm.c
4 * OMAP2 Power Management Routines
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 * Copyright (C) 2006-2008 Nokia Corporation
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * Amit Kucheria <amit.kucheria@nokia.com>
14 * Igor Stoppa <igor.stoppa@nokia.com>
16 * Based on pm.c for omap1
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
23 #include <linux/suspend.h>
24 #include <linux/sched.h>
25 #include <linux/proc_fs.h>
26 #include <linux/interrupt.h>
27 #include <linux/sysfs.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
32 #include <linux/irq.h>
34 #include <asm/mach/time.h>
35 #include <asm/mach/irq.h>
36 #include <asm/mach-types.h>
38 #include <mach/irqs.h>
39 #include <mach/clock.h>
40 #include <mach/sram.h>
41 #include <mach/control.h>
42 #include <mach/gpio.h>
46 #include <mach/board.h>
49 #include "prm-regbits-24xx.h"
51 #include "cm-regbits-24xx.h"
55 #include <mach/powerdomain.h>
56 #include <mach/clockdomain.h>
58 static void (*omap2_sram_idle)(void);
59 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
60 void __iomem *sdrc_power);
61 static void (*saved_idle)(void);
63 static struct powerdomain *mpu_pwrdm;
64 static struct powerdomain *core_pwrdm;
66 static struct clockdomain *dsp_clkdm;
67 static struct clockdomain *gfx_clkdm;
69 static struct clk *osc_ck, *emul_ck;
71 static int omap2_fclks_active(void)
75 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
76 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
77 serial_console_fclk_mask(&f1, &f2);
83 static void omap2_enter_full_retention(void)
85 u32 l, sleep_time = 0;
87 /* There is 1 reference hold for all children of the oscillator
88 * clock, the following will remove it. If no one else uses the
89 * oscillator itself it will be disabled if/when we enter retention
94 /* Clear old wake-up events */
95 /* REVISIT: These write to reserved bits? */
96 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
97 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
98 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
101 * Set MPU powerdomain's next power state to RETENTION;
102 * preserve logic state during retention
104 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
105 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
107 /* Workaround to kill USB */
108 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
109 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
111 omap2_gpio_prepare_for_retention();
113 if (omap2_pm_debug) {
114 omap2_pm_dump(0, 0, 0);
115 sleep_time = omap2_read_32k_sync_counter();
118 /* One last check for pending IRQs to avoid extra latency due
119 * to sleeping unnecessarily. */
120 if (omap_irq_pending())
123 serial_console_sleep(1);
124 /* Jump to SRAM suspend code */
125 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
126 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
127 OMAP_SDRC_REGADDR(SDRC_POWER));
129 serial_console_sleep(0);
131 if (omap2_pm_debug) {
132 unsigned long long tmp;
135 resume_time = omap2_read_32k_sync_counter();
136 tmp = resume_time - sleep_time;
138 omap2_pm_dump(0, 1, tmp / 32768);
140 omap2_gpio_resume_after_retention();
144 /* clear CORE wake-up events */
145 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
146 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
148 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
149 prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
151 /* MPU domain wake events */
152 l = prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
154 prm_write_mod_reg(0x01, OCP_MOD,
155 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
157 prm_write_mod_reg(0x20, OCP_MOD,
158 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
160 /* Mask future PRCM-to-MPU interrupts */
161 prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
164 static int omap2_i2c_active(void)
168 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
169 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
172 static int sti_console_enabled;
174 static int omap2_allow_mpu_retention(void)
178 if (atomic_read(&sleep_block))
181 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
182 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
183 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
184 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
185 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
187 /* Check for UART3. */
188 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
189 if (l & OMAP24XX_EN_UART3)
191 if (sti_console_enabled)
197 static void omap2_enter_mpu_retention(void)
202 /* Putting MPU into the WFI state while a transfer is active
203 * seems to cause the I2C block to timeout. Why? Good question. */
204 if (omap2_i2c_active())
207 /* The peripherals seem not to be able to wake up the MPU when
208 * it is in retention mode. */
209 if (omap2_allow_mpu_retention()) {
210 /* REVISIT: These write to reserved bits? */
211 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
212 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
213 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
215 /* Try to enter MPU retention */
216 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
218 MPU_MOD, PM_PWSTCTRL);
220 /* Block MPU retention */
222 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
226 if (omap2_pm_debug) {
227 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
228 sleep_time = omap2_read_32k_sync_counter();
233 if (omap2_pm_debug) {
234 unsigned long long tmp;
237 resume_time = omap2_read_32k_sync_counter();
238 tmp = resume_time - sleep_time;
240 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
244 static int omap2_can_sleep(void)
246 if (!enable_dyn_sleep)
248 if (omap2_fclks_active())
250 if (atomic_read(&sleep_block) > 0)
252 if (clk_get_usecount(osc_ck) > 1)
254 if (omap_dma_running())
261 * Note that you can use clock_event_device->min_delta_ns if you want to
262 * avoid reprogramming timer too often when using CONFIG_NO_HZ.
264 static void omap2_pm_idle(void)
269 if (!omap2_can_sleep()) {
270 if (!atomic_read(&sleep_block) && omap_irq_pending())
272 omap2_enter_mpu_retention();
276 if (omap_irq_pending())
279 omap2_enter_full_retention();
286 static int omap2_pm_prepare(void)
288 /* We cannot sleep in idle until we have resumed */
289 saved_idle = pm_idle;
295 static int omap2_pm_suspend(void)
299 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
300 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
303 mir1 = omap_readl(0x480fe0a4);
304 omap_writel(1 << 5, 0x480fe0ac);
306 omap2_enter_full_retention();
308 omap_writel(mir1, 0x480fe0a4);
309 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
314 static int omap2_pm_enter(suspend_state_t state)
319 case PM_SUSPEND_STANDBY:
321 ret = omap2_pm_suspend();
330 static void omap2_pm_finish(void)
332 pm_idle = saved_idle;
335 static struct platform_suspend_ops omap_pm_ops = {
336 .prepare = omap2_pm_prepare,
337 .enter = omap2_pm_enter,
338 .finish = omap2_pm_finish,
339 .valid = suspend_valid_only_mem,
342 static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
344 omap2_clkdm_allow_idle(clkdm);
348 static void __init prcm_setup_regs(void)
350 int i, num_mem_banks;
351 struct powerdomain *pwrdm;
353 /* Enable autoidle */
354 prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
355 OMAP24XX_PRM_SYSCONFIG_OFFSET);
357 /* Set all domain wakeup dependencies */
358 prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
359 prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
360 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
361 prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
362 if (cpu_is_omap2430())
363 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
366 * Set CORE powerdomain memory banks to retain their contents
369 num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
370 for (i = 0; i < num_mem_banks; i++)
371 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
373 /* Set CORE powerdomain's next power state to RETENTION */
374 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
377 * Set MPU powerdomain's next power state to RETENTION;
378 * preserve logic state during retention
380 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
381 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
383 /* Force-power down DSP, GFX powerdomains */
385 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
386 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
387 omap2_clkdm_sleep(dsp_clkdm);
389 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
390 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
391 omap2_clkdm_sleep(gfx_clkdm);
393 /* Enable clockdomain hardware-supervised control for all clkdms */
394 clkdm_for_each(_pm_clkdm_enable_hwsup);
396 /* Enable clock autoidle for all domains */
397 cm_write_mod_reg(OMAP24XX_AUTO_CAM |
398 OMAP24XX_AUTO_MAILBOXES |
401 OMAP24XX_AUTO_MSPRO |
406 OMAP24XX_AUTO_UART2 |
407 OMAP24XX_AUTO_UART1 |
410 OMAP24XX_AUTO_MCSPI2 |
411 OMAP24XX_AUTO_MCSPI1 |
412 OMAP24XX_AUTO_MCBSP2 |
413 OMAP24XX_AUTO_MCBSP1 |
414 OMAP24XX_AUTO_GPT12 |
415 OMAP24XX_AUTO_GPT11 |
416 OMAP24XX_AUTO_GPT10 |
425 OMAP2420_AUTO_VLYNQ |
427 CORE_MOD, CM_AUTOIDLE1);
428 cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
431 CORE_MOD, CM_AUTOIDLE2);
432 cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
435 CORE_MOD, CM_AUTOIDLE3);
436 cm_write_mod_reg(OMAP24XX_AUTO_PKA |
441 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
443 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
445 /* Put DPLL and both APLLs into autoidle mode */
446 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
447 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
448 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
449 PLL_MOD, CM_AUTOIDLE);
451 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
453 OMAP24XX_AUTO_MPU_WDT |
454 OMAP24XX_AUTO_GPIOS |
455 OMAP24XX_AUTO_32KSYNC |
457 WKUP_MOD, CM_AUTOIDLE);
459 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
461 prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
462 OMAP24XX_PRCM_CLKSSETUP_OFFSET);
464 /* Configure automatic voltage transition */
465 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
466 OMAP24XX_PRCM_VOLTSETUP_OFFSET);
467 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
468 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
469 OMAP24XX_MEMRETCTRL |
470 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
471 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
472 OMAP24XX_GR_MOD, OMAP24XX_PRCM_VOLTCTRL_OFFSET);
474 /* Enable wake-up events */
475 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
479 int __init omap2_pm_init(void)
483 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
484 l = prm_read_mod_reg(OCP_MOD, OMAP24XX_PRM_REVISION_OFFSET);
485 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
487 /* Look up important powerdomains, clockdomains */
489 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
491 pr_err("PM: mpu_pwrdm not found\n");
493 core_pwrdm = pwrdm_lookup("core_pwrdm");
495 pr_err("PM: core_pwrdm not found\n");
497 dsp_clkdm = clkdm_lookup("dsp_clkdm");
499 pr_err("PM: mpu_clkdm not found\n");
501 gfx_clkdm = clkdm_lookup("gfx_clkdm");
503 pr_err("PM: gfx_clkdm not found\n");
506 osc_ck = clk_get(NULL, "osc_ck");
507 if (IS_ERR(osc_ck)) {
508 printk(KERN_ERR "could not get osc_ck\n");
512 if (cpu_is_omap242x()) {
513 emul_ck = clk_get(NULL, "emul_ck");
514 if (IS_ERR(emul_ck)) {
515 printk(KERN_ERR "could not get emul_ck\n");
523 pm_init_serial_console();
525 /* Hack to prevent MPU retention when STI console is enabled. */
527 const struct omap_sti_console_config *sti;
529 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
530 struct omap_sti_console_config);
531 if (sti != NULL && sti->enable)
532 sti_console_enabled = 1;
536 * We copy the assembler sleep/wakeup routines to SRAM.
537 * These routines need to be in SRAM as that's the only
538 * memory the MPU can see when it wakes up.
540 if (cpu_is_omap24xx()) {
541 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
542 omap24xx_idle_loop_suspend_sz);
544 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
545 omap24xx_cpu_suspend_sz);
548 suspend_set_ops(&omap_pm_ops);
549 pm_idle = omap2_pm_idle;