2 * linux/arch/arm/mach-omap2/pm34xx.c
4 * OMAP3 Power Management Routines
6 * Copyright (C) 2006-2008 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
10 * Copyright (C) 2005 Texas Instruments, Inc.
11 * Richard Woodruff <r-woodruff2@ti.com>
13 * Based on pm.c for omap1
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/err.h>
27 #include <mach/gpio.h>
28 #include <mach/sram.h>
30 #include <mach/clockdomain.h>
31 #include <mach/powerdomain.h>
34 #include "cm-regbits-34xx.h"
35 #include "prm-regbits-34xx.h"
39 #include "smartreflex.h"
42 struct powerdomain *pwrdm;
45 struct list_head node;
48 static LIST_HEAD(pwrst_list);
50 static void (*_omap_sram_idle)(u32 *addr, int save_state);
52 static void (*saved_idle)(void);
54 static struct powerdomain *mpu_pwrdm;
56 /* PRCM Interrupt Handler for wakeups */
57 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
59 u32 wkst, irqstatus_mpu;
63 wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
65 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
66 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
67 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
68 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
69 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
70 while (prm_read_mod_reg(WKUP_MOD, PM_WKST));
71 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
72 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
76 wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
78 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
79 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
80 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
81 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
82 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
83 while (prm_read_mod_reg(CORE_MOD, PM_WKST1));
84 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
85 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
87 wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
89 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
90 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
91 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
92 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
93 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
94 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3));
95 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
96 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
100 wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
102 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
103 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
104 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
105 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
106 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
107 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST));
108 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
109 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
112 if (system_rev > OMAP3430_REV_ES1_0) {
114 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
116 iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
118 fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
120 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
122 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
124 prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
126 while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
128 cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
130 cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
135 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
136 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
137 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
138 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
140 while (prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET));
145 static void omap_sram_idle(void)
147 /* Variable to tell what needs to be saved and restored
148 * in omap_sram_idle*/
149 /* save_state = 0 => Nothing to save and restored */
150 /* save_state = 1 => Only L1 and logic lost */
151 /* save_state = 2 => Only L2 lost */
152 /* save_state = 3 => L1, L2 and logic lost */
153 int save_state = 0, mpu_next_state;
155 if (!_omap_sram_idle)
158 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
159 switch (mpu_next_state) {
160 case PWRDM_POWER_RET:
161 /* No need to save context */
166 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
169 /* Disable smartreflex before entering WFI */
170 disable_smartreflex(SR1);
171 disable_smartreflex(SR2);
173 omap2_gpio_prepare_for_retention();
175 _omap_sram_idle(NULL, save_state);
177 omap2_gpio_resume_after_retention();
179 /* Enable smartreflex after WFI */
180 enable_smartreflex(SR1);
181 enable_smartreflex(SR2);
185 * Check if functional clocks are enabled before entering
186 * sleep. This function could be behind CONFIG_PM_DEBUG
187 * when all drivers are configuring their sysconfig registers
188 * properly and using their clocks properly.
190 static int omap3_fclks_active(void)
192 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
193 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
195 fck_core1 = cm_read_mod_reg(CORE_MOD,
197 if (system_rev > OMAP3430_REV_ES1_0) {
198 fck_core3 = cm_read_mod_reg(CORE_MOD,
199 OMAP3430ES2_CM_FCLKEN3);
200 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
202 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
205 fck_sgx = cm_read_mod_reg(GFX_MOD,
206 OMAP3430ES2_CM_FCLKEN3);
207 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
209 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
211 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
213 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
214 fck_cam | fck_per | fck_usbhost)
219 static int omap3_can_sleep(void)
221 if (!enable_dyn_sleep)
223 if (omap3_fclks_active())
225 if (atomic_read(&sleep_block) > 0)
230 /* This sets pwrdm state (other than mpu & core. Currently only ON &
231 * RET are supported. Function is assuming that clkdm doesn't have
232 * hw_sup mode enabled. */
233 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
236 int sleep_switch = 0;
239 if (pwrdm == NULL || IS_ERR(pwrdm))
242 cur_state = pwrdm_read_next_pwrst(pwrdm);
244 if (cur_state == state)
247 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
248 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
250 pwrdm_wait_transition(pwrdm);
253 ret = pwrdm_set_next_pwrst(pwrdm, state);
255 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
261 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
262 pwrdm_wait_transition(pwrdm);
269 static void omap3_pm_idle(void)
274 if (!omap3_can_sleep())
277 if (omap_irq_pending())
287 static int omap3_pm_prepare(void)
289 saved_idle = pm_idle;
294 static int omap3_pm_suspend(void)
296 struct power_state *pwrst;
299 /* Read current next_pwrsts */
300 list_for_each_entry(pwrst, &pwrst_list, node)
301 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
302 /* Set ones wanted by suspend */
303 list_for_each_entry(pwrst, &pwrst_list, node) {
304 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
306 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
313 /* Restore next_pwrsts */
314 list_for_each_entry(pwrst, &pwrst_list, node) {
315 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
316 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
317 if (state != pwrst->next_state) {
318 printk(KERN_INFO "Powerdomain (%s) didn't enter "
320 pwrst->pwrdm->name, pwrst->next_state);
325 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
327 printk(KERN_INFO "Successfully put all powerdomains "
328 "to target state\n");
333 static int omap3_pm_enter(suspend_state_t state)
338 case PM_SUSPEND_STANDBY:
340 ret = omap3_pm_suspend();
349 static void omap3_pm_finish(void)
351 pm_idle = saved_idle;
354 static struct platform_suspend_ops omap_pm_ops = {
355 .prepare = omap3_pm_prepare,
356 .enter = omap3_pm_enter,
357 .finish = omap3_pm_finish,
358 .valid = suspend_valid_only_mem,
361 static void __init prcm_setup_regs(void)
363 /* XXX Reset all wkdeps. This should be done when initializing
365 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
366 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
367 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
368 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
369 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
370 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
371 if (system_rev > OMAP3430_REV_ES1_0) {
372 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
373 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
375 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
378 * Enable interface clock autoidle for all modules.
379 * Note that in the long run this should be done by clockfw
382 OMAP3430ES2_AUTO_MMC3 |
383 OMAP3430ES2_AUTO_ICR |
385 OMAP3430_AUTO_SHA12 |
389 OMAP3430_AUTO_MSPRO |
391 OMAP3430_AUTO_MCSPI4 |
392 OMAP3430_AUTO_MCSPI3 |
393 OMAP3430_AUTO_MCSPI2 |
394 OMAP3430_AUTO_MCSPI1 |
398 OMAP3430_AUTO_UART2 |
399 OMAP3430_AUTO_UART1 |
400 OMAP3430_AUTO_GPT11 |
401 OMAP3430_AUTO_GPT10 |
402 OMAP3430_AUTO_MCBSP5 |
403 OMAP3430_AUTO_MCBSP1 |
404 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
405 OMAP3430_AUTO_MAILBOXES |
406 OMAP3430_AUTO_OMAPCTRL |
407 OMAP3430ES1_AUTO_FSHOSTUSB |
408 OMAP3430_AUTO_HSOTGUSB |
409 OMAP3430ES1_AUTO_D2D | /* This is es1 only */
411 CORE_MOD, CM_AUTOIDLE1);
417 OMAP3430_AUTO_SHA11 |
419 CORE_MOD, CM_AUTOIDLE2);
421 if (system_rev > OMAP3430_REV_ES1_0) {
423 OMAP3430ES2_AUTO_USBTLL,
424 CORE_MOD, CM_AUTOIDLE3);
430 OMAP3430_AUTO_GPIO1 |
431 OMAP3430_AUTO_32KSYNC |
432 OMAP3430_AUTO_GPT12 |
434 WKUP_MOD, CM_AUTOIDLE);
447 OMAP3430_AUTO_GPIO6 |
448 OMAP3430_AUTO_GPIO5 |
449 OMAP3430_AUTO_GPIO4 |
450 OMAP3430_AUTO_GPIO3 |
451 OMAP3430_AUTO_GPIO2 |
453 OMAP3430_AUTO_UART3 |
462 OMAP3430_AUTO_MCBSP4 |
463 OMAP3430_AUTO_MCBSP3 |
464 OMAP3430_AUTO_MCBSP2,
468 if (system_rev > OMAP3430_REV_ES1_0) {
470 OMAP3430ES2_AUTO_USBHOST,
471 OMAP3430ES2_USBHOST_MOD,
476 * Set all plls to autoidle. This is needed until autoidle is
479 cm_write_mod_reg(1 << OMAP3430_CLKTRCTRL_IVA2_SHIFT,
482 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
485 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
486 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
489 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
494 * Enable control of expternal oscillator through
495 * sys_clkreq. In the long run clock framework should
498 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
499 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
501 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
503 /* setup wakup source */
504 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
506 /* No need to write EN_IO, that is always enabled */
507 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
508 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
509 /* For some reason IO doesn't generate wakeup event even if
510 * it is selected to mpu wakeup goup */
511 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
512 OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
515 static int __init pwrdms_setup(struct powerdomain *pwrdm)
517 struct power_state *pwrst;
522 pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
525 pwrst->pwrdm = pwrdm;
526 pwrst->next_state = PWRDM_POWER_RET;
527 list_add(&pwrst->node, &pwrst_list);
529 if (pwrdm_has_hdwr_sar(pwrdm))
530 pwrdm_enable_hdwr_sar(pwrdm);
532 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
535 static int __init clkdms_setup(struct clockdomain *clkdm)
537 omap2_clkdm_allow_idle(clkdm);
541 int __init omap3_pm_init(void)
543 struct power_state *pwrst;
546 printk(KERN_ERR "Power Management for TI OMAP3.\n");
548 /* XXX prcm_setup_regs needs to be before enabling hw
549 * supervised mode for powerdomains */
552 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
553 (irq_handler_t)prcm_interrupt_handler,
554 IRQF_DISABLED, "prcm", NULL);
556 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
557 INT_34XX_PRCM_MPU_IRQ);
561 ret = pwrdm_for_each(pwrdms_setup);
563 printk(KERN_ERR "Failed to setup powerdomains\n");
567 (void) clkdm_for_each(clkdms_setup);
569 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
570 if (mpu_pwrdm == NULL) {
571 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
575 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
576 omap34xx_cpu_suspend_sz);
578 suspend_set_ops(&omap_pm_ops);
580 pm_idle = omap3_pm_idle;
585 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
586 list_for_each_entry(pwrst, &pwrst_list, node) {
587 list_del(&pwrst->node);
593 static void __init configure_vc(void)
595 prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
596 (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
597 OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
598 prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
599 (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
600 OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
602 prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON <<
603 OMAP3430_VC_CMD_ON_SHIFT) |
604 (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
605 (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
606 (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
607 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
609 prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON <<
610 OMAP3430_VC_CMD_ON_SHIFT) |
611 (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
612 (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
613 (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
614 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
616 prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
618 OMAP3_PRM_VC_CH_CONF_OFFSET);
620 prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
622 OMAP3_PRM_VC_I2C_CFG_OFFSET);
624 /* Setup voltctrl and other setup times */
625 prm_write_mod_reg(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
626 OMAP3_PRM_VOLTCTRL_OFFSET);
628 prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
629 OMAP3_PRM_CLKSETUP_OFFSET);
630 prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
631 OMAP3430_SETUP_TIME2_SHIFT) |
632 (OMAP3430_VOLTSETUP_TIME1 <<
633 OMAP3430_SETUP_TIME1_SHIFT),
634 OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
636 prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
637 OMAP3_PRM_VOLTOFFSET_OFFSET);
638 prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
639 OMAP3_PRM_VOLTSETUP2_OFFSET);
642 static int __init omap3_pm_early_init(void)
644 prm_clear_mod_reg_bits(OMAP3430_OFFMODE_POL, OMAP3430_GR_MOD,
645 OMAP3_PRM_POLCTRL_OFFSET);
652 arch_initcall(omap3_pm_early_init);