2 * linux/arch/arm/mach-omap2/pm34xx.c
4 * OMAP3 Power Management Routines
6 * Copyright (C) 2006-2008 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
10 * Copyright (C) 2005 Texas Instruments, Inc.
11 * Richard Woodruff <r-woodruff2@ti.com>
13 * Based on pm.c for omap1
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/err.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/sram.h>
29 #include <asm/arch/pm.h>
30 #include <asm/arch/clockdomain.h>
31 #include <asm/arch/powerdomain.h>
34 #include "cm-regbits-34xx.h"
35 #include "prm-regbits-34xx.h"
39 #include "smartreflex.h"
42 struct powerdomain *pwrdm;
45 struct list_head node;
48 static LIST_HEAD(pwrst_list);
50 static void (*_omap_sram_idle)(u32 *addr, int save_state);
52 static void (*saved_idle)(void);
54 static struct powerdomain *mpu_pwrdm;
56 /* PRCM Interrupt Handler for wakeups */
57 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
59 u32 wkst, irqstatus_mpu;
63 wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
65 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
66 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
67 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
68 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
69 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
70 while (prm_read_mod_reg(WKUP_MOD, PM_WKST));
71 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
72 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
76 wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
78 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
79 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
80 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
81 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
82 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
83 while (prm_read_mod_reg(CORE_MOD, PM_WKST1));
84 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
85 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
87 wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
89 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
90 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
91 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
92 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
93 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
94 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3));
95 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
96 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
100 wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
102 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
103 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
104 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
105 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
106 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
107 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST));
108 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
109 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
112 if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
114 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
116 iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
118 fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
120 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
122 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
124 prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
126 while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
128 cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
130 cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
135 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
136 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
137 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
138 OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
140 while (prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET));
145 static void omap_sram_idle(void)
147 /* Variable to tell what needs to be saved and restored
148 * in omap_sram_idle*/
149 /* save_state = 0 => Nothing to save and restored */
150 /* save_state = 1 => Only L1 and logic lost */
151 /* save_state = 2 => Only L2 lost */
152 /* save_state = 3 => L1, L2 and logic lost */
153 int save_state = 0, mpu_next_state;
155 if (!_omap_sram_idle)
158 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
159 switch (mpu_next_state) {
160 case PWRDM_POWER_RET:
161 /* No need to save context */
166 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
170 omap2_gpio_prepare_for_retention();
172 _omap_sram_idle(NULL, save_state);
174 omap2_gpio_resume_after_retention();
177 static int omap3_can_sleep(void)
179 if (!enable_dyn_sleep)
181 if (atomic_read(&sleep_block) > 0)
186 /* _clkdm_deny_idle - private callback function used by set_pwrdm_state() */
187 static int _clkdm_deny_idle(struct powerdomain *pwrdm,
188 struct clockdomain *clkdm)
190 omap2_clkdm_deny_idle(clkdm);
194 /* _clkdm_allow_idle - private callback function used by set_pwrdm_state() */
195 static int _clkdm_allow_idle(struct powerdomain *pwrdm,
196 struct clockdomain *clkdm)
198 omap2_clkdm_allow_idle(clkdm);
202 /* This sets pwrdm state (other than mpu & core. Currently only ON &
203 * RET are supported. Function is assuming that clkdm doesn't have
204 * hw_sup mode enabled. */
205 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
210 if (pwrdm == NULL || IS_ERR(pwrdm))
213 cur_state = pwrdm_read_next_pwrst(pwrdm);
215 if (cur_state == state)
218 pwrdm_for_each_clkdm(pwrdm, _clkdm_deny_idle);
220 ret = pwrdm_set_next_pwrst(pwrdm, state);
222 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
227 pwrdm_for_each_clkdm(pwrdm, _clkdm_allow_idle);
233 static void omap3_pm_idle(void)
238 if (!omap3_can_sleep())
241 if (omap_irq_pending())
251 static int omap3_pm_prepare(void)
253 saved_idle = pm_idle;
258 static int omap3_pm_suspend(void)
260 struct power_state *pwrst;
263 /* XXX Disable smartreflex before entering suspend */
264 disable_smartreflex(SR1);
265 disable_smartreflex(SR2);
267 /* Read current next_pwrsts */
268 list_for_each_entry(pwrst, &pwrst_list, node)
269 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
270 /* Set ones wanted by suspend */
271 list_for_each_entry(pwrst, &pwrst_list, node) {
272 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
274 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
281 /* Restore next_pwrsts */
282 list_for_each_entry(pwrst, &pwrst_list, node) {
283 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
284 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
285 if (state != pwrst->next_state) {
286 printk(KERN_INFO "Powerdomain (%s) didn't enter "
288 pwrst->pwrdm->name, pwrst->next_state);
293 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
295 printk(KERN_INFO "Successfully put all powerdomains "
296 "to target state\n");
298 /* XXX Enable smartreflex after suspend */
299 enable_smartreflex(SR1);
300 enable_smartreflex(SR2);
305 static int omap3_pm_enter(suspend_state_t state)
310 case PM_SUSPEND_STANDBY:
312 ret = omap3_pm_suspend();
321 static void omap3_pm_finish(void)
323 pm_idle = saved_idle;
326 static struct platform_suspend_ops omap_pm_ops = {
327 .prepare = omap3_pm_prepare,
328 .enter = omap3_pm_enter,
329 .finish = omap3_pm_finish,
330 .valid = suspend_valid_only_mem,
333 static void __init prcm_setup_regs(void)
335 /* XXX Reset all wkdeps. This should be done when initializing
337 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
338 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
339 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
340 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
341 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
342 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
343 if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
344 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
345 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
347 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
349 /* setup wakup source */
350 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
352 /* No need to write EN_IO, that is always enabled */
353 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
354 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
355 /* For some reason IO doesn't generate wakeup event even if
356 * it is selected to mpu wakeup goup */
357 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
358 OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
361 static int __init pwrdms_setup(struct powerdomain *pwrdm)
363 struct power_state *pwrst;
368 pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
371 pwrst->pwrdm = pwrdm;
372 pwrst->next_state = PWRDM_POWER_RET;
373 list_add(&pwrst->node, &pwrst_list);
375 if (pwrdm_has_hdwr_sar(pwrdm))
376 pwrdm_enable_hdwr_sar(pwrdm);
378 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
381 int __init omap3_pm_init(void)
383 struct power_state *pwrst;
386 printk(KERN_ERR "Power Management for TI OMAP3.\n");
388 /* XXX prcm_setup_regs needs to be before enabling hw
389 * supervised mode for powerdomains */
392 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
393 (irq_handler_t)prcm_interrupt_handler,
394 IRQF_DISABLED, "prcm", NULL);
396 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
397 INT_34XX_PRCM_MPU_IRQ);
401 ret = pwrdm_for_each(pwrdms_setup);
403 printk(KERN_ERR "Failed to setup powerdomains\n");
407 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
408 if (mpu_pwrdm == NULL) {
409 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
413 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
414 omap34xx_cpu_suspend_sz);
416 suspend_set_ops(&omap_pm_ops);
418 pm_idle = omap3_pm_idle;
423 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
424 list_for_each_entry(pwrst, &pwrst_list, node) {
425 list_del(&pwrst->node);
431 static void __init configure_vc(void)
433 prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
434 (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
435 OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
436 prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
437 (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
438 OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
440 prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON <<
441 OMAP3430_VC_CMD_ON_SHIFT) |
442 (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
443 (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
444 (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
445 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
447 prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON <<
448 OMAP3430_VC_CMD_ON_SHIFT) |
449 (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
450 (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
451 (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
452 OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
454 prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
456 OMAP3_PRM_VC_CH_CONF_OFFSET);
458 prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
460 OMAP3_PRM_VC_I2C_CFG_OFFSET);
462 /* Setup voltctrl and other setup times */
464 #ifdef CONFIG_OMAP_SYSOFFMODE
465 prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET |
466 OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
467 OMAP3_PRM_VOLTCTRL_OFFSET);
469 prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
470 OMAP3_PRM_CLKSETUP_OFFSET);
471 prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
472 OMAP3430_SETUP_TIME2_SHIFT) |
473 (OMAP3430_VOLTSETUP_TIME1 <<
474 OMAP3430_SETUP_TIME1_SHIFT),
475 OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
477 prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
478 OMAP3_PRM_VOLTOFFSET_OFFSET);
479 prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
480 OMAP3_PRM_VOLTSETUP2_OFFSET);
482 prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
483 OMAP3_PRM_VOLTCTRL_OFFSET);