2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
21 #include <linux/clk.h>
24 #include <mach/common.h>
25 #include <mach/board.h>
26 #include <mach/clock.h>
27 #include <mach/control.h>
31 #include "prm-regbits-34xx.h"
33 #define DEFAULT_TIMEOUT (2 * HZ)
35 struct omap_uart_state {
38 struct timer_list timer;
50 struct plat_serial8250_port *p;
51 struct list_head node;
54 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
55 static LIST_HEAD(uart_list);
57 static struct plat_serial8250_port serial_platform_data[] = {
59 .membase = IO_ADDRESS(OMAP_UART1_BASE),
60 .mapbase = OMAP_UART1_BASE,
62 .flags = UPF_BOOT_AUTOCONF,
65 .uartclk = OMAP24XX_BASE_BAUD * 16,
67 .membase = IO_ADDRESS(OMAP_UART2_BASE),
68 .mapbase = OMAP_UART2_BASE,
70 .flags = UPF_BOOT_AUTOCONF,
73 .uartclk = OMAP24XX_BASE_BAUD * 16,
75 .membase = IO_ADDRESS(OMAP_UART3_BASE),
76 .mapbase = OMAP_UART3_BASE,
78 .flags = UPF_BOOT_AUTOCONF,
81 .uartclk = OMAP24XX_BASE_BAUD * 16,
87 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
90 offset <<= up->regshift;
91 return (unsigned int)__raw_readb(up->membase + offset);
94 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
97 offset <<= p->regshift;
98 __raw_writeb(value, p->membase + offset);
102 * Internal UARTs need to be initialized for the 8250 autoconfig to work
103 * properly. Note that the TX watermark initialization may not be needed
104 * once the 8250.c watermark handling code is merged.
106 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
108 struct plat_serial8250_port *p = uart->p;
110 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
111 serial_write_reg(p, UART_OMAP_SCR, 0x08);
112 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
113 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
117 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
120 struct plat_serial8250_port *p = uart->p;
123 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
129 serial_write_reg(p, UART_OMAP_SYSC, sysc);
132 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
137 clk_enable(uart->ick);
138 clk_enable(uart->fck);
142 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
148 clk_disable(uart->ick);
149 clk_disable(uart->fck);
152 static void omap_uart_block_sleep(struct omap_uart_state *uart)
154 omap_uart_enable_clocks(uart);
156 omap_uart_smart_idle_enable(uart, 0);
158 mod_timer(&uart->timer, jiffies + uart->timeout);
161 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
166 omap_uart_smart_idle_enable(uart, 1);
168 del_timer(&uart->timer);
171 static void omap_uart_idle_timer(unsigned long data)
173 struct omap_uart_state *uart = (struct omap_uart_state *)data;
175 omap_uart_allow_sleep(uart);
178 void omap_uart_prepare_idle(int num)
180 struct omap_uart_state *uart;
182 list_for_each_entry(uart, &uart_list, node) {
183 if (!clocks_off_while_idle)
186 if (num == uart->num && uart->can_sleep) {
187 omap_uart_disable_clocks(uart);
193 void omap_uart_resume_idle(int num)
195 struct omap_uart_state *uart;
197 list_for_each_entry(uart, &uart_list, node) {
198 if (num == uart->num) {
199 omap_uart_enable_clocks(uart);
201 /* Check for IO pad wakeup */
202 if (cpu_is_omap34xx() && uart->padconf) {
203 u16 p = omap_ctrl_readw(uart->padconf);
205 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
206 omap_uart_block_sleep(uart);
209 /* Check for normal UART wakeup */
210 if (__raw_readl(uart->wk_st) & uart->wk_mask)
211 omap_uart_block_sleep(uart);
218 void omap_uart_prepare_suspend(void)
220 struct omap_uart_state *uart;
222 list_for_each_entry(uart, &uart_list, node) {
223 omap_uart_allow_sleep(uart);
227 int omap_uart_can_sleep(void)
229 struct omap_uart_state *uart;
232 list_for_each_entry(uart, &uart_list, node) {
236 if (!uart->can_sleep) {
241 /* This UART can now safely sleep. */
242 omap_uart_allow_sleep(uart);
249 * omap_uart_interrupt()
251 * This handler is used only to detect that *any* UART interrupt has
252 * occurred. It does _nothing_ to handle the interrupt. Rather,
253 * any UART interrupt will trigger the inactivity timer so the
254 * UART will not idle or sleep for its timeout period.
257 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
259 struct omap_uart_state *uart = dev_id;
261 omap_uart_block_sleep(uart);
266 static void omap_uart_idle_init(struct omap_uart_state *uart)
269 struct plat_serial8250_port *p = uart->p;
273 uart->timeout = DEFAULT_TIMEOUT;
274 setup_timer(&uart->timer, omap_uart_idle_timer,
275 (unsigned long) uart);
276 mod_timer(&uart->timer, jiffies + uart->timeout);
277 omap_uart_smart_idle_enable(uart, 0);
279 if (cpu_is_omap34xx()) {
280 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
284 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
285 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
288 wk_mask = OMAP3430_ST_UART1_MASK;
292 wk_mask = OMAP3430_ST_UART2_MASK;
296 wk_mask = OMAP3430_ST_UART3_MASK;
300 uart->wk_mask = wk_mask;
301 uart->padconf = padconf;
302 } else if (cpu_is_omap24xx()) {
305 if (cpu_is_omap2430()) {
306 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
307 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
308 } else if (cpu_is_omap2420()) {
309 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
310 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
314 wk_mask = OMAP24XX_ST_UART1_MASK;
317 wk_mask = OMAP24XX_ST_UART2_MASK;
320 wk_mask = OMAP24XX_ST_UART3_MASK;
323 uart->wk_mask = wk_mask;
331 /* Set wake-enable bit */
332 if (uart->wk_en && uart->wk_mask) {
333 v = __raw_readl(uart->wk_en);
335 __raw_writel(v, uart->wk_en);
338 /* Ensure IOPAD wake-enables are set */
339 if (cpu_is_omap34xx() && uart->padconf) {
342 v = omap_ctrl_readw(uart->padconf);
343 v |= OMAP3_PADCONF_WAKEUPENABLE0;
344 omap_ctrl_writew(v, uart->padconf);
347 p->flags |= UPF_SHARE_IRQ;
348 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
349 "serial idle", (void *)uart);
354 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
355 #endif /* CONFIG_PM */
357 void __init omap_serial_init(void)
360 const struct omap_uart_config *info;
364 * Make sure the serial ports are muxed on at this point.
365 * You have to mux them off in device drivers later on
369 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
374 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
375 struct plat_serial8250_port *p = serial_platform_data + i;
376 struct omap_uart_state *uart = &omap_uart[i];
378 if (!(info->enabled_uarts & (1 << i))) {
384 sprintf(name, "uart%d_ick", i+1);
385 uart->ick = clk_get(NULL, name);
386 if (IS_ERR(uart->ick)) {
387 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
391 sprintf(name, "uart%d_fck", i+1);
392 uart->fck = clk_get(NULL, name);
393 if (IS_ERR(uart->fck)) {
394 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
398 if (!uart->ick || !uart->fck)
402 p->private_data = uart;
404 list_add(&uart->node, &uart_list);
406 omap_uart_enable_clocks(uart);
407 omap_uart_reset(uart);
408 omap_uart_idle_init(uart);
412 static struct platform_device serial_device = {
413 .name = "serial8250",
414 .id = PLAT8250_DEV_PLATFORM,
416 .platform_data = serial_platform_data,
420 static int __init omap_init(void)
422 return platform_device_register(&serial_device);
424 arch_initcall(omap_init);