arch/arm/mach-orion/rd88f5182-setup.c

   1 /*
   2  * arch/arm/mach-orion/rd88f5182-setup.c
   3  *
   4  * Marvell Orion-NAS Reference Design Setup
   5  *
   6  * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
   7  *
   8  * This file is licensed under  the terms of the GNU General Public
   9  * License version 2. This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pci.h>
  17 #include <linux/irq.h>
  18 #include <linux/mtd/physmap.h>
  19 #include <linux/mv643xx_eth.h>
  20 #include <linux/i2c.h>
  21 #include <asm/mach-types.h>
  22 #include <asm/gpio.h>
  23 #include <asm/leds.h>
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/pci.h>
  26 #include <asm/arch/orion.h>
  27 #include <asm/arch/platform.h>
  28 #include "common.h"
  29
  30 /*****************************************************************************
  31  * RD-88F5182 Info
  32  ****************************************************************************/
  33
  34 /*
  35  * 512K NOR flash Device bus boot chip select
  36  */
  37
  38 #define RD88F5182_NOR_BOOT_BASE         0xf4000000
  39 #define RD88F5182_NOR_BOOT_SIZE         SZ_512K
  40
  41 /*
  42  * 16M NOR flash on Device bus chip select 1
  43  */
  44
  45 #define RD88F5182_NOR_BASE              0xfc000000
  46 #define RD88F5182_NOR_SIZE              SZ_16M
  47
  48 /*
  49  * PCI
  50  */
  51
  52 #define RD88F5182_PCI_SLOT0_OFFS        7
  53 #define RD88F5182_PCI_SLOT0_IRQ_A_PIN   7
  54 #define RD88F5182_PCI_SLOT0_IRQ_B_PIN   6
  55
  56 /*
  57  * GPIO Debug LED
  58  */
  59
  60 #define RD88F5182_GPIO_DBG_LED          0
  61
  62 /*****************************************************************************
  63  * 16M NOR Flash on Device bus CS1
  64  ****************************************************************************/
  65
  66 static struct physmap_flash_data rd88f5182_nor_flash_data = {
  67         .width          = 1,
  68 };
  69
  70 static struct resource rd88f5182_nor_flash_resource = {
  71         .flags                  = IORESOURCE_MEM,
  72         .start                  = RD88F5182_NOR_BASE,
  73         .end                    = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
  74 };
  75
  76 static struct platform_device rd88f5182_nor_flash = {
  77         .name                   = "physmap-flash",
  78         .id                     = 0,
  79         .dev            = {
  80                 .platform_data  = &rd88f5182_nor_flash_data,
  81         },
  82         .num_resources          = 1,
  83         .resource               = &rd88f5182_nor_flash_resource,
  84 };
  85
  86 #ifdef CONFIG_LEDS
  87
  88 /*****************************************************************************
  89  * Use GPIO debug led as CPU active indication
  90  ****************************************************************************/
  91
  92 static void rd88f5182_dbgled_event(led_event_t evt)
  93 {
  94         int val;
  95
  96         if (evt == led_idle_end)
  97                 val = 1;
  98         else if (evt == led_idle_start)
  99                 val = 0;
 100         else
 101                 return;
 102
 103         gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
 104 }
 105
 106 static int __init rd88f5182_dbgled_init(void)
 107 {
 108         int pin;
 109
 110         if (machine_is_rd88f5182()) {
 111                 pin = RD88F5182_GPIO_DBG_LED;
 112
 113                 if (gpio_request(pin, "DBGLED") == 0) {
 114                         if (gpio_direction_output(pin, 0) != 0) {
 115                                 printk(KERN_ERR "rd88f5182_dbgled_init failed "
 116                                                 "to set output pin %d\n", pin);
 117                                 gpio_free(pin);
 118                                 return 0;
 119                         }
 120                 } else {
 121                         printk(KERN_ERR "rd88f5182_dbgled_init failed "
 122                                         "to request gpio %d\n", pin);
 123                         return 0;
 124                 }
 125
 126                 leds_event = rd88f5182_dbgled_event;
 127         }
 128         return 0;
 129 }
 130
 131 __initcall(rd88f5182_dbgled_init);
 132
 133 #endif
 134
 135 /*****************************************************************************
 136  * PCI
 137  ****************************************************************************/
 138
 139 void __init rd88f5182_pci_preinit(void)
 140 {
 141         int pin;
 142
 143         /*
 144          * Configure PCI GPIO IRQ pins
 145          */
 146         pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
 147         if (gpio_request(pin, "PCI IntA") == 0) {
 148                 if (gpio_direction_input(pin) == 0) {
 149                         set_irq_type(gpio_to_irq(pin), IRQT_LOW);
 150                 } else {
 151                         printk(KERN_ERR "rd88f5182_pci_preinit faield to "
 152                                         "set_irq_type pin %d\n", pin);
 153                         gpio_free(pin);
 154                 }
 155         } else {
 156                 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
 157         }
 158
 159         pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
 160         if (gpio_request(pin, "PCI IntB") == 0) {
 161                 if (gpio_direction_input(pin) == 0) {
 162                         set_irq_type(gpio_to_irq(pin), IRQT_LOW);
 163                 } else {
 164                         printk(KERN_ERR "rd88f5182_pci_preinit faield to "
 165                                         "set_irq_type pin %d\n", pin);
 166                         gpio_free(pin);
 167                 }
 168         } else {
 169                 printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
 170         }
 171 }
 172
 173 static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 174 {
 175         /*
 176          * PCI-E isn't used on the RD2
 177          */
 178         if (dev->bus->number == orion_pcie_local_bus_nr())
 179                 return IRQ_ORION_PCIE0_INT;
 180
 181         /*
 182          * PCI IRQs are connected via GPIOs
 183          */
 184         switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
 185         case 0:
 186                 if (pin == 1)
 187                         return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
 188                 else
 189                         return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
 190         default:
 191                 return -1;
 192         }
 193 }
 194
 195 static struct hw_pci rd88f5182_pci __initdata = {
 196         .nr_controllers = 2,
 197         .preinit        = rd88f5182_pci_preinit,
 198         .swizzle        = pci_std_swizzle,
 199         .setup          = orion_pci_sys_setup,
 200         .scan           = orion_pci_sys_scan_bus,
 201         .map_irq        = rd88f5182_pci_map_irq,
 202 };
 203
 204 static int __init rd88f5182_pci_init(void)
 205 {
 206         if (machine_is_rd88f5182())
 207                 pci_common_init(&rd88f5182_pci);
 208
 209         return 0;
 210 }
 211
 212 subsys_initcall(rd88f5182_pci_init);
 213
 214 /*****************************************************************************
 215  * Ethernet
 216  ****************************************************************************/
 217
 218 static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
 219         .phy_addr       = 8,
 220         .force_phy_addr = 1,
 221 };
 222
 223 /*****************************************************************************
 224  * RTC DS1338 on I2C bus
 225  ****************************************************************************/
 226 static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
 227         .driver_name    = "rtc-ds1307",
 228         .type           = "ds1338",
 229         .addr           = 0x68,
 230 };
 231
 232 /*****************************************************************************
 233  * General Setup
 234  ****************************************************************************/
 235
 236 static struct platform_device *rd88f5182_devices[] __initdata = {
 237         &rd88f5182_nor_flash,
 238 };
 239
 240 static void __init rd88f5182_init(void)
 241 {
 242         /*
 243          * Setup basic Orion functions. Need to be called early.
 244          */
 245         orion_init();
 246
 247         /*
 248          * Setup the CPU address decode windows for our devices
 249          */
 250         orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE,
 251                                 RD88F5182_NOR_BOOT_SIZE, -1);
 252         orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE,
 253                                 RD88F5182_NOR_SIZE, -1);
 254
 255         /*
 256          * Open a special address decode windows for the PCIE WA.
 257          */
 258         orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
 259         orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
 260                 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
 261
 262         /*
 263          * Setup Multiplexing Pins --
 264          * MPP[0] Debug Led (GPIO - Out)
 265          * MPP[1] Debug Led (GPIO - Out)
 266          * MPP[2] N/A
 267          * MPP[3] RTC_Int (GPIO - In)
 268          * MPP[4] GPIO
 269          * MPP[5] GPIO
 270          * MPP[6] PCI_intA (GPIO - In)
 271          * MPP[7] PCI_intB (GPIO - In)
 272          * MPP[8-11] N/A
 273          * MPP[12] SATA 0 presence Indication
 274          * MPP[13] SATA 1 presence Indication
 275          * MPP[14] SATA 0 active Indication
 276          * MPP[15] SATA 1 active indication
 277          * MPP[16-19] Not used
 278          * MPP[20] PCI Clock to MV88F5182
 279          * MPP[21] PCI Clock to mini PCI CON11
 280          * MPP[22] USB 0 over current indication
 281          * MPP[23] USB 1 over current indication
 282          * MPP[24] USB 1 over current enable
 283          * MPP[25] USB 0 over current enable
 284          */
 285
 286         orion_write(MPP_0_7_CTRL, 0x00000003);
 287         orion_write(MPP_8_15_CTRL, 0x55550000);
 288         orion_write(MPP_16_19_CTRL, 0x5555);
 289
 290         orion_gpio_set_valid_pins(0x000000fb);
 291
 292         platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
 293         i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
 294         orion_eth_init(&rd88f5182_eth_data);
 295 }
 296
 297 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
 298         /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
 299         .phys_io        = ORION_REGS_BASE,
 300         .io_pg_offst    = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
 301         .boot_params    = 0x00000100,
 302         .init_machine   = rd88f5182_init,
 303         .map_io         = orion_map_io,
 304         .init_irq       = orion_init_irq,
 305         .timer          = &orion_timer,
 306 MACHINE_END