2 * linux/arch/arm/mach-pxa/cpu-pxa.c
4 * Copyright (C) 2002,2003 Intrinsyc Software
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * 31-Jul-2002 : Initial version [FB]
22 * 29-Jan-2003 : added PXA255 support [FB]
23 * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
26 * This driver may change the memory bus clock rate, but will not do any
27 * platform specific access timing changes... for example if you have flash
28 * memory connected to CS0, you will need to register a platform specific
29 * notifier which will adjust the memory access strobes to maintain a
30 * minimum strobe width.
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/sched.h>
37 #include <linux/init.h>
38 #include <linux/cpufreq.h>
40 #include <asm/hardware.h>
41 #include <asm/arch/pxa-regs.h>
42 #include <asm/arch/pxa2xx-regs.h>
45 static unsigned int freq_debug;
46 module_param(freq_debug, uint, 0);
47 MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
59 /* Define the refresh period in mSec for the SDRAM and the number of rows */
60 #define SDRAM_TREF 64 /* standard 64ms SDRAM */
61 #define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
62 #define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
64 #define CCLKCFG_TURBO 0x1
65 #define CCLKCFG_FCS 0x2
66 #define PXA25x_MIN_FREQ 99500
67 #define PXA25x_MAX_FREQ 398100
68 #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
69 #define MDREFR_DRI_MASK 0xFFF
72 /* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
73 static pxa_freqs_t pxa255_run_freqs[] =
75 /* CPU MEMBUS CCCR DIV2 run turbo PXbus SDRAM */
76 { 99500, 99500, 0x121, 1}, /* 99, 99, 50, 50 */
77 {132700, 132700, 0x123, 1}, /* 133, 133, 66, 66 */
78 {199100, 99500, 0x141, 0}, /* 199, 199, 99, 99 */
79 {265400, 132700, 0x143, 1}, /* 265, 265, 133, 66 */
80 {331800, 165900, 0x145, 1}, /* 331, 331, 166, 83 */
81 {398100, 99500, 0x161, 0}, /* 398, 398, 196, 99 */
84 #define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
86 static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
88 /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
89 static pxa_freqs_t pxa255_turbo_freqs[] =
91 /* CPU MEMBUS CCCR DIV2 run turbo PXbus SDRAM */
92 { 99500, 99500, 0x121, 1}, /* 99, 99, 50, 50 */
93 {199100, 99500, 0x221, 0}, /* 99, 199, 50, 99 */
94 {298500, 99500, 0x321, 0}, /* 99, 287, 50, 99 */
95 {298600, 99500, 0x1c1, 0}, /* 199, 287, 99, 99 */
96 {398100, 99500, 0x241, 0}, /* 199, 398, 99, 99 */
99 #define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
101 static struct cpufreq_frequency_table
102 pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
104 extern unsigned get_clk_frequency_khz(int info);
106 /* find a valid frequency point */
107 static int pxa_verify_policy(struct cpufreq_policy *policy)
109 struct cpufreq_frequency_table *pxa_freqs_table;
112 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
113 pxa_freqs_table = pxa255_run_freq_table;
114 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
115 pxa_freqs_table = pxa255_turbo_freq_table;
117 printk("CPU PXA: Unknown policy found. "
118 "Using CPUFREQ_POLICY_PERFORMANCE\n");
119 pxa_freqs_table = pxa255_run_freq_table;
122 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
125 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
126 policy->min, policy->max);
131 static int pxa_set_target(struct cpufreq_policy *policy,
132 unsigned int target_freq,
133 unsigned int relation)
135 struct cpufreq_frequency_table *pxa_freqs_table;
136 pxa_freqs_t *pxa_freq_settings;
137 struct cpufreq_freqs freqs;
140 unsigned int unused, preset_mdrefr, postset_mdrefr;
141 void *ramstart = phys_to_virt(0xa0000000);
143 /* Get the current policy */
144 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
145 pxa_freq_settings = pxa255_run_freqs;
146 pxa_freqs_table = pxa255_run_freq_table;
147 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
148 pxa_freq_settings = pxa255_turbo_freqs;
149 pxa_freqs_table = pxa255_turbo_freq_table;
151 printk("CPU PXA: Unknown policy found. "
152 "Using CPUFREQ_POLICY_PERFORMANCE\n");
153 pxa_freq_settings = pxa255_run_freqs;
154 pxa_freqs_table = pxa255_run_freq_table;
157 /* Lookup the next frequency */
158 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
159 target_freq, relation, &idx)) {
163 freqs.old = policy->cur;
164 freqs.new = pxa_freq_settings[idx].khz;
165 freqs.cpu = policy->cpu;
168 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
170 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
171 (pxa_freq_settings[idx].membus / 2000) :
172 (pxa_freq_settings[idx].membus / 1000));
175 * Tell everyone what we're about to do...
176 * you should add a notify client with any platform specific
177 * Vcc changing capability
179 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
181 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
182 * we need to preset the smaller DRI before the change. If we're
183 * speeding up we need to set the larger DRI value after the change.
185 preset_mdrefr = postset_mdrefr = MDREFR;
186 if ((MDREFR & MDREFR_DRI_MASK) >
187 MDREFR_DRI(pxa_freq_settings[idx].membus)) {
188 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
189 MDREFR_DRI(pxa_freq_settings[idx].membus);
191 postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
192 MDREFR_DRI(pxa_freq_settings[idx].membus);
194 /* If we're dividing the memory clock by two for the SDRAM clock, this
195 * must be set prior to the change. Clearing the divide must be done
198 if (pxa_freq_settings[idx].div2) {
199 preset_mdrefr |= MDREFR_DB2_MASK;
200 postset_mdrefr |= MDREFR_DB2_MASK;
202 postset_mdrefr &= ~MDREFR_DB2_MASK;
205 local_irq_save(flags);
207 /* Set new the CCCR */
208 CCCR = pxa_freq_settings[idx].cccr;
211 ldr r4, [%1] /* load MDREFR */ \n\
215 str %4, [%1] /* preset the MDREFR */ \n\
216 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
217 str %5, [%1] /* postset the MDREFR */ \n\
224 : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
225 "r" (preset_mdrefr), "r" (postset_mdrefr)
227 local_irq_restore(flags);
230 * Tell everyone what we've just done...
231 * you should add a notify client with any platform specific
232 * SDRAM refresh timer adjustments
234 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
239 static unsigned int pxa_cpufreq_get(unsigned int cpu)
241 return get_clk_frequency_khz(0);
244 static int pxa_cpufreq_init(struct cpufreq_policy *policy)
248 /* set default policy and cpuinfo */
249 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
250 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
251 policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
252 policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
253 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
254 policy->cur = get_clk_frequency_khz(0); /* current freq */
255 policy->min = policy->max = policy->cur;
257 /* Generate the run cpufreq_frequency_table struct */
258 for (i = 0; i < NUM_RUN_FREQS; i++) {
259 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
260 pxa255_run_freq_table[i].index = i;
263 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
264 /* Generate the turbo cpufreq_frequency_table struct */
265 for (i = 0; i < NUM_TURBO_FREQS; i++) {
266 pxa255_turbo_freq_table[i].frequency =
267 pxa255_turbo_freqs[i].khz;
268 pxa255_turbo_freq_table[i].index = i;
270 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
272 printk(KERN_INFO "PXA CPU frequency change support initialized\n");
277 static struct cpufreq_driver pxa_cpufreq_driver = {
278 .verify = pxa_verify_policy,
279 .target = pxa_set_target,
280 .init = pxa_cpufreq_init,
281 .get = pxa_cpufreq_get,
285 static int __init pxa_cpu_init(void)
289 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
293 static void __exit pxa_cpu_exit(void)
296 cpufreq_unregister_driver(&pxa_cpufreq_driver);
300 MODULE_AUTHOR("Intrinsyc Software Inc.");
301 MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
302 MODULE_LICENSE("GPL");
303 module_init(pxa_cpu_init);
304 module_exit(pxa_cpu_exit);