1 /* linux/arch/arm/mach-s3c2443/clock.c
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2443 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/sysdev.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33 #include <linux/serial_core.h>
35 #include <asm/mach/map.h>
37 #include <asm/hardware.h>
40 #include <asm/arch/regs-s3c2443-clock.h>
42 #include <asm/plat-s3c24xx/s3c2443.h>
43 #include <asm/plat-s3c24xx/clock.h>
44 #include <asm/plat-s3c24xx/cpu.h>
46 /* We currently have to assume that the system is running
47 * from the XTPll input, and that all ***REFCLKs are being
48 * fed from it, as we cannot read the state of OM[4] from
51 * It would be possible for each board initialisation to
52 * set the correct muxing at initialisation
55 static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
57 unsigned int clocks = clk->ctrlbit;
60 clkcon = __raw_readl(S3C2443_HCLKCON);
67 __raw_writel(clkcon, S3C2443_HCLKCON);
72 static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
74 unsigned int clocks = clk->ctrlbit;
77 clkcon = __raw_readl(S3C2443_PCLKCON);
84 __raw_writel(clkcon, S3C2443_PCLKCON);
89 static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
91 unsigned int clocks = clk->ctrlbit;
94 clkcon = __raw_readl(S3C2443_SCLKCON);
101 __raw_writel(clkcon, S3C2443_SCLKCON);
106 static unsigned long s3c2443_roundrate_clksrc(struct clk *clk,
110 unsigned long parent_rate = clk_get_rate(clk->parent);
113 if (rate > parent_rate)
116 /* note, we remove the +/- 1 calculations as they cancel out */
118 div = (rate / parent_rate);
125 return parent_rate / div;
128 static unsigned long s3c2443_roundrate_clksrc4(struct clk *clk,
131 return s3c2443_roundrate_clksrc(clk, rate, 4);
134 static unsigned long s3c2443_roundrate_clksrc16(struct clk *clk,
137 return s3c2443_roundrate_clksrc(clk, rate, 16);
140 static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk,
143 return s3c2443_roundrate_clksrc(clk, rate, 256);
146 /* clock selections */
148 /* CPU EXTCLK input */
149 static struct clk clk_ext = {
154 static struct clk clk_mpllref = {
161 static struct clk clk_mpll = {
163 .parent = &clk_mpllref,
168 static struct clk clk_epllref;
170 static struct clk clk_epll = {
172 .parent = &clk_epllref,
176 static struct clk clk_i2s_ext = {
181 static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent)
183 unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
185 clksrc &= ~S3C2443_CLKSRC_EPLLREF_MASK;
187 if (parent == &clk_xtal)
188 clksrc |= S3C2443_CLKSRC_EPLLREF_XTAL;
189 else if (parent == &clk_ext)
190 clksrc |= S3C2443_CLKSRC_EPLLREF_EXTCLK;
191 else if (parent != &clk_mpllref)
194 __raw_writel(clksrc, S3C2443_CLKSRC);
195 clk->parent = parent;
200 static struct clk clk_epllref = {
203 .set_parent = s3c2443_setparent_epllref,
206 static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
208 unsigned long parent_rate = clk_get_rate(clk->parent);
209 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
211 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
212 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
214 return parent_rate / (div + 1);
217 static struct clk clk_mdivclk = {
219 .parent = &clk_mpllref,
221 .get_rate = s3c2443_getrate_mdivclk,
224 static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
226 unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
228 clksrc &= ~(S3C2443_CLKSRC_MSYSCLK_MPLL |
229 S3C2443_CLKSRC_EXTCLK_DIV);
231 if (parent == &clk_mpll)
232 clksrc |= S3C2443_CLKSRC_MSYSCLK_MPLL;
233 else if (parent == &clk_mdivclk)
234 clksrc |= S3C2443_CLKSRC_EXTCLK_DIV;
235 else if (parent != &clk_mpllref)
238 __raw_writel(clksrc, S3C2443_CLKSRC);
239 clk->parent = parent;
244 static struct clk clk_msysclk = {
248 .set_parent = s3c2443_setparent_msysclk,
253 * this clock is sourced from msysclk and can have a number of
254 * divider values applied to it to then be fed into armclk.
257 static struct clk clk_armdiv = {
260 .parent = &clk_msysclk,
265 * this is the clock fed into the ARM core itself, either from
266 * armdiv or from hclk.
269 static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent)
271 unsigned long clkdiv0;
273 clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
275 if (parent == &clk_armdiv)
276 clkdiv0 &= ~S3C2443_CLKDIV0_DVS;
277 else if (parent == &clk_h)
278 clkdiv0 |= S3C2443_CLKDIV0_DVS;
282 __raw_writel(clkdiv0, S3C2443_CLKDIV0);
286 static struct clk clk_arm = {
289 .set_parent = s3c2443_setparent_armclk,
294 * this is sourced from either the EPLL or the EPLLref clock
297 static int s3c2443_setparent_esysclk(struct clk *clk, struct clk *parent)
299 unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
301 if (parent == &clk_epll)
302 clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL;
303 else if (parent == &clk_epllref)
304 clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL;
308 __raw_writel(clksrc, S3C2443_CLKSRC);
309 clk->parent = parent;
314 static struct clk clk_esysclk = {
318 .set_parent = s3c2443_setparent_esysclk,
323 * UART baud-rate clock sourced from esysclk via a divisor
326 static unsigned long s3c2443_getrate_uart(struct clk *clk)
328 unsigned long parent_rate = clk_get_rate(clk->parent);
329 unsigned long div = __raw_readl(S3C2443_CLKDIV1);
331 div &= S3C2443_CLKDIV1_UARTDIV_MASK;
332 div >>= S3C2443_CLKDIV1_UARTDIV_SHIFT;
334 return parent_rate / (div + 1);
338 static int s3c2443_setrate_uart(struct clk *clk, unsigned long rate)
340 unsigned long parent_rate = clk_get_rate(clk->parent);
341 unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
343 rate = s3c2443_roundrate_clksrc16(clk, rate);
344 rate = parent_rate / rate;
346 clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
347 clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
349 __raw_writel(clkdivn, S3C2443_CLKDIV1);
353 static struct clk clk_uart = {
356 .parent = &clk_esysclk,
357 .get_rate = s3c2443_getrate_uart,
358 .set_rate = s3c2443_setrate_uart,
359 .round_rate = s3c2443_roundrate_clksrc16,
364 * high-speed spi clock, sourced from esysclk
367 static unsigned long s3c2443_getrate_hsspi(struct clk *clk)
369 unsigned long parent_rate = clk_get_rate(clk->parent);
370 unsigned long div = __raw_readl(S3C2443_CLKDIV1);
372 div &= S3C2443_CLKDIV1_HSSPIDIV_MASK;
373 div >>= S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
375 return parent_rate / (div + 1);
379 static int s3c2443_setrate_hsspi(struct clk *clk, unsigned long rate)
381 unsigned long parent_rate = clk_get_rate(clk->parent);
382 unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
384 rate = s3c2443_roundrate_clksrc4(clk, rate);
385 rate = parent_rate / rate;
387 clkdivn &= ~S3C2443_CLKDIV1_HSSPIDIV_MASK;
388 clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
390 __raw_writel(clkdivn, S3C2443_CLKDIV1);
394 static struct clk clk_hsspi = {
397 .parent = &clk_esysclk,
398 .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
399 .enable = s3c2443_clkcon_enable_s,
400 .get_rate = s3c2443_getrate_hsspi,
401 .set_rate = s3c2443_setrate_hsspi,
402 .round_rate = s3c2443_roundrate_clksrc4,
407 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
410 static unsigned long s3c2443_getrate_usbhost(struct clk *clk)
412 unsigned long parent_rate = clk_get_rate(clk->parent);
413 unsigned long div = __raw_readl(S3C2443_CLKDIV1);
415 div &= S3C2443_CLKDIV1_USBHOSTDIV_MASK;
416 div >>= S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
418 return parent_rate / (div + 1);
421 static int s3c2443_setrate_usbhost(struct clk *clk, unsigned long rate)
423 unsigned long parent_rate = clk_get_rate(clk->parent);
424 unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
426 rate = s3c2443_roundrate_clksrc4(clk, rate);
427 rate = parent_rate / rate;
429 clkdivn &= ~S3C2443_CLKDIV1_USBHOSTDIV_MASK;
430 clkdivn |= (rate - 1) << S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
432 __raw_writel(clkdivn, S3C2443_CLKDIV1);
436 static struct clk clk_usb_bus_host = {
437 .name = "usb-bus-host-parent",
439 .parent = &clk_esysclk,
440 .ctrlbit = S3C2443_SCLKCON_USBHOST,
441 .enable = s3c2443_clkcon_enable_s,
442 .get_rate = s3c2443_getrate_usbhost,
443 .set_rate = s3c2443_setrate_usbhost,
444 .round_rate = s3c2443_roundrate_clksrc4,
449 * this clock is sourced from epll, and is fed through a divider,
450 * to a mux controlled by sclkcon where either it or a extclk can
451 * be fed to the hsmmc block
454 static unsigned long s3c2443_getrate_hsmmc_div(struct clk *clk)
456 unsigned long parent_rate = clk_get_rate(clk->parent);
457 unsigned long div = __raw_readl(S3C2443_CLKDIV1);
459 div &= S3C2443_CLKDIV1_HSMMCDIV_MASK;
460 div >>= S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
462 return parent_rate / (div + 1);
465 static int s3c2443_setrate_hsmmc_div(struct clk *clk, unsigned long rate)
467 unsigned long parent_rate = clk_get_rate(clk->parent);
468 unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
470 rate = s3c2443_roundrate_clksrc4(clk, rate);
471 rate = parent_rate / rate;
473 clkdivn &= ~S3C2443_CLKDIV1_HSMMCDIV_MASK;
474 clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
476 __raw_writel(clkdivn, S3C2443_CLKDIV1);
480 static struct clk clk_hsmmc_div = {
483 .parent = &clk_esysclk,
484 .get_rate = s3c2443_getrate_hsmmc_div,
485 .set_rate = s3c2443_setrate_hsmmc_div,
486 .round_rate = s3c2443_roundrate_clksrc4,
489 static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
491 unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
493 clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
494 S3C2443_SCLKCON_HSMMCCLK_EPLL);
496 if (parent == &clk_epll)
497 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
498 else if (parent == &clk_ext)
499 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
503 if (clk->usage > 0) {
504 __raw_writel(clksrc, S3C2443_SCLKCON);
507 clk->parent = parent;
511 static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
513 return s3c2443_setparent_hsmmc(clk, clk->parent);
516 static struct clk clk_hsmmc = {
519 .parent = &clk_hsmmc_div,
520 .enable = s3c2443_enable_hsmmc,
521 .set_parent = s3c2443_setparent_hsmmc,
526 * this clock is the output from the i2s divisor of esysclk
529 static unsigned long s3c2443_getrate_i2s_eplldiv(struct clk *clk)
531 unsigned long parent_rate = clk_get_rate(clk->parent);
532 unsigned long div = __raw_readl(S3C2443_CLKDIV1);
534 div &= S3C2443_CLKDIV1_I2SDIV_MASK;
535 div >>= S3C2443_CLKDIV1_I2SDIV_SHIFT;
537 return parent_rate / (div + 1);
540 static int s3c2443_setrate_i2s_eplldiv(struct clk *clk, unsigned long rate)
542 unsigned long parent_rate = clk_get_rate(clk->parent);
543 unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
545 rate = s3c2443_roundrate_clksrc16(clk, rate);
546 rate = parent_rate / rate;
548 clkdivn &= ~S3C2443_CLKDIV1_I2SDIV_MASK;
549 clkdivn |= (rate - 1) << S3C2443_CLKDIV1_I2SDIV_SHIFT;
551 __raw_writel(clkdivn, S3C2443_CLKDIV1);
555 static struct clk clk_i2s_eplldiv = {
556 .name = "i2s-eplldiv",
558 .parent = &clk_esysclk,
559 .get_rate = s3c2443_getrate_i2s_eplldiv,
560 .set_rate = s3c2443_setrate_i2s_eplldiv,
561 .round_rate = s3c2443_roundrate_clksrc16,
566 * i2s bus reference clock, selectable from external, esysclk or epllref
569 static int s3c2443_setparent_i2s(struct clk *clk, struct clk *parent)
571 unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
573 clksrc &= ~S3C2443_CLKSRC_I2S_MASK;
575 if (parent == &clk_epllref)
576 clksrc |= S3C2443_CLKSRC_I2S_EPLLREF;
577 else if (parent == &clk_i2s_ext)
578 clksrc |= S3C2443_CLKSRC_I2S_EXT;
579 else if (parent != &clk_i2s_eplldiv)
582 clk->parent = parent;
583 __raw_writel(clksrc, S3C2443_CLKSRC);
588 static struct clk clk_i2s = {
591 .parent = &clk_i2s_eplldiv,
592 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
593 .enable = s3c2443_clkcon_enable_s,
594 .set_parent = s3c2443_setparent_i2s,
599 * camera interface bus-clock, divided down from esysclk
602 static unsigned long s3c2443_getrate_cam(struct clk *clk)
604 unsigned long parent_rate = clk_get_rate(clk->parent);
605 unsigned long div = __raw_readl(S3C2443_CLKDIV1);
607 div &= S3C2443_CLKDIV1_CAMDIV_MASK;
608 div >>= S3C2443_CLKDIV1_CAMDIV_SHIFT;
610 return parent_rate / (div + 1);
613 static int s3c2443_setrate_cam(struct clk *clk, unsigned long rate)
615 unsigned long parent_rate = clk_get_rate(clk->parent);
616 unsigned long clkdiv1 = __raw_readl(S3C2443_CLKDIV1);
618 rate = s3c2443_roundrate_clksrc16(clk, rate);
619 rate = parent_rate / rate;
621 clkdiv1 &= ~S3C2443_CLKDIV1_CAMDIV_MASK;
622 clkdiv1 |= (rate - 1) << S3C2443_CLKDIV1_CAMDIV_SHIFT;
624 __raw_writel(clkdiv1, S3C2443_CLKDIV1);
628 static struct clk clk_cam = {
629 .name = "camif-upll", /* same as 2440 name */
631 .parent = &clk_esysclk,
632 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
633 .enable = s3c2443_clkcon_enable_s,
634 .get_rate = s3c2443_getrate_cam,
635 .set_rate = s3c2443_setrate_cam,
636 .round_rate = s3c2443_roundrate_clksrc16,
641 * display interface clock, divided from esysclk
644 static unsigned long s3c2443_getrate_display(struct clk *clk)
646 unsigned long parent_rate = clk_get_rate(clk->parent);
647 unsigned long div = __raw_readl(S3C2443_CLKDIV1);
649 div &= S3C2443_CLKDIV1_DISPDIV_MASK;
650 div >>= S3C2443_CLKDIV1_DISPDIV_SHIFT;
652 return parent_rate / (div + 1);
655 static int s3c2443_setrate_display(struct clk *clk, unsigned long rate)
657 unsigned long parent_rate = clk_get_rate(clk->parent);
658 unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
660 rate = s3c2443_roundrate_clksrc256(clk, rate);
661 rate = parent_rate / rate;
663 clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
664 clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
666 __raw_writel(clkdivn, S3C2443_CLKDIV1);
670 static struct clk clk_display = {
671 .name = "display-if",
673 .parent = &clk_esysclk,
674 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
675 .enable = s3c2443_clkcon_enable_s,
676 .get_rate = s3c2443_getrate_display,
677 .set_rate = s3c2443_setrate_display,
678 .round_rate = s3c2443_roundrate_clksrc256,
681 /* standard clock definitions */
683 static struct clk init_clocks_disable[] = {
692 .enable = s3c2443_clkcon_enable_p,
693 .ctrlbit = S3C2443_PCLKCON_SDI,
698 .enable = s3c2443_clkcon_enable_p,
699 .ctrlbit = S3C2443_PCLKCON_ADC,
704 .enable = s3c2443_clkcon_enable_p,
705 .ctrlbit = S3C2443_PCLKCON_IIC,
710 .enable = s3c2443_clkcon_enable_p,
711 .ctrlbit = S3C2443_PCLKCON_IIS,
716 .enable = s3c2443_clkcon_enable_p,
717 .ctrlbit = S3C2443_PCLKCON_SPI0,
722 .enable = s3c2443_clkcon_enable_p,
723 .ctrlbit = S3C2443_PCLKCON_SPI1,
727 static struct clk init_clocks[] = {
732 .enable = s3c2443_clkcon_enable_h,
733 .ctrlbit = S3C2443_HCLKCON_DMA0,
738 .enable = s3c2443_clkcon_enable_h,
739 .ctrlbit = S3C2443_HCLKCON_DMA1,
744 .enable = s3c2443_clkcon_enable_h,
745 .ctrlbit = S3C2443_HCLKCON_DMA2,
750 .enable = s3c2443_clkcon_enable_h,
751 .ctrlbit = S3C2443_HCLKCON_DMA3,
756 .enable = s3c2443_clkcon_enable_h,
757 .ctrlbit = S3C2443_HCLKCON_DMA4,
762 .enable = s3c2443_clkcon_enable_h,
763 .ctrlbit = S3C2443_HCLKCON_DMA5,
768 .enable = s3c2443_clkcon_enable_h,
769 .ctrlbit = S3C2443_HCLKCON_LCDC,
774 .enable = s3c2443_clkcon_enable_p,
775 .ctrlbit = S3C2443_PCLKCON_GPIO,
780 .enable = s3c2443_clkcon_enable_h,
781 .ctrlbit = S3C2443_HCLKCON_USBH,
783 .name = "usb-device",
786 .enable = s3c2443_clkcon_enable_h,
787 .ctrlbit = S3C2443_HCLKCON_USBD,
792 .enable = s3c2443_clkcon_enable_h,
793 .ctrlbit = S3C2443_HCLKCON_HSMMC,
798 .enable = s3c2443_clkcon_enable_h,
799 .ctrlbit = S3C2443_HCLKCON_CFC,
804 .enable = s3c2443_clkcon_enable_h,
805 .ctrlbit = S3C2443_HCLKCON_SSMC,
810 .enable = s3c2443_clkcon_enable_p,
811 .ctrlbit = S3C2443_PCLKCON_PWMT,
816 .enable = s3c2443_clkcon_enable_p,
817 .ctrlbit = S3C2443_PCLKCON_UART0,
822 .enable = s3c2443_clkcon_enable_p,
823 .ctrlbit = S3C2443_PCLKCON_UART1,
828 .enable = s3c2443_clkcon_enable_p,
829 .ctrlbit = S3C2443_PCLKCON_UART2,
834 .enable = s3c2443_clkcon_enable_p,
835 .ctrlbit = S3C2443_PCLKCON_UART3,
840 .enable = s3c2443_clkcon_enable_p,
841 .ctrlbit = S3C2443_PCLKCON_RTC,
846 .ctrlbit = S3C2443_PCLKCON_WDT,
848 .name = "usb-bus-host",
850 .parent = &clk_usb_bus_host,
855 .ctrlbit = S3C2443_PCLKCON_AC97,
859 /* clocks to add where we need to check their parentage */
861 /* s3c2443_clk_initparents
863 * Initialise the parents for the clocks that we get at start-time
866 static int __init clk_init_set_parent(struct clk *clk, struct clk *parent)
868 printk(KERN_DEBUG "clock %s: parent %s\n", clk->name, parent->name);
869 return clk_set_parent(clk, parent);
872 static void __init s3c2443_clk_initparents(void)
874 unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
877 switch (clksrc & S3C2443_CLKSRC_EPLLREF_MASK) {
878 case S3C2443_CLKSRC_EPLLREF_EXTCLK:
882 case S3C2443_CLKSRC_EPLLREF_XTAL:
887 case S3C2443_CLKSRC_EPLLREF_MPLLREF:
888 case S3C2443_CLKSRC_EPLLREF_MPLLREF2:
889 parent = &clk_mpllref;
893 clk_init_set_parent(&clk_epllref, parent);
895 switch (clksrc & S3C2443_CLKSRC_I2S_MASK) {
896 case S3C2443_CLKSRC_I2S_EXT:
897 parent = &clk_i2s_ext;
900 case S3C2443_CLKSRC_I2S_EPLLDIV:
902 parent = &clk_i2s_eplldiv;
905 case S3C2443_CLKSRC_I2S_EPLLREF:
906 case S3C2443_CLKSRC_I2S_EPLLREF3:
907 parent = &clk_epllref;
910 clk_init_set_parent(&clk_i2s, &clk_epllref);
914 parent = (clksrc & S3C2443_CLKSRC_ESYSCLK_EPLL) ?
915 &clk_epll : &clk_epllref;
917 clk_init_set_parent(&clk_esysclk, parent);
921 if (clksrc & S3C2443_CLKSRC_MSYSCLK_MPLL) {
924 parent = (clksrc & S3C2443_CLKSRC_EXTCLK_DIV) ?
925 &clk_mdivclk : &clk_mpllref;
928 clk_init_set_parent(&clk_msysclk, parent);
932 if (__raw_readl(S3C2443_CLKDIV0) & S3C2443_CLKDIV0_DVS)
935 parent = &clk_armdiv;
937 clk_init_set_parent(&clk_arm, parent);
940 /* armdiv divisor table */
942 static unsigned int armdiv[16] = {
943 [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
944 [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
945 [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
946 [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
947 [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
948 [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
949 [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
950 [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
953 static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
955 clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
957 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
960 static inline unsigned long s3c2443_get_prediv(unsigned long clkcon0)
962 clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK;
963 clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
968 /* clocks to add straight away */
970 static struct clk *clks[] __initdata = {
991 void __init s3c2443_init_clocks(int xtal)
993 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
994 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
995 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
1004 pll = s3c2443_get_mpll(mpllcon, xtal);
1006 fclk = pll / s3c2443_fclk_div(clkdiv0);
1007 hclk = fclk / s3c2443_get_prediv(clkdiv0);
1008 hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
1009 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
1011 clk_armdiv.rate = fclk;
1013 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
1015 printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
1016 (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
1017 print_mhz(pll), print_mhz(fclk),
1018 print_mhz(hclk), print_mhz(pclk));
1020 s3c2443_clk_initparents();
1022 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
1025 ret = s3c24xx_register_clock(clkp);
1027 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1032 clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
1034 clk_usb_bus.parent = &clk_usb_bus_host;
1036 /* ensure usb bus clock is within correct rate of 48MHz */
1038 if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) {
1039 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
1040 clk_set_rate(&clk_usb_bus_host, 48*1000*1000);
1043 printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
1044 (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
1045 print_mhz(clk_get_rate(&clk_epll)),
1046 print_mhz(clk_get_rate(&clk_usb_bus)));
1048 /* register clocks from clock array */
1051 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
1052 ret = s3c24xx_register_clock(clkp);
1054 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1059 /* We must be careful disabling the clocks we are not intending to
1060 * be using at boot time, as subsystems such as the LCD which do
1061 * their own DMA requests to the bus can cause the system to lockup
1062 * if they where in the middle of requesting bus access.
1064 * Disabling the LCD clock if the LCD is active is very dangerous,
1065 * and therefore the bootloader should be careful to not enable
1066 * the LCD clock if it is not needed.
1069 /* install (and disable) the clocks we do not need immediately */
1071 clkp = init_clocks_disable;
1072 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1074 ret = s3c24xx_register_clock(clkp);
1076 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1080 (clkp->enable)(clkp, 0);