arch/arm/mach-sa1100/cpu-sa1110.c

   1 /*
   2  *  linux/arch/arm/mach-sa1100/cpu-sa1110.c
   3  *
   4  *  Copyright (C) 2001 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Note: there are two erratas that apply to the SA1110 here:
  11  *  7 - SDRAM auto-power-up failure (rev A0)
  12  * 13 - Corruption of internal register reads/writes following
  13  *      SDRAM reads (rev A0, B0, B1)
  14  *
  15  * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
  16  *
  17  * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
  18  */
  19 #include <linux/moduleparam.h>
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/sched.h>
  23 #include <linux/cpufreq.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26
  27 #include <mach/hardware.h>
  28 #include <asm/mach-types.h>
  29 #include <asm/io.h>
  30 #include <asm/system.h>
  31
  32 #include "generic.h"
  33
  34 #undef DEBUG
  35
  36 static struct cpufreq_driver sa1110_driver;
  37
  38 struct sdram_params {
  39         const char name[16];
  40         u_char  rows;           /* bits                          */
  41         u_char  cas_latency;    /* cycles                        */
  42         u_char  tck;            /* clock cycle time (ns)         */
  43         u_char  trcd;           /* activate to r/w (ns)          */
  44         u_char  trp;            /* precharge to activate (ns)    */
  45         u_char  twr;            /* write recovery time (ns)      */
  46         u_short refresh;        /* refresh time for array (us)   */
  47 };
  48
  49 struct sdram_info {
  50         u_int   mdcnfg;
  51         u_int   mdrefr;
  52         u_int   mdcas[3];
  53 };
  54
  55 static struct sdram_params sdram_tbl[] __initdata = {
  56         {       /* Toshiba TC59SM716 CL2 */
  57                 .name           = "TC59SM716-CL2",
  58                 .rows           = 12,
  59                 .tck            = 10,
  60                 .trcd           = 20,
  61                 .trp            = 20,
  62                 .twr            = 10,
  63                 .refresh        = 64000,
  64                 .cas_latency    = 2,
  65         }, {    /* Toshiba TC59SM716 CL3 */
  66                 .name           = "TC59SM716-CL3",
  67                 .rows           = 12,
  68                 .tck            = 8,
  69                 .trcd           = 20,
  70                 .trp            = 20,
  71                 .twr            = 8,
  72                 .refresh        = 64000,
  73                 .cas_latency    = 3,
  74         }, {    /* Samsung K4S641632D TC75 */
  75                 .name           = "K4S641632D",
  76                 .rows           = 14,
  77                 .tck            = 9,
  78                 .trcd           = 27,
  79                 .trp            = 20,
  80                 .twr            = 9,
  81                 .refresh        = 64000,
  82                 .cas_latency    = 3,
  83         }, {    /* Samsung K4S281632B-1H */
  84                 .name           = "K4S281632B-1H",
  85                 .rows           = 12,
  86                 .tck            = 10,
  87                 .trp            = 20,
  88                 .twr            = 10,
  89                 .refresh        = 64000,
  90                 .cas_latency    = 3,
  91         }, {    /* Samsung KM416S4030CT */
  92                 .name           = "KM416S4030CT",
  93                 .rows           = 13,
  94                 .tck            = 8,
  95                 .trcd           = 24,   /* 3 CLKs */
  96                 .trp            = 24,   /* 3 CLKs */
  97                 .twr            = 16,   /* Trdl: 2 CLKs */
  98                 .refresh        = 64000,
  99                 .cas_latency    = 3,
 100         }, {    /* Winbond W982516AH75L CL3 */
 101                 .name           = "W982516AH75L",
 102                 .rows           = 16,
 103                 .tck            = 8,
 104                 .trcd           = 20,
 105                 .trp            = 20,
 106                 .twr            = 8,
 107                 .refresh        = 64000,
 108                 .cas_latency    = 3,
 109         },
 110 };
 111
 112 static struct sdram_params sdram_params;
 113
 114 /*
 115  * Given a period in ns and frequency in khz, calculate the number of
 116  * cycles of frequency in period.  Note that we round up to the next
 117  * cycle, even if we are only slightly over.
 118  */
 119 static inline u_int ns_to_cycles(u_int ns, u_int khz)
 120 {
 121         return (ns * khz + 999999) / 1000000;
 122 }
 123
 124 /*
 125  * Create the MDCAS register bit pattern.
 126  */
 127 static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
 128 {
 129         u_int shift;
 130
 131         rcd = 2 * rcd - 1;
 132         shift = delayed + 1 + rcd;
 133
 134         mdcas[0]  = (1 << rcd) - 1;
 135         mdcas[0] |= 0x55555555 << shift;
 136         mdcas[1]  = mdcas[2] = 0x55555555 << (shift & 1);
 137 }
 138
 139 static void
 140 sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
 141                        struct sdram_params *sdram)
 142 {
 143         u_int mem_khz, sd_khz, trp, twr;
 144
 145         mem_khz = cpu_khz / 2;
 146         sd_khz = mem_khz;
 147
 148         /*
 149          * If SDCLK would invalidate the SDRAM timings,
 150          * run SDCLK at half speed.
 151          *
 152          * CPU steppings prior to B2 must either run the memory at
 153          * half speed or use delayed read latching (errata 13).
 154          */
 155         if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
 156             (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
 157                 sd_khz /= 2;
 158
 159         sd->mdcnfg = MDCNFG & 0x007f007f;
 160
 161         twr = ns_to_cycles(sdram->twr, mem_khz);
 162
 163         /* trp should always be >1 */
 164         trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
 165         if (trp < 1)
 166                 trp = 1;
 167
 168         sd->mdcnfg |= trp << 8;
 169         sd->mdcnfg |= trp << 24;
 170         sd->mdcnfg |= sdram->cas_latency << 12;
 171         sd->mdcnfg |= sdram->cas_latency << 28;
 172         sd->mdcnfg |= twr << 14;
 173         sd->mdcnfg |= twr << 30;
 174
 175         sd->mdrefr = MDREFR & 0xffbffff0;
 176         sd->mdrefr |= 7;
 177
 178         if (sd_khz != mem_khz)
 179                 sd->mdrefr |= MDREFR_K1DB2;
 180
 181         /* initial number of '1's in MDCAS + 1 */
 182         set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
 183
 184 #ifdef DEBUG
 185         printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
 186                 sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]);
 187 #endif
 188 }
 189
 190 /*
 191  * Set the SDRAM refresh rate.
 192  */
 193 static inline void sdram_set_refresh(u_int dri)
 194 {
 195         MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
 196         (void) MDREFR;
 197 }
 198
 199 /*
 200  * Update the refresh period.  We do this such that we always refresh
 201  * the SDRAMs within their permissible period.  The refresh period is
 202  * always a multiple of the memory clock (fixed at cpu_clock / 2).
 203  *
 204  * FIXME: we don't currently take account of burst accesses here,
 205  * but neither do Intels DM nor Angel.
 206  */
 207 static void
 208 sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
 209 {
 210         u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
 211         u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
 212
 213 #ifdef DEBUG
 214         mdelay(250);
 215         printk("new dri value = %d\n", dri);
 216 #endif
 217
 218         sdram_set_refresh(dri);
 219 }
 220
 221 /*
 222  * Ok, set the CPU frequency.
 223  */
 224 static int sa1110_target(struct cpufreq_policy *policy,
 225                          unsigned int target_freq,
 226                          unsigned int relation)
 227 {
 228         struct sdram_params *sdram = &sdram_params;
 229         struct cpufreq_freqs freqs;
 230         struct sdram_info sd;
 231         unsigned long flags;
 232         unsigned int ppcr, unused;
 233
 234         switch(relation){
 235         case CPUFREQ_RELATION_L:
 236                 ppcr = sa11x0_freq_to_ppcr(target_freq);
 237                 if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
 238                         ppcr--;
 239                 break;
 240         case CPUFREQ_RELATION_H:
 241                 ppcr = sa11x0_freq_to_ppcr(target_freq);
 242                 if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&
 243                     (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))
 244                         ppcr--;
 245                 break;
 246         default:
 247                 return -EINVAL;
 248         }
 249
 250         freqs.old = sa11x0_getspeed(0);
 251         freqs.new = sa11x0_ppcr_to_freq(ppcr);
 252         freqs.cpu = 0;
 253
 254         sdram_calculate_timing(&sd, freqs.new, sdram);
 255
 256 #if 0
 257         /*
 258          * These values are wrong according to the SA1110 documentation
 259          * and errata, but they seem to work.  Need to get a storage
 260          * scope on to the SDRAM signals to work out why.
 261          */
 262         if (policy->max < 147500) {
 263                 sd.mdrefr |= MDREFR_K1DB2;
 264                 sd.mdcas[0] = 0xaaaaaa7f;
 265         } else {
 266                 sd.mdrefr &= ~MDREFR_K1DB2;
 267                 sd.mdcas[0] = 0xaaaaaa9f;
 268         }
 269         sd.mdcas[1] = 0xaaaaaaaa;
 270         sd.mdcas[2] = 0xaaaaaaaa;
 271 #endif
 272
 273         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 274
 275         /*
 276          * The clock could be going away for some time.  Set the SDRAMs
 277          * to refresh rapidly (every 64 memory clock cycles).  To get
 278          * through the whole array, we need to wait 262144 mclk cycles.
 279          * We wait 20ms to be safe.
 280          */
 281         sdram_set_refresh(2);
 282         if (!irqs_disabled()) {
 283                 msleep(20);
 284         } else {
 285                 mdelay(20);
 286         }
 287
 288         /*
 289          * Reprogram the DRAM timings with interrupts disabled, and
 290          * ensure that we are doing this within a complete cache line.
 291          * This means that we won't access SDRAM for the duration of
 292          * the programming.
 293          */
 294         local_irq_save(flags);
 295         asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 296         udelay(10);
 297         __asm__ __volatile__("                                  \n\
 298                 b       2f                                      \n\
 299                 .align  5                                       \n\
 300 1:              str     %3, [%1, #0]            @ MDCNFG        \n\
 301                 str     %4, [%1, #28]           @ MDREFR        \n\
 302                 str     %5, [%1, #4]            @ MDCAS0        \n\
 303                 str     %6, [%1, #8]            @ MDCAS1        \n\
 304                 str     %7, [%1, #12]           @ MDCAS2        \n\
 305                 str     %8, [%2, #0]            @ PPCR          \n\
 306                 ldr     %0, [%1, #0]                            \n\
 307                 b       3f                                      \n\
 308 2:              b       1b                                      \n\
 309 3:              nop                                             \n\
 310                 nop"
 311                 : "=&r" (unused)
 312                 : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
 313                   "r" (sd.mdrefr), "r" (sd.mdcas[0]),
 314                   "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
 315         local_irq_restore(flags);
 316
 317         /*
 318          * Now, return the SDRAM refresh back to normal.
 319          */
 320         sdram_update_refresh(freqs.new, sdram);
 321
 322         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 323
 324         return 0;
 325 }
 326
 327 static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
 328 {
 329         if (policy->cpu != 0)
 330                 return -EINVAL;
 331         policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
 332         policy->cpuinfo.min_freq = 59000;
 333         policy->cpuinfo.max_freq = 287000;
 334         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
 335         return 0;
 336 }
 337
 338 static struct cpufreq_driver sa1110_driver = {
 339         .flags          = CPUFREQ_STICKY,
 340         .verify         = sa11x0_verify_speed,
 341         .target         = sa1110_target,
 342         .get            = sa11x0_getspeed,
 343         .init           = sa1110_cpu_init,
 344         .name           = "sa1110",
 345 };
 346
 347 static struct sdram_params *sa1110_find_sdram(const char *name)
 348 {
 349         struct sdram_params *sdram;
 350
 351         for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
 352                 if (strcmp(name, sdram->name) == 0)
 353                         return sdram;
 354
 355         return NULL;
 356 }
 357
 358 static char sdram_name[16];
 359
 360 static int __init sa1110_clk_init(void)
 361 {
 362         struct sdram_params *sdram;
 363         const char *name = sdram_name;
 364
 365         if (!name[0]) {
 366                 if (machine_is_assabet())
 367                         name = "TC59SM716-CL3";
 368
 369                 if (machine_is_pt_system3())
 370                         name = "K4S641632D";
 371
 372                 if (machine_is_h3100())
 373                         name = "KM416S4030CT";
 374                 if (machine_is_jornada720())
 375                         name = "K4S281632B-1H";
 376         }
 377
 378         sdram = sa1110_find_sdram(name);
 379         if (sdram) {
 380                 printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
 381                         " twr: %d refresh: %d cas_latency: %d\n",
 382                         sdram->tck, sdram->trcd, sdram->trp,
 383                         sdram->twr, sdram->refresh, sdram->cas_latency);
 384
 385                 memcpy(&sdram_params, sdram, sizeof(sdram_params));
 386
 387                 return cpufreq_register_driver(&sa1110_driver);
 388         }
 389
 390         return 0;
 391 }
 392
 393 module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
 394 arch_initcall(sa1110_clk_init);