2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
18 #include <asm/mach-types.h>
19 #include <asm/setup.h>
20 #include <asm/sizes.h>
23 #include <asm/mach/arch.h>
24 #include <asm/mach/map.h>
28 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
30 extern void _stext, _etext, __data_start, _end;
31 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
34 * empty_zero_page is a special page that is used for
35 * zero-initialized data and COW.
37 struct page *empty_zero_page;
40 * The pmd table for the upper-most set of pages.
44 #define CPOLICY_UNCACHED 0
45 #define CPOLICY_BUFFERED 1
46 #define CPOLICY_WRITETHROUGH 2
47 #define CPOLICY_WRITEBACK 3
48 #define CPOLICY_WRITEALLOC 4
50 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
51 static unsigned int ecc_mask __initdata = 0;
53 pgprot_t pgprot_kernel;
55 EXPORT_SYMBOL(pgprot_user);
56 EXPORT_SYMBOL(pgprot_kernel);
59 const char policy[16];
65 static struct cachepolicy cache_policies[] __initdata = {
69 .pmd = PMD_SECT_UNCACHED,
74 .pmd = PMD_SECT_BUFFERED,
75 .pte = PTE_BUFFERABLE,
77 .policy = "writethrough",
82 .policy = "writeback",
85 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
87 .policy = "writealloc",
90 .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
95 * These are useful for identifing cache coherency
96 * problems by allowing the cache or the cache and
97 * writebuffer to be turned off. (Note: the write
98 * buffer should not be on and the cache off).
100 static void __init early_cachepolicy(char **p)
104 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
105 int len = strlen(cache_policies[i].policy);
107 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
109 cr_alignment &= ~cache_policies[i].cr_mask;
110 cr_no_alignment &= ~cache_policies[i].cr_mask;
115 if (i == ARRAY_SIZE(cache_policies))
116 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
118 set_cr(cr_alignment);
120 __early_param("cachepolicy=", early_cachepolicy);
122 static void __init early_nocache(char **__unused)
124 char *p = "buffered";
125 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
126 early_cachepolicy(&p);
128 __early_param("nocache", early_nocache);
130 static void __init early_nowrite(char **__unused)
132 char *p = "uncached";
133 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
134 early_cachepolicy(&p);
136 __early_param("nowb", early_nowrite);
138 static void __init early_ecc(char **p)
140 if (memcmp(*p, "on", 2) == 0) {
141 ecc_mask = PMD_PROTECTION;
143 } else if (memcmp(*p, "off", 3) == 0) {
148 __early_param("ecc=", early_ecc);
150 static int __init noalign_setup(char *__unused)
152 cr_alignment &= ~CR_A;
153 cr_no_alignment &= ~CR_A;
154 set_cr(cr_alignment);
157 __setup("noalign", noalign_setup);
160 void adjust_cr(unsigned long mask, unsigned long set)
168 local_irq_save(flags);
170 cr_no_alignment = (cr_no_alignment & ~mask) | set;
171 cr_alignment = (cr_alignment & ~mask) | set;
173 set_cr((get_cr() & ~mask) | set);
175 local_irq_restore(flags);
180 unsigned int prot_pte;
181 unsigned int prot_l1;
182 unsigned int prot_sect;
186 static struct mem_type mem_types[] __initdata = {
188 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
190 .prot_l1 = PMD_TYPE_TABLE,
191 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
196 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
197 .domain = DOMAIN_KERNEL,
200 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
201 .domain = DOMAIN_KERNEL,
204 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
206 .prot_l1 = PMD_TYPE_TABLE,
207 .domain = DOMAIN_USER,
209 [MT_HIGH_VECTORS] = {
210 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
211 L_PTE_USER | L_PTE_EXEC,
212 .prot_l1 = PMD_TYPE_TABLE,
213 .domain = DOMAIN_USER,
216 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
217 .domain = DOMAIN_KERNEL,
220 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
221 .domain = DOMAIN_KERNEL,
223 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
224 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
226 .prot_l1 = PMD_TYPE_TABLE,
227 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
228 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
232 [MT_NONSHARED_DEVICE] = {
233 .prot_l1 = PMD_TYPE_TABLE,
234 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
241 * Adjust the PMD section entries according to the CPU in use.
243 static void __init build_mem_type_table(void)
245 struct cachepolicy *cp;
246 unsigned int cr = get_cr();
247 unsigned int user_pgprot, kern_pgprot;
248 int cpu_arch = cpu_architecture();
251 #if defined(CONFIG_CPU_DCACHE_DISABLE)
252 if (cachepolicy > CPOLICY_BUFFERED)
253 cachepolicy = CPOLICY_BUFFERED;
254 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
255 if (cachepolicy > CPOLICY_WRITETHROUGH)
256 cachepolicy = CPOLICY_WRITETHROUGH;
258 if (cpu_arch < CPU_ARCH_ARMv5) {
259 if (cachepolicy >= CPOLICY_WRITEALLOC)
260 cachepolicy = CPOLICY_WRITEBACK;
265 * Xscale must not have PMD bit 4 set for section mappings.
268 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
269 mem_types[i].prot_sect &= ~PMD_BIT4;
272 * ARMv5 and lower, excluding Xscale, bit 4 must be set for
275 if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
276 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
277 if (mem_types[i].prot_l1)
278 mem_types[i].prot_l1 |= PMD_BIT4;
280 cp = &cache_policies[cachepolicy];
281 kern_pgprot = user_pgprot = cp->pte;
284 * Enable CPU-specific coherency if supported.
285 * (Only available on XSC3 at the moment.)
287 if (arch_is_coherent()) {
289 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
290 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
295 * ARMv6 and above have extended page tables.
297 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
299 * bit 4 becomes XN which we must clear for the
300 * kernel memory mapping.
302 mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
303 mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
306 * Mark cache clean areas and XIP ROM read only
307 * from SVC mode and no access from userspace.
309 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
310 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
311 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
314 * Mark the device area as "shared device"
316 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
317 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
321 * Mark memory with the "shared" attribute for SMP systems
323 user_pgprot |= L_PTE_SHARED;
324 kern_pgprot |= L_PTE_SHARED;
325 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
329 for (i = 0; i < 16; i++) {
330 unsigned long v = pgprot_val(protection_map[i]);
331 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
332 protection_map[i] = __pgprot(v);
335 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
336 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
338 if (cpu_arch >= CPU_ARCH_ARMv5) {
341 * Only use write-through for non-SMP systems
343 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
344 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
347 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
350 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
351 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
352 L_PTE_DIRTY | L_PTE_WRITE |
353 L_PTE_EXEC | kern_pgprot);
355 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
356 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
357 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
358 mem_types[MT_ROM].prot_sect |= cp->pmd;
362 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
366 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
369 printk("Memory policy: ECC %sabled, Data cache %s\n",
370 ecc_mask ? "en" : "dis", cp->policy);
372 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
373 struct mem_type *t = &mem_types[i];
375 t->prot_l1 |= PMD_DOMAIN(t->domain);
377 t->prot_sect |= PMD_DOMAIN(t->domain);
381 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
384 * Create a SECTION PGD between VIRT and PHYS in domain
385 * DOMAIN with protection PROT. This operates on half-
386 * pgdir entry increments.
389 alloc_init_section(unsigned long virt, unsigned long phys, int prot)
391 pmd_t *pmdp = pmd_off_k(virt);
393 if (virt & (1 << 20))
396 *pmdp = __pmd(phys | prot);
397 flush_pmd_entry(pmdp);
401 * Add a PAGE mapping between VIRT and PHYS in domain
402 * DOMAIN with protection PROT. Note that due to the
403 * way we map the PTEs, we must allocate two PTE_SIZE'd
404 * blocks - one for the Linux pte table, and one for
405 * the hardware pte table.
408 alloc_init_page(unsigned long virt, unsigned long phys, const struct mem_type *type)
410 pmd_t *pmdp = pmd_off_k(virt);
413 if (pmd_none(*pmdp)) {
414 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
417 __pmd_populate(pmdp, __pa(ptep) | type->prot_l1);
419 ptep = pte_offset_kernel(pmdp, virt);
421 set_pte_ext(ptep, pfn_pte(phys >> PAGE_SHIFT, __pgprot(type->prot_pte)), 0);
424 static void __init create_36bit_mapping(struct map_desc *md,
425 const struct mem_type *type)
427 unsigned long phys, addr, length, end;
431 phys = (unsigned long)__pfn_to_phys(md->pfn);
432 length = PAGE_ALIGN(md->length);
434 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
435 printk(KERN_ERR "MM: CPU does not support supersection "
436 "mapping for 0x%08llx at 0x%08lx\n",
437 __pfn_to_phys((u64)md->pfn), addr);
441 /* N.B. ARMv6 supersections are only defined to work with domain 0.
442 * Since domain assignments can in fact be arbitrary, the
443 * 'domain == 0' check below is required to insure that ARMv6
444 * supersections are only allocated for domain 0 regardless
445 * of the actual domain assignments in use.
448 printk(KERN_ERR "MM: invalid domain in supersection "
449 "mapping for 0x%08llx at 0x%08lx\n",
450 __pfn_to_phys((u64)md->pfn), addr);
454 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
455 printk(KERN_ERR "MM: cannot create mapping for "
456 "0x%08llx at 0x%08lx invalid alignment\n",
457 __pfn_to_phys((u64)md->pfn), addr);
462 * Shift bits [35:32] of address into bits [23:20] of PMD
465 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
467 pgd = pgd_offset_k(addr);
470 pmd_t *pmd = pmd_offset(pgd, addr);
473 for (i = 0; i < 16; i++)
474 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
476 addr += SUPERSECTION_SIZE;
477 phys += SUPERSECTION_SIZE;
478 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
479 } while (addr != end);
483 * Create the page directory entries and any necessary
484 * page tables for the mapping specified by `md'. We
485 * are able to cope here with varying sizes and address
486 * offsets, and we take full advantage of sections and
489 void __init create_mapping(struct map_desc *md)
491 unsigned long virt, length;
492 unsigned long off = (u32)__pfn_to_phys(md->pfn);
493 const struct mem_type *type;
495 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
496 printk(KERN_WARNING "BUG: not creating mapping for "
497 "0x%08llx at 0x%08lx in user region\n",
498 __pfn_to_phys((u64)md->pfn), md->virtual);
502 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
503 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
504 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
505 "overlaps vmalloc space\n",
506 __pfn_to_phys((u64)md->pfn), md->virtual);
509 type = &mem_types[md->type];
512 * Catch 36-bit addresses
514 if (md->pfn >= 0x100000) {
515 create_36bit_mapping(md, type);
523 if (type->prot_l1 == 0 &&
524 (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
525 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
526 "be mapped using pages, ignoring.\n",
527 __pfn_to_phys(md->pfn), md->virtual);
531 while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
532 alloc_init_page(virt, virt + off, type);
539 * A section mapping covers half a "pgdir" entry.
541 while (length >= (PGDIR_SIZE / 2)) {
542 alloc_init_section(virt, virt + off, type->prot_sect);
544 virt += (PGDIR_SIZE / 2);
545 length -= (PGDIR_SIZE / 2);
548 while (length >= PAGE_SIZE) {
549 alloc_init_page(virt, virt + off, type);
557 * Create the architecture specific mappings
559 void __init iotable_init(struct map_desc *io_desc, int nr)
563 for (i = 0; i < nr; i++)
564 create_mapping(io_desc + i);
567 static inline void prepare_page_table(struct meminfo *mi)
572 * Clear out all the mappings below the kernel image.
574 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
575 pmd_clear(pmd_off_k(addr));
577 #ifdef CONFIG_XIP_KERNEL
578 /* The XIP kernel is mapped in the module area -- skip over it */
579 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
581 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
582 pmd_clear(pmd_off_k(addr));
585 * Clear out all the kernel space mappings, except for the first
586 * memory bank, up to the end of the vmalloc region.
588 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
589 addr < VMALLOC_END; addr += PGDIR_SIZE)
590 pmd_clear(pmd_off_k(addr));
594 * Reserve the various regions of node 0
596 void __init reserve_node_zero(pg_data_t *pgdat)
598 unsigned long res_size = 0;
601 * Register the kernel text and data with bootmem.
602 * Note that this can only be in node 0.
604 #ifdef CONFIG_XIP_KERNEL
605 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start);
607 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext);
611 * Reserve the page tables. These are already in use,
612 * and can only be in node 0.
614 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
615 PTRS_PER_PGD * sizeof(pgd_t));
618 * Hmm... This should go elsewhere, but we really really need to
619 * stop things allocating the low memory; ideally we need a better
620 * implementation of GFP_DMA which does not assume that DMA-able
621 * memory starts at zero.
623 if (machine_is_integrator() || machine_is_cintegrator())
624 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
627 * These should likewise go elsewhere. They pre-reserve the
628 * screen memory region at the start of main system memory.
630 if (machine_is_edb7211())
631 res_size = 0x00020000;
632 if (machine_is_p720t())
633 res_size = 0x00014000;
635 /* H1940 and RX3715 need to reserve this for suspend */
637 if (machine_is_h1940() || machine_is_rx3715()) {
638 reserve_bootmem_node(pgdat, 0x30003000, 0x1000);
639 reserve_bootmem_node(pgdat, 0x30081000, 0x1000);
644 * Because of the SA1111 DMA bug, we want to preserve our
645 * precious DMA-able memory...
647 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
650 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size);
654 * Set up device the mappings. Since we clear out the page tables for all
655 * mappings above VMALLOC_END, we will remove any debug device mappings.
656 * This means you have to be careful how you debug this function, or any
657 * called function. This means you can't use any function or debugging
658 * method which may touch any device, otherwise the kernel _will_ crash.
660 static void __init devicemaps_init(struct machine_desc *mdesc)
667 * Allocate the vector page early.
669 vectors = alloc_bootmem_low_pages(PAGE_SIZE);
672 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
673 pmd_clear(pmd_off_k(addr));
676 * Map the kernel if it is XIP.
677 * It is always first in the modulearea.
679 #ifdef CONFIG_XIP_KERNEL
680 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
681 map.virtual = MODULE_START;
682 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
684 create_mapping(&map);
688 * Map the cache flushing regions.
691 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
692 map.virtual = FLUSH_BASE;
694 map.type = MT_CACHECLEAN;
695 create_mapping(&map);
697 #ifdef FLUSH_BASE_MINICACHE
698 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
699 map.virtual = FLUSH_BASE_MINICACHE;
701 map.type = MT_MINICLEAN;
702 create_mapping(&map);
706 * Create a mapping for the machine vectors at the high-vectors
707 * location (0xffff0000). If we aren't using high-vectors, also
708 * create a mapping at the low-vectors virtual address.
710 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
711 map.virtual = 0xffff0000;
712 map.length = PAGE_SIZE;
713 map.type = MT_HIGH_VECTORS;
714 create_mapping(&map);
716 if (!vectors_high()) {
718 map.type = MT_LOW_VECTORS;
719 create_mapping(&map);
723 * Ask the machine support to map in the statically mapped devices.
729 * Finally flush the caches and tlb to ensure that we're in a
730 * consistent state wrt the writebuffer. This also ensures that
731 * any write-allocated cache lines in the vector page are written
732 * back. After this point, we can start to touch devices again.
734 local_flush_tlb_all();
739 * paging_init() sets up the page tables, initialises the zone memory
740 * maps, and sets up the zero page, bad page and bad page tables.
742 void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
746 build_mem_type_table();
747 prepare_page_table(mi);
749 devicemaps_init(mdesc);
751 top_pmd = pmd_off_k(0xffff0000);
754 * allocate the zero page. Note that we count on this going ok.
756 zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
757 memzero(zero_page, PAGE_SIZE);
758 empty_zero_page = virt_to_page(zero_page);
759 flush_dcache_page(empty_zero_page);
763 * In order to soft-boot, we need to insert a 1:1 mapping in place of
764 * the user-mode pages. This will then ensure that we have predictable
765 * results when turning the mmu off
767 void setup_mm_for_reboot(char mode)
769 unsigned long base_pmdval;
773 if (current->mm && current->mm->pgd)
774 pgd = current->mm->pgd;
778 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
779 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
780 base_pmdval |= PMD_BIT4;
782 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
783 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
786 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
787 pmd[0] = __pmd(pmdval);
788 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
789 flush_pmd_entry(pmd);