2 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
4 * Heavily based on proc-arm926.S
5 * Maintainer: Assaf Hoffman <hoffman@marvell.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/linkage.h>
23 #include <linux/init.h>
24 #include <asm/assembler.h>
26 #include <asm/pgtable-hwdef.h>
27 #include <asm/pgtable.h>
29 #include <asm/ptrace.h>
30 #include "proc-macros.S"
33 * This is the maximum size of an area which will be invalidated
34 * using the single invalidate entry instructions. Anything larger
35 * than this, and we go for the whole cache.
37 * This value should be chosen such that we choose the cheapest
40 #define CACHE_DLIMIT 16384
43 * the cache line size of the I and D cache
45 #define CACHE_DLINESIZE 32
54 .word __cache_params_loc
57 * cpu_feroceon_proc_init()
59 ENTRY(cpu_feroceon_proc_init)
60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
61 ldr r1, __cache_params
63 tst r0, #(1 << 16) @ get way
64 mov r0, r0, lsr #18 @ get cache size order
65 movne r3, #((4 - 1) << 30) @ 4-way
68 mov r2, r2, lsl r0 @ actual cache size
69 movne r2, r2, lsr #2 @ turned into # of sets
75 * cpu_feroceon_proc_fin()
77 ENTRY(cpu_feroceon_proc_fin)
79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
81 bl feroceon_flush_kern_cache_all
83 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
84 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
86 mcr p15, 1, r0, c15, c9, 0 @ clean L2
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
90 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
91 bic r0, r0, #0x1000 @ ...i............
92 bic r0, r0, #0x000e @ ............wca.
93 mcr p15, 0, r0, c1, c0, 0 @ disable caches
97 * cpu_feroceon_reset(loc)
99 * Perform a soft reset of the system. Put the CPU into the
100 * same state as it would be if it had been reset, and branch
101 * to what would be the reset vector.
103 * loc: location to jump to for soft reset
106 ENTRY(cpu_feroceon_reset)
108 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
109 mcr p15, 0, ip, c7, c10, 4 @ drain WB
111 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
114 bic ip, ip, #0x000f @ ............wcam
115 bic ip, ip, #0x1100 @ ...i...s........
116 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
120 * cpu_feroceon_do_idle()
122 * Called with IRQs disabled
125 ENTRY(cpu_feroceon_do_idle)
127 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
128 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
132 * flush_user_cache_all()
134 * Clean and invalidate all cache entries in a particular
138 ENTRY(feroceon_flush_user_cache_all)
142 * flush_kern_cache_all()
144 * Clean and invalidate the entire cache.
146 ENTRY(feroceon_flush_kern_cache_all)
150 ldr r1, __cache_params
153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
154 subs ip, ip, #(1 << 30) @ next way
156 subs r1, r1, #(1 << 5) @ next set
161 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
162 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
166 * flush_user_cache_range(start, end, flags)
168 * Clean and invalidate a range of cache entries in the
169 * specified address range.
171 * - start - start address (inclusive)
172 * - end - end address (exclusive)
173 * - flags - vm_flags describing address space
176 ENTRY(feroceon_flush_user_cache_range)
177 sub r3, r1, r0 @ calculate total size
178 cmp r3, #CACHE_DLIMIT
179 bgt __flush_whole_cache
181 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
182 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
183 add r0, r0, #CACHE_DLINESIZE
184 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
185 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
186 add r0, r0, #CACHE_DLINESIZE
191 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
195 * coherent_kern_range(start, end)
197 * Ensure coherency between the Icache and the Dcache in the
198 * region described by start, end. If you have non-snooping
199 * Harvard caches, you need to implement this function.
201 * - start - virtual start address
202 * - end - virtual end address
205 ENTRY(feroceon_coherent_kern_range)
209 * coherent_user_range(start, end)
211 * Ensure coherency between the Icache and the Dcache in the
212 * region described by start, end. If you have non-snooping
213 * Harvard caches, you need to implement this function.
215 * - start - virtual start address
216 * - end - virtual end address
218 ENTRY(feroceon_coherent_user_range)
219 bic r0, r0, #CACHE_DLINESIZE - 1
220 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
222 add r0, r0, #CACHE_DLINESIZE
225 mcr p15, 0, r0, c7, c10, 4 @ drain WB
229 * flush_kern_dcache_page(void *page)
231 * Ensure no D cache aliasing occurs, either with itself or
234 * - addr - page aligned address
237 ENTRY(feroceon_flush_kern_dcache_page)
239 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
240 add r0, r0, #CACHE_DLINESIZE
244 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
245 mcr p15, 0, r0, c7, c10, 4 @ drain WB
249 ENTRY(feroceon_range_flush_kern_dcache_page)
251 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
252 orr r3, r2, #PSR_I_BIT
253 msr cpsr_c, r3 @ disable interrupts
254 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
255 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
256 msr cpsr_c, r2 @ restore interrupts
258 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
259 mcr p15, 0, r0, c7, c10, 4 @ drain WB
263 * dma_inv_range(start, end)
265 * Invalidate (discard) the specified virtual address range.
266 * May not write back any entries. If 'start' or 'end'
267 * are not cache line aligned, those lines must be written
270 * - start - virtual start address
271 * - end - virtual end address
276 ENTRY(feroceon_dma_inv_range)
277 tst r0, #CACHE_DLINESIZE - 1
278 bic r0, r0, #CACHE_DLINESIZE - 1
279 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
280 tst r1, #CACHE_DLINESIZE - 1
281 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
282 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
283 add r0, r0, #CACHE_DLINESIZE
286 mcr p15, 0, r0, c7, c10, 4 @ drain WB
290 ENTRY(feroceon_range_dma_inv_range)
292 tst r0, #CACHE_DLINESIZE - 1
293 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
294 tst r1, #CACHE_DLINESIZE - 1
295 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
297 subne r1, r1, #1 @ top address is inclusive
298 orr r3, r2, #PSR_I_BIT
299 msr cpsr_c, r3 @ disable interrupts
300 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
301 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
302 msr cpsr_c, r2 @ restore interrupts
306 * dma_clean_range(start, end)
308 * Clean the specified virtual address range.
310 * - start - virtual start address
311 * - end - virtual end address
316 ENTRY(feroceon_dma_clean_range)
317 bic r0, r0, #CACHE_DLINESIZE - 1
318 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
319 add r0, r0, #CACHE_DLINESIZE
322 mcr p15, 0, r0, c7, c10, 4 @ drain WB
326 ENTRY(feroceon_range_dma_clean_range)
329 subne r1, r1, #1 @ top address is inclusive
330 orr r3, r2, #PSR_I_BIT
331 msr cpsr_c, r3 @ disable interrupts
332 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
333 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
334 msr cpsr_c, r2 @ restore interrupts
335 mcr p15, 0, r0, c7, c10, 4 @ drain WB
339 * dma_flush_range(start, end)
341 * Clean and invalidate the specified virtual address range.
343 * - start - virtual start address
344 * - end - virtual end address
347 ENTRY(feroceon_dma_flush_range)
348 bic r0, r0, #CACHE_DLINESIZE - 1
349 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
350 add r0, r0, #CACHE_DLINESIZE
353 mcr p15, 0, r0, c7, c10, 4 @ drain WB
357 ENTRY(feroceon_range_dma_flush_range)
360 subne r1, r1, #1 @ top address is inclusive
361 orr r3, r2, #PSR_I_BIT
362 msr cpsr_c, r3 @ disable interrupts
363 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
364 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
365 msr cpsr_c, r2 @ restore interrupts
366 mcr p15, 0, r0, c7, c10, 4 @ drain WB
369 ENTRY(feroceon_cache_fns)
370 .long feroceon_flush_kern_cache_all
371 .long feroceon_flush_user_cache_all
372 .long feroceon_flush_user_cache_range
373 .long feroceon_coherent_kern_range
374 .long feroceon_coherent_user_range
375 .long feroceon_flush_kern_dcache_page
376 .long feroceon_dma_inv_range
377 .long feroceon_dma_clean_range
378 .long feroceon_dma_flush_range
380 ENTRY(feroceon_range_cache_fns)
381 .long feroceon_flush_kern_cache_all
382 .long feroceon_flush_user_cache_all
383 .long feroceon_flush_user_cache_range
384 .long feroceon_coherent_kern_range
385 .long feroceon_coherent_user_range
386 .long feroceon_range_flush_kern_dcache_page
387 .long feroceon_range_dma_inv_range
388 .long feroceon_range_dma_clean_range
389 .long feroceon_range_dma_flush_range
392 ENTRY(cpu_feroceon_dcache_clean_area)
393 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
394 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
398 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
399 add r0, r0, #CACHE_DLINESIZE
400 subs r1, r1, #CACHE_DLINESIZE
402 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
403 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
404 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
405 add r2, r2, #CACHE_DLINESIZE
406 subs r3, r3, #CACHE_DLINESIZE
409 mcr p15, 0, r0, c7, c10, 4 @ drain WB
412 /* =============================== PageTable ============================== */
415 * cpu_feroceon_switch_mm(pgd)
417 * Set the translation base pointer to be as described by pgd.
419 * pgd: new page tables
422 ENTRY(cpu_feroceon_switch_mm)
425 * Note: we wish to call __flush_whole_cache but we need to preserve
426 * lr to do so. The only way without touching main memory is to
427 * use r2 which is normally used to test the VM_EXEC flag, and
428 * compensate locally for the skipped ops if it is not set.
430 mov r2, lr @ abuse r2 to preserve lr
431 bl __flush_whole_cache
432 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
434 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
435 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
437 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
438 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
445 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
447 * Set a PTE and flush it out
450 ENTRY(cpu_feroceon_set_pte_ext)
452 str r1, [r0], #-2048 @ linux version
454 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
456 bic r2, r1, #PTE_SMALL_AP_MASK
457 bic r2, r2, #PTE_TYPE_MASK
458 orr r2, r2, #PTE_TYPE_SMALL
460 tst r1, #L_PTE_USER @ User?
461 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
463 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
464 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
466 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
469 str r2, [r0] @ hardware version
471 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
472 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
473 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
474 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
476 mcr p15, 0, r0, c7, c10, 4 @ drain WB
482 .type __feroceon_setup, #function
485 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
486 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
488 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
491 adr r5, feroceon_crval
493 mrc p15, 0, r0, c1, c0 @ get control register v4
497 .size __feroceon_setup, . - __feroceon_setup
502 * .RVI UFRS BLDP WCAM
503 * .011 .001 ..11 0101
506 .type feroceon_crval, #object
508 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
513 * Purpose : Function pointers used to access above functions - all calls
516 .type feroceon_processor_functions, #object
517 feroceon_processor_functions:
518 .word v5t_early_abort
520 .word cpu_feroceon_proc_init
521 .word cpu_feroceon_proc_fin
522 .word cpu_feroceon_reset
523 .word cpu_feroceon_do_idle
524 .word cpu_feroceon_dcache_clean_area
525 .word cpu_feroceon_switch_mm
526 .word cpu_feroceon_set_pte_ext
527 .size feroceon_processor_functions, . - feroceon_processor_functions
531 .type cpu_arch_name, #object
534 .size cpu_arch_name, . - cpu_arch_name
536 .type cpu_elf_name, #object
539 .size cpu_elf_name, . - cpu_elf_name
541 .type cpu_feroceon_name, #object
544 .size cpu_feroceon_name, . - cpu_feroceon_name
546 .type cpu_88fr531_name, #object
548 .asciz "Feroceon 88FR531-vd"
549 .size cpu_88fr531_name, . - cpu_88fr531_name
551 .type cpu_88fr571_name, #object
553 .asciz "Feroceon 88FR571-vd"
554 .size cpu_88fr571_name, . - cpu_88fr571_name
556 .type cpu_88fr131_name, #object
558 .asciz "Feroceon 88FR131"
559 .size cpu_88fr131_name, . - cpu_88fr131_name
563 .section ".proc.info.init", #alloc, #execinstr
565 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
566 .type __feroceon_old_id_proc_info,#object
567 __feroceon_old_id_proc_info:
570 .long PMD_TYPE_SECT | \
571 PMD_SECT_BUFFERABLE | \
572 PMD_SECT_CACHEABLE | \
574 PMD_SECT_AP_WRITE | \
576 .long PMD_TYPE_SECT | \
578 PMD_SECT_AP_WRITE | \
583 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
584 .long cpu_feroceon_name
585 .long feroceon_processor_functions
587 .long feroceon_user_fns
588 .long feroceon_cache_fns
589 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
592 .type __88fr531_proc_info,#object
596 .long PMD_TYPE_SECT | \
597 PMD_SECT_BUFFERABLE | \
598 PMD_SECT_CACHEABLE | \
600 PMD_SECT_AP_WRITE | \
602 .long PMD_TYPE_SECT | \
604 PMD_SECT_AP_WRITE | \
609 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
610 .long cpu_88fr531_name
611 .long feroceon_processor_functions
613 .long feroceon_user_fns
614 .long feroceon_cache_fns
615 .size __88fr531_proc_info, . - __88fr531_proc_info
617 .type __88fr571_proc_info,#object
621 .long PMD_TYPE_SECT | \
622 PMD_SECT_BUFFERABLE | \
623 PMD_SECT_CACHEABLE | \
625 PMD_SECT_AP_WRITE | \
627 .long PMD_TYPE_SECT | \
629 PMD_SECT_AP_WRITE | \
634 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
635 .long cpu_88fr571_name
636 .long feroceon_processor_functions
638 .long feroceon_user_fns
639 .long feroceon_range_cache_fns
640 .size __88fr571_proc_info, . - __88fr571_proc_info
642 .type __88fr131_proc_info,#object
646 .long PMD_TYPE_SECT | \
647 PMD_SECT_BUFFERABLE | \
648 PMD_SECT_CACHEABLE | \
650 PMD_SECT_AP_WRITE | \
652 .long PMD_TYPE_SECT | \
654 PMD_SECT_AP_WRITE | \
659 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
660 .long cpu_88fr131_name
661 .long feroceon_processor_functions
663 .long feroceon_user_fns
664 .long feroceon_range_cache_fns
665 .size __88fr131_proc_info, . - __88fr131_proc_info