2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/ptrace.h>
19 #include <linux/sysdev.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
23 #include <asm/hardware.h>
25 #include <asm/delay.h>
26 #include <asm/arch/irqs.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/mach/irq.h>
33 * OMAP1510 GPIO registers
35 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
44 #define OMAP1510_IH_GPIO_BASE 64
47 * OMAP1610 specific GPIO registers
49 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
50 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
51 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
52 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
53 #define OMAP1610_GPIO_REVISION 0x0000
54 #define OMAP1610_GPIO_SYSCONFIG 0x0010
55 #define OMAP1610_GPIO_SYSSTATUS 0x0014
56 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
57 #define OMAP1610_GPIO_IRQENABLE1 0x001c
58 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
59 #define OMAP1610_GPIO_DATAIN 0x002c
60 #define OMAP1610_GPIO_DATAOUT 0x0030
61 #define OMAP1610_GPIO_DIRECTION 0x0034
62 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
65 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
66 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
68 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
69 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
72 * OMAP730 specific GPIO registers
74 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
75 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
76 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
77 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
78 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
79 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
80 #define OMAP730_GPIO_DATA_INPUT 0x00
81 #define OMAP730_GPIO_DATA_OUTPUT 0x04
82 #define OMAP730_GPIO_DIR_CONTROL 0x08
83 #define OMAP730_GPIO_INT_CONTROL 0x0c
84 #define OMAP730_GPIO_INT_MASK 0x10
85 #define OMAP730_GPIO_INT_STATUS 0x14
88 * omap24xx specific GPIO registers
90 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
91 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
92 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
93 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
94 #define OMAP24XX_GPIO_REVISION 0x0000
95 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
96 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
97 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
98 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
99 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
100 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
101 #define OMAP24XX_GPIO_CTRL 0x0030
102 #define OMAP24XX_GPIO_OE 0x0034
103 #define OMAP24XX_GPIO_DATAIN 0x0038
104 #define OMAP24XX_GPIO_DATAOUT 0x003c
105 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
106 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
107 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
108 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
109 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
110 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
111 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
112 #define OMAP24XX_GPIO_SETWKUENA 0x0084
113 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
114 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
119 u16 virtual_irq_start;
122 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
126 #ifdef CONFIG_ARCH_OMAP24XX
127 u32 non_wakeup_gpios;
128 u32 enabled_non_wakeup_gpios;
131 u32 saved_fallingdetect;
132 u32 saved_risingdetect;
137 #define METHOD_MPUIO 0
138 #define METHOD_GPIO_1510 1
139 #define METHOD_GPIO_1610 2
140 #define METHOD_GPIO_730 3
141 #define METHOD_GPIO_24XX 4
143 #ifdef CONFIG_ARCH_OMAP16XX
144 static struct gpio_bank gpio_bank_1610[5] = {
145 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
146 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
147 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
148 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
149 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
153 #ifdef CONFIG_ARCH_OMAP15XX
154 static struct gpio_bank gpio_bank_1510[2] = {
155 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
156 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
160 #ifdef CONFIG_ARCH_OMAP730
161 static struct gpio_bank gpio_bank_730[7] = {
162 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
163 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
164 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
165 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
166 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
167 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
168 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
172 #ifdef CONFIG_ARCH_OMAP24XX
173 static struct gpio_bank gpio_bank_24xx[4] = {
174 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
175 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
176 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
177 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
181 static struct gpio_bank *gpio_bank;
182 static int gpio_bank_count;
184 static inline struct gpio_bank *get_gpio_bank(int gpio)
186 #ifdef CONFIG_ARCH_OMAP15XX
187 if (cpu_is_omap15xx()) {
188 if (OMAP_GPIO_IS_MPUIO(gpio))
189 return &gpio_bank[0];
190 return &gpio_bank[1];
193 #if defined(CONFIG_ARCH_OMAP16XX)
194 if (cpu_is_omap16xx()) {
195 if (OMAP_GPIO_IS_MPUIO(gpio))
196 return &gpio_bank[0];
197 return &gpio_bank[1 + (gpio >> 4)];
200 #ifdef CONFIG_ARCH_OMAP730
201 if (cpu_is_omap730()) {
202 if (OMAP_GPIO_IS_MPUIO(gpio))
203 return &gpio_bank[0];
204 return &gpio_bank[1 + (gpio >> 5)];
207 #ifdef CONFIG_ARCH_OMAP24XX
208 if (cpu_is_omap24xx())
209 return &gpio_bank[gpio >> 5];
213 static inline int get_gpio_index(int gpio)
215 #ifdef CONFIG_ARCH_OMAP730
216 if (cpu_is_omap730())
219 #ifdef CONFIG_ARCH_OMAP24XX
220 if (cpu_is_omap24xx())
226 static inline int gpio_valid(int gpio)
230 #ifndef CONFIG_ARCH_OMAP24XX
231 if (OMAP_GPIO_IS_MPUIO(gpio)) {
232 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
237 #ifdef CONFIG_ARCH_OMAP15XX
238 if (cpu_is_omap15xx() && gpio < 16)
241 #if defined(CONFIG_ARCH_OMAP16XX)
242 if ((cpu_is_omap16xx()) && gpio < 64)
245 #ifdef CONFIG_ARCH_OMAP730
246 if (cpu_is_omap730() && gpio < 192)
249 #ifdef CONFIG_ARCH_OMAP24XX
250 if (cpu_is_omap24xx() && gpio < 128)
256 static int check_gpio(int gpio)
258 if (unlikely(gpio_valid(gpio)) < 0) {
259 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
266 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
268 void __iomem *reg = bank->base;
271 switch (bank->method) {
273 reg += OMAP_MPUIO_IO_CNTL;
275 case METHOD_GPIO_1510:
276 reg += OMAP1510_GPIO_DIR_CONTROL;
278 case METHOD_GPIO_1610:
279 reg += OMAP1610_GPIO_DIRECTION;
281 case METHOD_GPIO_730:
282 reg += OMAP730_GPIO_DIR_CONTROL;
284 case METHOD_GPIO_24XX:
285 reg += OMAP24XX_GPIO_OE;
288 l = __raw_readl(reg);
293 __raw_writel(l, reg);
296 void omap_set_gpio_direction(int gpio, int is_input)
298 struct gpio_bank *bank;
300 if (check_gpio(gpio) < 0)
302 bank = get_gpio_bank(gpio);
303 spin_lock(&bank->lock);
304 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
305 spin_unlock(&bank->lock);
308 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
310 void __iomem *reg = bank->base;
313 switch (bank->method) {
315 reg += OMAP_MPUIO_OUTPUT;
316 l = __raw_readl(reg);
322 case METHOD_GPIO_1510:
323 reg += OMAP1510_GPIO_DATA_OUTPUT;
324 l = __raw_readl(reg);
330 case METHOD_GPIO_1610:
332 reg += OMAP1610_GPIO_SET_DATAOUT;
334 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
337 case METHOD_GPIO_730:
338 reg += OMAP730_GPIO_DATA_OUTPUT;
339 l = __raw_readl(reg);
345 case METHOD_GPIO_24XX:
347 reg += OMAP24XX_GPIO_SETDATAOUT;
349 reg += OMAP24XX_GPIO_CLEARDATAOUT;
356 __raw_writel(l, reg);
359 void omap_set_gpio_dataout(int gpio, int enable)
361 struct gpio_bank *bank;
363 if (check_gpio(gpio) < 0)
365 bank = get_gpio_bank(gpio);
366 spin_lock(&bank->lock);
367 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
368 spin_unlock(&bank->lock);
371 int omap_get_gpio_datain(int gpio)
373 struct gpio_bank *bank;
376 if (check_gpio(gpio) < 0)
378 bank = get_gpio_bank(gpio);
380 switch (bank->method) {
382 reg += OMAP_MPUIO_INPUT_LATCH;
384 case METHOD_GPIO_1510:
385 reg += OMAP1510_GPIO_DATA_INPUT;
387 case METHOD_GPIO_1610:
388 reg += OMAP1610_GPIO_DATAIN;
390 case METHOD_GPIO_730:
391 reg += OMAP730_GPIO_DATA_INPUT;
393 case METHOD_GPIO_24XX:
394 reg += OMAP24XX_GPIO_DATAIN;
400 return (__raw_readl(reg)
401 & (1 << get_gpio_index(gpio))) != 0;
404 #define MOD_REG_BIT(reg, bit_mask, set) \
406 int l = __raw_readl(base + reg); \
407 if (set) l |= bit_mask; \
408 else l &= ~bit_mask; \
409 __raw_writel(l, base + reg); \
412 #ifdef CONFIG_ARCH_OMAP24XX
413 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
415 void __iomem *base = bank->base;
416 u32 gpio_bit = 1 << gpio;
418 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
419 trigger & __IRQT_LOWLVL);
420 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
421 trigger & __IRQT_HIGHLVL);
422 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
423 trigger & __IRQT_RISEDGE);
424 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
425 trigger & __IRQT_FALEDGE);
426 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
428 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
430 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
433 bank->enabled_non_wakeup_gpios |= gpio_bit;
435 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
437 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
438 * triggering requested. */
442 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
444 void __iomem *reg = bank->base;
447 switch (bank->method) {
449 reg += OMAP_MPUIO_GPIO_INT_EDGE;
450 l = __raw_readl(reg);
451 if (trigger & __IRQT_RISEDGE)
453 else if (trigger & __IRQT_FALEDGE)
458 case METHOD_GPIO_1510:
459 reg += OMAP1510_GPIO_INT_CONTROL;
460 l = __raw_readl(reg);
461 if (trigger & __IRQT_RISEDGE)
463 else if (trigger & __IRQT_FALEDGE)
468 #ifdef CONFIG_ARCH_OMAP16XX
469 case METHOD_GPIO_1610:
471 reg += OMAP1610_GPIO_EDGE_CTRL2;
473 reg += OMAP1610_GPIO_EDGE_CTRL1;
475 /* We allow only edge triggering, i.e. two lowest bits */
476 if (trigger & (__IRQT_LOWLVL | __IRQT_HIGHLVL))
478 l = __raw_readl(reg);
479 l &= ~(3 << (gpio << 1));
480 if (trigger & __IRQT_RISEDGE)
481 l |= 2 << (gpio << 1);
482 if (trigger & __IRQT_FALEDGE)
483 l |= 1 << (gpio << 1);
485 /* Enable wake-up during idle for dynamic tick */
486 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
488 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
491 #ifdef CONFIG_ARCH_OMAP730
492 case METHOD_GPIO_730:
493 reg += OMAP730_GPIO_INT_CONTROL;
494 l = __raw_readl(reg);
495 if (trigger & __IRQT_RISEDGE)
497 else if (trigger & __IRQT_FALEDGE)
503 #ifdef CONFIG_ARCH_OMAP24XX
504 case METHOD_GPIO_24XX:
505 set_24xx_gpio_triggering(bank, gpio, trigger);
512 __raw_writel(l, reg);
518 static int gpio_irq_type(unsigned irq, unsigned type)
520 struct gpio_bank *bank;
524 if (irq > IH_MPUIO_BASE)
525 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
527 gpio = irq - IH_GPIO_BASE;
529 if (check_gpio(gpio) < 0)
532 if (type & IRQT_PROBE)
534 if (!cpu_is_omap24xx() && (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL)))
537 bank = get_gpio_bank(gpio);
538 spin_lock(&bank->lock);
539 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
540 spin_unlock(&bank->lock);
544 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
546 void __iomem *reg = bank->base;
548 switch (bank->method) {
550 /* MPUIO irqstatus is reset by reading the status register,
551 * so do nothing here */
553 case METHOD_GPIO_1510:
554 reg += OMAP1510_GPIO_INT_STATUS;
556 case METHOD_GPIO_1610:
557 reg += OMAP1610_GPIO_IRQSTATUS1;
559 case METHOD_GPIO_730:
560 reg += OMAP730_GPIO_INT_STATUS;
562 case METHOD_GPIO_24XX:
563 reg += OMAP24XX_GPIO_IRQSTATUS1;
569 __raw_writel(gpio_mask, reg);
571 /* Workaround for clearing DSP GPIO interrupts to allow retention */
572 if (cpu_is_omap2420())
573 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
576 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
578 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
581 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
583 void __iomem *reg = bank->base;
588 switch (bank->method) {
590 reg += OMAP_MPUIO_GPIO_MASKIT;
594 case METHOD_GPIO_1510:
595 reg += OMAP1510_GPIO_INT_MASK;
599 case METHOD_GPIO_1610:
600 reg += OMAP1610_GPIO_IRQENABLE1;
603 case METHOD_GPIO_730:
604 reg += OMAP730_GPIO_INT_MASK;
608 case METHOD_GPIO_24XX:
609 reg += OMAP24XX_GPIO_IRQENABLE1;
617 l = __raw_readl(reg);
624 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
626 void __iomem *reg = bank->base;
629 switch (bank->method) {
631 reg += OMAP_MPUIO_GPIO_MASKIT;
632 l = __raw_readl(reg);
638 case METHOD_GPIO_1510:
639 reg += OMAP1510_GPIO_INT_MASK;
640 l = __raw_readl(reg);
646 case METHOD_GPIO_1610:
648 reg += OMAP1610_GPIO_SET_IRQENABLE1;
650 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
653 case METHOD_GPIO_730:
654 reg += OMAP730_GPIO_INT_MASK;
655 l = __raw_readl(reg);
661 case METHOD_GPIO_24XX:
663 reg += OMAP24XX_GPIO_SETIRQENABLE1;
665 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
672 __raw_writel(l, reg);
675 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
677 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
681 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
682 * 1510 does not seem to have a wake-up register. If JTAG is connected
683 * to the target, system will wake up always on GPIO events. While
684 * system is running all registered GPIO interrupts need to have wake-up
685 * enabled. When system is suspended, only selected GPIO interrupts need
686 * to have wake-up enabled.
688 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
690 switch (bank->method) {
691 #ifdef CONFIG_ARCH_OMAP16XX
692 case METHOD_GPIO_1610:
693 spin_lock(&bank->lock);
695 bank->suspend_wakeup |= (1 << gpio);
697 bank->suspend_wakeup &= ~(1 << gpio);
698 spin_unlock(&bank->lock);
701 #ifdef CONFIG_ARCH_OMAP24XX
702 case METHOD_GPIO_24XX:
703 spin_lock(&bank->lock);
705 if (bank->non_wakeup_gpios & (1 << gpio)) {
706 printk(KERN_ERR "Unable to enable wakeup on"
707 "non-wakeup GPIO%d\n",
708 (bank - gpio_bank) * 32 + gpio);
709 spin_unlock(&bank->lock);
712 bank->suspend_wakeup |= (1 << gpio);
714 bank->suspend_wakeup &= ~(1 << gpio);
715 spin_unlock(&bank->lock);
719 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
725 static void _reset_gpio(struct gpio_bank *bank, int gpio)
727 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
728 _set_gpio_irqenable(bank, gpio, 0);
729 _clear_gpio_irqstatus(bank, gpio);
730 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
733 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
734 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
736 unsigned int gpio = irq - IH_GPIO_BASE;
737 struct gpio_bank *bank;
740 if (check_gpio(gpio) < 0)
742 bank = get_gpio_bank(gpio);
743 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
748 int omap_request_gpio(int gpio)
750 struct gpio_bank *bank;
752 if (check_gpio(gpio) < 0)
755 bank = get_gpio_bank(gpio);
756 spin_lock(&bank->lock);
757 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
758 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
760 spin_unlock(&bank->lock);
763 bank->reserved_map |= (1 << get_gpio_index(gpio));
765 /* Set trigger to none. You need to enable the desired trigger with
766 * request_irq() or set_irq_type().
768 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
770 #ifdef CONFIG_ARCH_OMAP15XX
771 if (bank->method == METHOD_GPIO_1510) {
774 /* Claim the pin for MPU */
775 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
776 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
779 spin_unlock(&bank->lock);
784 void omap_free_gpio(int gpio)
786 struct gpio_bank *bank;
788 if (check_gpio(gpio) < 0)
790 bank = get_gpio_bank(gpio);
791 spin_lock(&bank->lock);
792 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
793 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
795 spin_unlock(&bank->lock);
798 #ifdef CONFIG_ARCH_OMAP16XX
799 if (bank->method == METHOD_GPIO_1610) {
800 /* Disable wake-up during idle for dynamic tick */
801 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
802 __raw_writel(1 << get_gpio_index(gpio), reg);
805 #ifdef CONFIG_ARCH_OMAP24XX
806 if (bank->method == METHOD_GPIO_24XX) {
807 /* Disable wake-up during idle for dynamic tick */
808 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
809 __raw_writel(1 << get_gpio_index(gpio), reg);
812 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
813 _reset_gpio(bank, gpio);
814 spin_unlock(&bank->lock);
818 * We need to unmask the GPIO bank interrupt as soon as possible to
819 * avoid missing GPIO interrupts for other lines in the bank.
820 * Then we need to mask-read-clear-unmask the triggered GPIO lines
821 * in the bank to avoid missing nested interrupts for a GPIO line.
822 * If we wait to unmask individual GPIO lines in the bank after the
823 * line's interrupt handler has been run, we may miss some nested
826 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
827 struct pt_regs *regs)
829 void __iomem *isr_reg = NULL;
831 unsigned int gpio_irq;
832 struct gpio_bank *bank;
836 desc->chip->ack(irq);
838 bank = get_irq_data(irq);
839 if (bank->method == METHOD_MPUIO)
840 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
841 #ifdef CONFIG_ARCH_OMAP15XX
842 if (bank->method == METHOD_GPIO_1510)
843 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
845 #if defined(CONFIG_ARCH_OMAP16XX)
846 if (bank->method == METHOD_GPIO_1610)
847 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
849 #ifdef CONFIG_ARCH_OMAP730
850 if (bank->method == METHOD_GPIO_730)
851 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
853 #ifdef CONFIG_ARCH_OMAP24XX
854 if (bank->method == METHOD_GPIO_24XX)
855 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
858 u32 isr_saved, level_mask = 0;
861 enabled = _get_gpio_irqbank_mask(bank);
862 isr_saved = isr = __raw_readl(isr_reg) & enabled;
864 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
867 if (cpu_is_omap24xx()) {
869 __raw_readl(bank->base +
870 OMAP24XX_GPIO_LEVELDETECT0) |
871 __raw_readl(bank->base +
872 OMAP24XX_GPIO_LEVELDETECT1);
873 level_mask &= enabled;
876 /* clear edge sensitive interrupts before handler(s) are
877 called so that we don't miss any interrupt occurred while
879 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
880 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
881 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
883 /* if there is only edge sensitive GPIO pin interrupts
884 configured, we could unmask GPIO bank interrupt immediately */
885 if (!level_mask && !unmasked) {
887 desc->chip->unmask(irq);
895 gpio_irq = bank->virtual_irq_start;
896 for (; isr != 0; isr >>= 1, gpio_irq++) {
901 d = irq_desc + gpio_irq;
902 /* Don't run the handler if it's already running
903 * or was disabled lazely.
905 if (unlikely((d->depth ||
906 (d->status & IRQ_INPROGRESS)))) {
908 (gpio_irq - bank->virtual_irq_start);
909 /* The unmasking will be done by
910 * enable_irq in case it is disabled or
911 * after returning from the handler if
912 * it's already running.
914 _enable_gpio_irqbank(bank, irq_mask, 0);
916 /* Level triggered interrupts
917 * won't ever be reentered
919 BUG_ON(level_mask & irq_mask);
920 d->status |= IRQ_PENDING;
925 desc_handle_irq(gpio_irq, d, regs);
927 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
929 (gpio_irq - bank->virtual_irq_start);
930 d->status &= ~IRQ_PENDING;
931 _enable_gpio_irqbank(bank, irq_mask, 1);
932 retrigger |= irq_mask;
936 if (cpu_is_omap24xx()) {
937 /* clear level sensitive interrupts after handler(s) */
938 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
939 _clear_gpio_irqbank(bank, isr_saved & level_mask);
940 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
944 /* if bank has any level sensitive GPIO pin interrupt
945 configured, we must unmask the bank interrupt only after
946 handler(s) are executed in order to avoid spurious bank
949 desc->chip->unmask(irq);
953 static void gpio_irq_shutdown(unsigned int irq)
955 unsigned int gpio = irq - IH_GPIO_BASE;
956 struct gpio_bank *bank = get_gpio_bank(gpio);
958 _reset_gpio(bank, gpio);
961 static void gpio_ack_irq(unsigned int irq)
963 unsigned int gpio = irq - IH_GPIO_BASE;
964 struct gpio_bank *bank = get_gpio_bank(gpio);
966 _clear_gpio_irqstatus(bank, gpio);
969 static void gpio_mask_irq(unsigned int irq)
971 unsigned int gpio = irq - IH_GPIO_BASE;
972 struct gpio_bank *bank = get_gpio_bank(gpio);
974 _set_gpio_irqenable(bank, gpio, 0);
977 static void gpio_unmask_irq(unsigned int irq)
979 unsigned int gpio = irq - IH_GPIO_BASE;
980 unsigned int gpio_idx = get_gpio_index(gpio);
981 struct gpio_bank *bank = get_gpio_bank(gpio);
983 _set_gpio_irqenable(bank, gpio_idx, 1);
986 static void mpuio_ack_irq(unsigned int irq)
988 /* The ISR is reset automatically, so do nothing here. */
991 static void mpuio_mask_irq(unsigned int irq)
993 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
994 struct gpio_bank *bank = get_gpio_bank(gpio);
996 _set_gpio_irqenable(bank, gpio, 0);
999 static void mpuio_unmask_irq(unsigned int irq)
1001 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1002 struct gpio_bank *bank = get_gpio_bank(gpio);
1004 _set_gpio_irqenable(bank, gpio, 1);
1007 static struct irq_chip gpio_irq_chip = {
1009 .shutdown = gpio_irq_shutdown,
1010 .ack = gpio_ack_irq,
1011 .mask = gpio_mask_irq,
1012 .unmask = gpio_unmask_irq,
1013 .set_type = gpio_irq_type,
1014 .set_wake = gpio_wake_enable,
1017 static struct irq_chip mpuio_irq_chip = {
1019 .ack = mpuio_ack_irq,
1020 .mask = mpuio_mask_irq,
1021 .unmask = mpuio_unmask_irq
1024 static int initialized;
1025 static struct clk * gpio_ick;
1026 static struct clk * gpio_fck;
1028 static int __init _omap_gpio_init(void)
1031 struct gpio_bank *bank;
1035 if (cpu_is_omap15xx()) {
1036 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1037 if (IS_ERR(gpio_ick))
1038 printk("Could not get arm_gpio_ck\n");
1040 clk_enable(gpio_ick);
1042 if (cpu_is_omap24xx()) {
1043 gpio_ick = clk_get(NULL, "gpios_ick");
1044 if (IS_ERR(gpio_ick))
1045 printk("Could not get gpios_ick\n");
1047 clk_enable(gpio_ick);
1048 gpio_fck = clk_get(NULL, "gpios_fck");
1049 if (IS_ERR(gpio_fck))
1050 printk("Could not get gpios_fck\n");
1052 clk_enable(gpio_fck);
1055 #ifdef CONFIG_ARCH_OMAP15XX
1056 if (cpu_is_omap15xx()) {
1057 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1058 gpio_bank_count = 2;
1059 gpio_bank = gpio_bank_1510;
1062 #if defined(CONFIG_ARCH_OMAP16XX)
1063 if (cpu_is_omap16xx()) {
1066 gpio_bank_count = 5;
1067 gpio_bank = gpio_bank_1610;
1068 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1069 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1070 (rev >> 4) & 0x0f, rev & 0x0f);
1073 #ifdef CONFIG_ARCH_OMAP730
1074 if (cpu_is_omap730()) {
1075 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1076 gpio_bank_count = 7;
1077 gpio_bank = gpio_bank_730;
1080 #ifdef CONFIG_ARCH_OMAP24XX
1081 if (cpu_is_omap24xx()) {
1084 gpio_bank_count = 4;
1085 gpio_bank = gpio_bank_24xx;
1086 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1087 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
1088 (rev >> 4) & 0x0f, rev & 0x0f);
1091 for (i = 0; i < gpio_bank_count; i++) {
1092 int j, gpio_count = 16;
1094 bank = &gpio_bank[i];
1095 bank->reserved_map = 0;
1096 bank->base = IO_ADDRESS(bank->base);
1097 spin_lock_init(&bank->lock);
1098 if (bank->method == METHOD_MPUIO) {
1099 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1101 #ifdef CONFIG_ARCH_OMAP15XX
1102 if (bank->method == METHOD_GPIO_1510) {
1103 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1104 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1107 #if defined(CONFIG_ARCH_OMAP16XX)
1108 if (bank->method == METHOD_GPIO_1610) {
1109 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1110 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1111 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1114 #ifdef CONFIG_ARCH_OMAP730
1115 if (bank->method == METHOD_GPIO_730) {
1116 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1117 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1119 gpio_count = 32; /* 730 has 32-bit GPIOs */
1122 #ifdef CONFIG_ARCH_OMAP24XX
1123 if (bank->method == METHOD_GPIO_24XX) {
1124 static const u32 non_wakeup_gpios[] = {
1125 0xe203ffc0, 0x08700040
1128 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1129 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1130 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1132 /* Initialize interface clock ungated, module enabled */
1133 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1134 if (i < ARRAY_SIZE(non_wakeup_gpios))
1135 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1139 for (j = bank->virtual_irq_start;
1140 j < bank->virtual_irq_start + gpio_count; j++) {
1141 if (bank->method == METHOD_MPUIO)
1142 set_irq_chip(j, &mpuio_irq_chip);
1144 set_irq_chip(j, &gpio_irq_chip);
1145 set_irq_handler(j, do_simple_IRQ);
1146 set_irq_flags(j, IRQF_VALID);
1148 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1149 set_irq_data(bank->irq, bank);
1152 /* Enable system clock for GPIO module.
1153 * The CAM_CLK_CTRL *is* really the right place. */
1154 if (cpu_is_omap16xx())
1155 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1157 #ifdef CONFIG_ARCH_OMAP24XX
1158 /* Enable autoidle for the OCP interface */
1159 if (cpu_is_omap24xx())
1160 omap_writel(1 << 0, 0x48019010);
1166 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1167 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1171 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1174 for (i = 0; i < gpio_bank_count; i++) {
1175 struct gpio_bank *bank = &gpio_bank[i];
1176 void __iomem *wake_status;
1177 void __iomem *wake_clear;
1178 void __iomem *wake_set;
1180 switch (bank->method) {
1181 case METHOD_GPIO_1610:
1182 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1183 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1184 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1186 case METHOD_GPIO_24XX:
1187 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1188 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1189 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1195 spin_lock(&bank->lock);
1196 bank->saved_wakeup = __raw_readl(wake_status);
1197 __raw_writel(0xffffffff, wake_clear);
1198 __raw_writel(bank->suspend_wakeup, wake_set);
1199 spin_unlock(&bank->lock);
1205 static int omap_gpio_resume(struct sys_device *dev)
1209 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1212 for (i = 0; i < gpio_bank_count; i++) {
1213 struct gpio_bank *bank = &gpio_bank[i];
1214 void __iomem *wake_clear;
1215 void __iomem *wake_set;
1217 switch (bank->method) {
1218 case METHOD_GPIO_1610:
1219 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1220 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1222 case METHOD_GPIO_24XX:
1223 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1224 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1230 spin_lock(&bank->lock);
1231 __raw_writel(0xffffffff, wake_clear);
1232 __raw_writel(bank->saved_wakeup, wake_set);
1233 spin_unlock(&bank->lock);
1239 static struct sysdev_class omap_gpio_sysclass = {
1240 set_kset_name("gpio"),
1241 .suspend = omap_gpio_suspend,
1242 .resume = omap_gpio_resume,
1245 static struct sys_device omap_gpio_device = {
1247 .cls = &omap_gpio_sysclass,
1252 #ifdef CONFIG_ARCH_OMAP24XX
1254 static int workaround_enabled;
1256 void omap2_gpio_prepare_for_retention(void)
1260 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1261 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1262 for (i = 0; i < gpio_bank_count; i++) {
1263 struct gpio_bank *bank = &gpio_bank[i];
1266 if (!(bank->enabled_non_wakeup_gpios))
1268 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1269 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1270 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1271 bank->saved_fallingdetect = l1;
1272 bank->saved_risingdetect = l2;
1273 l1 &= ~bank->enabled_non_wakeup_gpios;
1274 l2 &= ~bank->enabled_non_wakeup_gpios;
1275 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1276 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1280 workaround_enabled = 0;
1283 workaround_enabled = 1;
1286 void omap2_gpio_resume_after_retention(void)
1290 if (!workaround_enabled)
1292 for (i = 0; i < gpio_bank_count; i++) {
1293 struct gpio_bank *bank = &gpio_bank[i];
1296 if (!(bank->enabled_non_wakeup_gpios))
1298 __raw_writel(bank->saved_fallingdetect,
1299 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1300 __raw_writel(bank->saved_risingdetect,
1301 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1302 /* Check if any of the non-wakeup interrupt GPIOs have changed
1303 * state. If so, generate an IRQ by software. This is
1304 * horribly racy, but it's the best we can do to work around
1305 * this silicon bug. */
1306 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1307 l ^= bank->saved_datain;
1308 l &= bank->non_wakeup_gpios;
1312 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1313 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1314 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1315 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1316 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1317 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1326 * This may get called early from board specific init
1327 * for boards that have interrupts routed via FPGA.
1329 int omap_gpio_init(void)
1332 return _omap_gpio_init();
1337 static int __init omap_gpio_sysinit(void)
1342 ret = _omap_gpio_init();
1344 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1345 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1347 ret = sysdev_class_register(&omap_gpio_sysclass);
1349 ret = sysdev_register(&omap_gpio_device);
1357 EXPORT_SYMBOL(omap_request_gpio);
1358 EXPORT_SYMBOL(omap_free_gpio);
1359 EXPORT_SYMBOL(omap_set_gpio_direction);
1360 EXPORT_SYMBOL(omap_set_gpio_dataout);
1361 EXPORT_SYMBOL(omap_get_gpio_datain);
1363 arch_initcall(omap_gpio_sysinit);