1 #ifndef ____ASM_ARCH_SDRC_H
2 #define ____ASM_ARCH_SDRC_H
5 * OMAP2/3 SDRC/SMS register definitions
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
21 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
23 #define SDRC_SYSCONFIG 0x010
24 #define SDRC_CS_CFG 0x040
25 #define SDRC_SHARING 0x044
26 #define SDRC_ERR_TYPE 0x04C
27 #define SDRC_DLLA_CTRL 0x060
28 #define SDRC_DLLA_STATUS 0x064
29 #define SDRC_DLLB_CTRL 0x068
30 #define SDRC_DLLB_STATUS 0x06C
31 #define SDRC_POWER 0x070
32 #define SDRC_MCFG_0 0x080
33 #define SDRC_MR_0 0x084
34 #define SDRC_ACTIM_CTRL_A_0 0x09c
35 #define SDRC_ACTIM_CTRL_B_0 0x0a0
36 #define SDRC_RFR_CTRL_0 0x0a4
37 #define SDRC_MCFG_1 0x0B0
38 #define SDRC_MR_1 0x0B4
39 #define SDRC_ACTIM_CTRL_A_1 0x0C4
40 #define SDRC_ACTIM_CTRL_B_1 0x0C8
41 #define SDRC_RFR_CTRL_1 0x0D4
44 * These values represent the number of memory clock cycles between
45 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
46 * rows per device, and include a subtraction of a 50 cycle window in the
47 * event that the autorefresh command is delayed due to other SDRC activity.
48 * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
51 * These represent optimal values for common parts, it won't work for all.
52 * As long as you scale down, most parameters are still work, they just
53 * become sub-optimal. The RFR value goes in the opposite direction. If you
54 * don't adjust it down as your clock period increases the refresh interval
55 * will not be met. Setting all parameters for complete worst case may work,
56 * but may cut memory performance by 2x. Due to errata the DLLs need to be
57 * unlocked and their value needs run time calibration. A dynamic call is
58 * need for that as no single right value exists acorss production samples.
60 * Only the FULL speed values are given. Current code is such that rate
61 * changes must be made at DPLLoutx2. The actual value adjustment for low
62 * frequency operation will be handled by omap_set_performance()
64 * By having the boot loader boot up in the fastest L4 speed available likely
65 * will result in something which you can switch between.
67 #define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
68 #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
69 #define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
70 #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
71 #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
78 #define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg)
79 #define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg)
80 #define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg)
82 /* SMS register offsets - read/write with sms_{read,write}_reg() */
84 #define SMS_SYSCONFIG 0x010
85 /* REVISIT: fill in other SMS registers here */
91 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
92 * @rate: SDRC clock rate (in Hz)
93 * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
94 * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
95 * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
96 * @mr: Value to program to SDRC_MR for this rate
98 * This structure holds a pre-computed set of register values for the
99 * SDRC for a given SDRC clock rate and SDRAM chip. These are
100 * intended to be pre-computed and specified in an array in the board-*.c
101 * files. The structure is keyed off the 'rate' field.
103 struct omap_sdrc_params {
111 void __init omap2_sdrc_init(struct omap_sdrc_params *);
112 struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
114 #ifdef CONFIG_ARCH_OMAP2
116 struct memory_timings {
117 u32 m_type; /* ddr = 1, sdr = 0 */
118 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
119 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
120 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
121 u32 base_cs; /* base chip select to use for calculations */
124 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
126 u32 omap2xxx_sdrc_dll_is_unlocked(void);
127 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
129 #endif /* CONFIG_ARCH_OMAP2 */
131 #endif /* __ASSEMBLER__ */