1 /* linux/arch/arm/plat-s3c64xx/clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX Base clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/delay.h>
22 #include <mach/hardware.h>
25 #include <plat/regs-clock.h>
27 #include <plat/devs.h>
28 #include <plat/clock.h>
30 struct clk clk_27m = {
36 struct clk clk_48m = {
42 static int inline s3c64xx_gate(void __iomem *reg,
46 unsigned int ctrlbit = clk->ctrlbit;
49 con = __raw_readl(reg);
56 __raw_writel(con, reg);
60 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
62 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
65 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
67 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
70 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
72 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
75 static struct clk init_clocks_disable[] = {
84 .enable = s3c64xx_pclk_ctrl,
85 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
90 .enable = s3c64xx_pclk_ctrl,
91 .ctrlbit = S3C_CLKCON_PCLK_IIC,
96 .enable = s3c64xx_pclk_ctrl,
97 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
102 .enable = s3c64xx_pclk_ctrl,
103 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
108 .enable = s3c64xx_pclk_ctrl,
109 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
114 .enable = s3c64xx_pclk_ctrl,
115 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
120 .enable = s3c64xx_sclk_ctrl,
121 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
126 .enable = s3c64xx_sclk_ctrl,
127 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
132 .enable = s3c64xx_sclk_ctrl,
133 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
137 static struct clk init_clocks[] = {
142 .enable = s3c64xx_hclk_ctrl,
143 .ctrlbit = S3C_CLKCON_HCLK_LCD,
148 .enable = s3c64xx_pclk_ctrl,
149 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
154 .enable = s3c64xx_hclk_ctrl,
155 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
160 .enable = s3c64xx_hclk_ctrl,
161 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
166 .enable = s3c64xx_hclk_ctrl,
167 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
172 .enable = s3c64xx_hclk_ctrl,
173 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
178 .enable = s3c64xx_pclk_ctrl,
179 .ctrlbit = S3C_CLKCON_PCLK_PWM,
184 .enable = s3c64xx_pclk_ctrl,
185 .ctrlbit = S3C_CLKCON_PCLK_UART0,
190 .enable = s3c64xx_pclk_ctrl,
191 .ctrlbit = S3C_CLKCON_PCLK_UART1,
196 .enable = s3c64xx_pclk_ctrl,
197 .ctrlbit = S3C_CLKCON_PCLK_UART2,
202 .enable = s3c64xx_pclk_ctrl,
203 .ctrlbit = S3C_CLKCON_PCLK_UART3,
208 .enable = s3c64xx_pclk_ctrl,
209 .ctrlbit = S3C_CLKCON_PCLK_RTC,
214 .ctrlbit = S3C_CLKCON_PCLK_WDT,
219 .ctrlbit = S3C_CLKCON_PCLK_AC97,
223 static struct clk *clks[] __initdata = {
230 void s3c64xx_register_clocks(void)
236 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
239 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
240 ret = s3c24xx_register_clock(clkp);
242 printk(KERN_ERR "Failed to register clock %s (%d)\n",
247 clkp = init_clocks_disable;
248 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
250 ret = s3c24xx_register_clock(clkp);
252 printk(KERN_ERR "Failed to register clock %s (%d)\n",
256 (clkp->enable)(clkp, 0);