arch/arm/plat-s3c64xx/clock.c

   1 /* linux/arch/arm/plat-s3c64xx/clock.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX Base clock support
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ioport.h>
  19 #include <linux/delay.h>
  20 #include <linux/io.h>
  21
  22 #include <mach/hardware.h>
  23 #include <mach/map.h>
  24
  25 #include <plat/regs-clock.h>
  26 #include <plat/cpu.h>
  27 #include <plat/devs.h>
  28 #include <plat/clock.h>
  29
  30 struct clk clk_27m = {
  31         .name           = "clk_27m",
  32         .id             = -1,
  33         .rate           = 27000000,
  34 };
  35
  36 struct clk clk_48m = {
  37         .name           = "clk_48m",
  38         .id             = -1,
  39         .rate           = 48000000,
  40 };
  41
  42 static int inline s3c64xx_gate(void __iomem *reg,
  43                                 struct clk *clk,
  44                                 int enable)
  45 {
  46         unsigned int ctrlbit = clk->ctrlbit;
  47         u32 con;
  48
  49         con = __raw_readl(reg);
  50
  51         if (enable)
  52                 con |= ctrlbit;
  53         else
  54                 con &= ~ctrlbit;
  55
  56         __raw_writel(con, reg);
  57         return 0;
  58 }
  59
  60 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
  61 {
  62         return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
  63 }
  64
  65 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
  66 {
  67         return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
  68 }
  69
  70 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
  71 {
  72         return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
  73 }
  74
  75 static struct clk init_clocks_disable[] = {
  76         {
  77                 .name           = "nand",
  78                 .id             = -1,
  79                 .parent         = &clk_h,
  80         }, {
  81                 .name           = "adc",
  82                 .id             = -1,
  83                 .parent         = &clk_p,
  84                 .enable         = s3c64xx_pclk_ctrl,
  85                 .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
  86         }, {
  87                 .name           = "i2c",
  88                 .id             = -1,
  89                 .parent         = &clk_p,
  90                 .enable         = s3c64xx_pclk_ctrl,
  91                 .ctrlbit        = S3C_CLKCON_PCLK_IIC,
  92         }, {
  93                 .name           = "iis",
  94                 .id             = 0,
  95                 .parent         = &clk_p,
  96                 .enable         = s3c64xx_pclk_ctrl,
  97                 .ctrlbit        = S3C_CLKCON_PCLK_IIS0,
  98         }, {
  99                 .name           = "iis",
 100                 .id             = 1,
 101                 .parent         = &clk_p,
 102                 .enable         = s3c64xx_pclk_ctrl,
 103                 .ctrlbit        = S3C_CLKCON_PCLK_IIS1,
 104         }, {
 105                 .name           = "spi",
 106                 .id             = 0,
 107                 .parent         = &clk_p,
 108                 .enable         = s3c64xx_pclk_ctrl,
 109                 .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
 110         }, {
 111                 .name           = "spi",
 112                 .id             = 1,
 113                 .parent         = &clk_p,
 114                 .enable         = s3c64xx_pclk_ctrl,
 115                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
 116         }, {
 117                 .name           = "48m",
 118                 .id             = 0,
 119                 .parent         = &clk_48m,
 120                 .enable         = s3c64xx_sclk_ctrl,
 121                 .ctrlbit        = S3C_CLKCON_SCLK_MMC0_48,
 122         }, {
 123                 .name           = "48m",
 124                 .id             = 1,
 125                 .parent         = &clk_48m,
 126                 .enable         = s3c64xx_sclk_ctrl,
 127                 .ctrlbit        = S3C_CLKCON_SCLK_MMC1_48,
 128         }, {
 129                 .name           = "48m",
 130                 .id             = 2,
 131                 .parent         = &clk_48m,
 132                 .enable         = s3c64xx_sclk_ctrl,
 133                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
 134         },
 135 };
 136
 137 static struct clk init_clocks[] = {
 138         {
 139                 .name           = "lcd",
 140                 .id             = -1,
 141                 .parent         = &clk_h,
 142                 .enable         = s3c64xx_hclk_ctrl,
 143                 .ctrlbit        = S3C_CLKCON_HCLK_LCD,
 144         }, {
 145                 .name           = "gpio",
 146                 .id             = -1,
 147                 .parent         = &clk_p,
 148                 .enable         = s3c64xx_pclk_ctrl,
 149                 .ctrlbit        = S3C_CLKCON_PCLK_GPIO,
 150         }, {
 151                 .name           = "usb-host",
 152                 .id             = -1,
 153                 .parent         = &clk_h,
 154                 .enable         = s3c64xx_hclk_ctrl,
 155                 .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
 156         }, {
 157                 .name           = "hsmmc",
 158                 .id             = 0,
 159                 .parent         = &clk_h,
 160                 .enable         = s3c64xx_hclk_ctrl,
 161                 .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
 162         }, {
 163                 .name           = "hsmmc",
 164                 .id             = 1,
 165                 .parent         = &clk_h,
 166                 .enable         = s3c64xx_hclk_ctrl,
 167                 .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
 168         }, {
 169                 .name           = "hsmmc",
 170                 .id             = 2,
 171                 .parent         = &clk_h,
 172                 .enable         = s3c64xx_hclk_ctrl,
 173                 .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
 174         }, {
 175                 .name           = "timers",
 176                 .id             = -1,
 177                 .parent         = &clk_p,
 178                 .enable         = s3c64xx_pclk_ctrl,
 179                 .ctrlbit        = S3C_CLKCON_PCLK_PWM,
 180         }, {
 181                 .name           = "uart",
 182                 .id             = 0,
 183                 .parent         = &clk_p,
 184                 .enable         = s3c64xx_pclk_ctrl,
 185                 .ctrlbit        = S3C_CLKCON_PCLK_UART0,
 186         }, {
 187                 .name           = "uart",
 188                 .id             = 1,
 189                 .parent         = &clk_p,
 190                 .enable         = s3c64xx_pclk_ctrl,
 191                 .ctrlbit        = S3C_CLKCON_PCLK_UART1,
 192         }, {
 193                 .name           = "uart",
 194                 .id             = 2,
 195                 .parent         = &clk_p,
 196                 .enable         = s3c64xx_pclk_ctrl,
 197                 .ctrlbit        = S3C_CLKCON_PCLK_UART2,
 198         }, {
 199                 .name           = "uart",
 200                 .id             = 3,
 201                 .parent         = &clk_p,
 202                 .enable         = s3c64xx_pclk_ctrl,
 203                 .ctrlbit        = S3C_CLKCON_PCLK_UART3,
 204         }, {
 205                 .name           = "rtc",
 206                 .id             = -1,
 207                 .parent         = &clk_p,
 208                 .enable         = s3c64xx_pclk_ctrl,
 209                 .ctrlbit        = S3C_CLKCON_PCLK_RTC,
 210         }, {
 211                 .name           = "watchdog",
 212                 .id             = -1,
 213                 .parent         = &clk_p,
 214                 .ctrlbit        = S3C_CLKCON_PCLK_WDT,
 215         }, {
 216                 .name           = "ac97",
 217                 .id             = -1,
 218                 .parent         = &clk_p,
 219                 .ctrlbit        = S3C_CLKCON_PCLK_AC97,
 220         }
 221 };
 222
 223 static struct clk *clks[] __initdata = {
 224         &clk_ext,
 225         &clk_epll,
 226         &clk_27m,
 227         &clk_48m,
 228 };
 229
 230 void s3c64xx_register_clocks(void)
 231 {
 232         struct clk *clkp;
 233         int ret;
 234         int ptr;
 235
 236         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 237
 238         clkp = init_clocks;
 239         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
 240                 ret = s3c24xx_register_clock(clkp);
 241                 if (ret < 0) {
 242                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 243                                clkp->name, ret);
 244                 }
 245         }
 246
 247         clkp = init_clocks_disable;
 248         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 249
 250                 ret = s3c24xx_register_clock(clkp);
 251                 if (ret < 0) {
 252                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 253                                clkp->name, ret);
 254                 }
 255
 256                 (clkp->enable)(clkp, 0);
 257         }
 258 }