2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
32 config SEMAPHORE_SLEEPERS
36 config GENERIC_FIND_NEXT_BIT
40 config GENERIC_HWEIGHT
44 config GENERIC_HARDIRQS
48 config GENERIC_IRQ_PROBE
60 config FORCE_MAX_ZONEORDER
64 config GENERIC_CALIBRATE_DELAY
73 source "kernel/Kconfig.preempt"
75 menu "Blackfin Processor Options"
77 comment "Processor and Board Settings"
86 BF522 Processor Support.
91 BF525 Processor Support.
96 BF527 Processor Support.
101 BF531 Processor Support.
106 BF532 Processor Support.
111 BF533 Processor Support.
116 BF534 Processor Support.
121 BF536 Processor Support.
126 BF537 Processor Support.
131 BF542 Processor Support.
136 BF544 Processor Support.
141 BF547 Processor Support.
146 BF548 Processor Support.
151 BF549 Processor Support.
156 Not Supported Yet - Work in progress - BF561 Processor Support.
162 default BF_REV_0_1 if BF527
163 default BF_REV_0_2 if BF537
164 default BF_REV_0_3 if BF533
165 default BF_REV_0_0 if BF549
169 depends on (BF52x || BF54x)
173 depends on (BF52x || BF54x)
177 depends on (BF537 || BF536 || BF534)
181 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
185 depends on (BF561 || BF533 || BF532 || BF531)
189 depends on (BF561 || BF533 || BF532 || BF531)
201 depends on (BF522 || BF525 || BF527)
206 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
211 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
214 config BFIN_DUAL_CORE
219 config BFIN_SINGLE_CORE
221 depends on !BFIN_DUAL_CORE
224 config MEM_GENERIC_BOARD
226 depends on GENERIC_BOARD
229 config MEM_MT48LC64M4A2FB_7E
231 depends on (BFIN533_STAMP)
234 config MEM_MT48LC16M16A2TG_75
236 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
237 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
241 config MEM_MT48LC32M8A2_75
243 depends on (BFIN537_STAMP || PNAV10)
246 config MEM_MT48LC8M32B2B5_7
248 depends on (BFIN561_BLUETECHNIX_CM)
251 config MEM_MT48LC32M16A2TG_75
253 depends on (BFIN527_EZKIT)
256 config BFIN_SHARED_FLASH_ENET
258 depends on (BFIN533_STAMP)
261 source "arch/blackfin/mach-bf527/Kconfig"
262 source "arch/blackfin/mach-bf533/Kconfig"
263 source "arch/blackfin/mach-bf561/Kconfig"
264 source "arch/blackfin/mach-bf537/Kconfig"
265 source "arch/blackfin/mach-bf548/Kconfig"
267 menu "Board customizations"
270 bool "Default bootloader kernel arguments"
273 string "Initial kernel command string"
274 depends on CMDLINE_BOOL
275 default "console=ttyBF0,57600"
277 If you don't have a boot loader capable of passing a command line string
278 to the kernel, you may specify one here. As a minimum, you should specify
279 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
281 comment "Clock/PLL Setup"
284 int "Crystal Frequency in Hz"
285 default "11059200" if BFIN533_STAMP
286 default "27000000" if BFIN533_EZKIT
287 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
288 default "30000000" if BFIN561_EZKIT
289 default "24576000" if PNAV10
291 The frequency of CLKIN crystal oscillator on the board in Hz.
293 config BFIN_KERNEL_CLOCK
294 bool "Re-program Clocks while Kernel boots?"
297 This option decides if kernel clocks are re-programed from the
298 bootloader settings. If the clocks are not set, the SDRAM settings
299 are also not changed, and the Bootloader does 100% of the hardware
304 depends on BFIN_KERNEL_CLOCK
309 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
312 If this is set the clock will be divided by 2, before it goes to the PLL.
316 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
318 default "22" if BFIN533_EZKIT
319 default "45" if BFIN533_STAMP
320 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
321 default "22" if BFIN533_BLUETECHNIX_CM
322 default "20" if BFIN537_BLUETECHNIX_CM
323 default "20" if BFIN561_BLUETECHNIX_CM
324 default "20" if BFIN561_EZKIT
325 default "16" if H8606_HVSISTEMAS
327 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
328 PLL Frequency = (Crystal Frequency) * (this setting)
331 prompt "Core Clock Divider"
332 depends on BFIN_KERNEL_CLOCK
335 This sets the frequency of the core. It can be 1, 2, 4 or 8
336 Core Frequency = (PLL frequency) / (this setting)
352 int "System Clock Divider"
353 depends on BFIN_KERNEL_CLOCK
355 default 5 if BFIN533_EZKIT
356 default 5 if BFIN533_STAMP
357 default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
358 default 5 if BFIN533_BLUETECHNIX_CM
359 default 4 if BFIN537_BLUETECHNIX_CM
360 default 4 if BFIN561_BLUETECHNIX_CM
361 default 5 if BFIN561_EZKIT
362 default 3 if H8606_HVSISTEMAS
364 This sets the frequency of the system clock (including SDRAM or DDR).
365 This can be between 1 and 15
366 System Clock = (PLL frequency) / (this setting)
369 # Max & Min Speeds for various Chips
373 default 600000000 if BF522
374 default 600000000 if BF525
375 default 600000000 if BF527
376 default 400000000 if BF531
377 default 400000000 if BF532
378 default 750000000 if BF533
379 default 500000000 if BF534
380 default 400000000 if BF536
381 default 600000000 if BF537
382 default 533333333 if BF538
383 default 533333333 if BF539
384 default 600000000 if BF542
385 default 533333333 if BF544
386 default 533333333 if BF549
387 default 600000000 if BF561
401 comment "Kernel Timer/Scheduler"
403 source kernel/Kconfig.hz
405 comment "Memory Setup"
408 int "SDRAM Memory Size in MBytes"
409 default 32 if BFIN533_EZKIT
410 default 64 if BFIN527_EZKIT
411 default 64 if BFIN537_STAMP
412 default 64 if BFIN548_EZKIT
413 default 64 if BFIN561_EZKIT
414 default 128 if BFIN533_STAMP
416 default 32 if H8606_HVSISTEMAS
419 int "SDRAM Memory Address Width"
421 default 9 if BFIN533_EZKIT
422 default 9 if BFIN561_EZKIT
423 default 9 if H8606_HVSISTEMAS
424 default 10 if BFIN527_EZKIT
425 default 10 if BFIN537_STAMP
426 default 11 if BFIN533_STAMP
431 prompt "DDR SDRAM Chip Type"
432 depends on BFIN548_EZKIT
433 default MEM_MT46V32M16_5B
435 config MEM_MT46V32M16_6T
438 config MEM_MT46V32M16_5B
442 config ENET_FLASH_PIN
443 int "PF port/pin used for flash and ethernet sharing"
444 depends on (BFIN533_STAMP)
447 PF port/pin used for flash and ethernet sharing to allow other PF
448 pins to be used on other platforms without having to touch common
450 For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
453 hex "Kernel load address for booting"
455 range 0x1000 0x20000000
457 This option allows you to set the load address of the kernel.
458 This can be useful if you are on a board which has a small amount
459 of memory or you wish to reserve some memory at the beginning of
462 Note that you need to keep this value above 4k (0x1000) as this
463 memory region is used to capture NULL pointer references as well
464 as some core kernel functions.
466 comment "LED Status Indicators"
467 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
469 config BFIN_ALIVE_LED
470 bool "Enable Board Alive"
471 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
474 Blink the LEDs you select when the kernel is running. Helps detect
477 config BFIN_ALIVE_LED_NUM
479 depends on BFIN_ALIVE_LED
480 range 1 3 if BFIN533_STAMP
481 default "3" if BFIN533_STAMP
483 Select the LED (marked on the board) for you to blink.
486 bool "Enable System Load/Idle LED"
487 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
490 Blinks the LED you select when to determine kernel load.
492 config BFIN_IDLE_LED_NUM
494 depends on BFIN_IDLE_LED
495 range 1 3 if BFIN533_STAMP
496 default "2" if BFIN533_STAMP
498 Select the LED (marked on the board) for you to blink.
501 prompt "Blackfin Exception Scratch Register"
502 default BFIN_SCRATCH_REG_RETN
504 Select the resource to reserve for the Exception handler:
505 - RETN: Non-Maskable Interrupt (NMI)
506 - RETE: Exception Return (JTAG/ICE)
507 - CYCLES: Performance counter
509 If you are unsure, please select "RETN".
511 config BFIN_SCRATCH_REG_RETN
514 Use the RETN register in the Blackfin exception handler
515 as a stack scratch register. This means you cannot
516 safely use NMI on the Blackfin while running Linux, but
517 you can debug the system with a JTAG ICE and use the
518 CYCLES performance registers.
520 If you are unsure, please select "RETN".
522 config BFIN_SCRATCH_REG_RETE
525 Use the RETE register in the Blackfin exception handler
526 as a stack scratch register. This means you cannot
527 safely use a JTAG ICE while debugging a Blackfin board,
528 but you can safely use the CYCLES performance registers
531 If you are unsure, please select "RETN".
533 config BFIN_SCRATCH_REG_CYCLES
536 Use the CYCLES register in the Blackfin exception handler
537 as a stack scratch register. This means you cannot
538 safely use the CYCLES performance registers on a Blackfin
539 board at anytime, but you can debug the system with a JTAG
542 If you are unsure, please select "RETN".
547 # Sorry - but you need to put the hex address here -
551 config BFIN_ALIVE_LED_PORT
553 default 0xFFC00700 if (BFIN533_STAMP)
555 # Peripheral Flag Direction Register
556 config BFIN_ALIVE_LED_DPORT
558 default 0xFFC00730 if (BFIN533_STAMP)
560 config BFIN_ALIVE_LED_PIN
562 default 0x04 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 1)
563 default 0x08 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 2)
564 default 0x10 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 3)
566 config BFIN_IDLE_LED_PORT
568 default 0xFFC00700 if (BFIN533_STAMP)
570 # Peripheral Flag Direction Register
571 config BFIN_IDLE_LED_DPORT
573 default 0xFFC00730 if (BFIN533_STAMP)
575 config BFIN_IDLE_LED_PIN
577 default 0x04 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 1)
578 default 0x08 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 2)
579 default 0x10 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 3)
584 menu "Blackfin Kernel Optimizations"
586 comment "Memory Optimizations"
589 bool "Locate interrupt entry code in L1 Memory"
592 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
593 into L1 instruction memory. (less latency)
595 config EXCPT_IRQ_SYSC_L1
596 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
599 If enabled, the entire ASM lowlevel exception and interrupt entry code
600 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
604 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
607 If enabled, the frequently called do_irq dispatcher function is linked
608 into L1 instruction memory. (less latency)
610 config CORE_TIMER_IRQ_L1
611 bool "Locate frequently called timer_interrupt() function in L1 Memory"
614 If enabled, the frequently called timer_interrupt() function is linked
615 into L1 instruction memory. (less latency)
618 bool "Locate frequently idle function in L1 Memory"
621 If enabled, the frequently called idle function is linked
622 into L1 instruction memory. (less latency)
625 bool "Locate kernel schedule function in L1 Memory"
628 If enabled, the frequently called kernel schedule is linked
629 into L1 instruction memory. (less latency)
631 config ARITHMETIC_OPS_L1
632 bool "Locate kernel owned arithmetic functions in L1 Memory"
635 If enabled, arithmetic functions are linked
636 into L1 instruction memory. (less latency)
639 bool "Locate access_ok function in L1 Memory"
642 If enabled, the access_ok function is linked
643 into L1 instruction memory. (less latency)
646 bool "Locate memset function in L1 Memory"
649 If enabled, the memset function is linked
650 into L1 instruction memory. (less latency)
653 bool "Locate memcpy function in L1 Memory"
656 If enabled, the memcpy function is linked
657 into L1 instruction memory. (less latency)
659 config SYS_BFIN_SPINLOCK_L1
660 bool "Locate sys_bfin_spinlock function in L1 Memory"
663 If enabled, sys_bfin_spinlock function is linked
664 into L1 instruction memory. (less latency)
666 config IP_CHECKSUM_L1
667 bool "Locate IP Checksum function in L1 Memory"
670 If enabled, the IP Checksum function is linked
671 into L1 instruction memory. (less latency)
673 config CACHELINE_ALIGNED_L1
674 bool "Locate cacheline_aligned data to L1 Data Memory"
679 If enabled, cacheline_anligned data is linked
680 into L1 data memory. (less latency)
682 config SYSCALL_TAB_L1
683 bool "Locate Syscall Table L1 Data Memory"
687 If enabled, the Syscall LUT is linked
688 into L1 data memory. (less latency)
690 config CPLB_SWITCH_TAB_L1
691 bool "Locate CPLB Switch Tables L1 Data Memory"
695 If enabled, the CPLB Switch Tables are linked
696 into L1 data memory. (less latency)
702 prompt "Kernel executes from"
704 Choose the memory type that the kernel will be running in.
709 The kernel will be resident in RAM when running.
714 The kernel will be resident in FLASH/ROM when running.
721 bool "Allow allocating large blocks (> 1MB) of memory"
723 Allow the slab memory allocator to keep chains for very large
724 memory sizes - upto 32MB. You may need this if your system has
725 a lot of RAM, and you need to able to allocate very large
726 contiguous chunks. If unsure, say N.
729 tristate "Enable Blackfin General Purpose Timers API"
732 Enable support for the General Purpose Timers API. If you
735 To compile this driver as a module, choose M here: the module
736 will be called gptimers.ko.
739 bool "Enable DMA Support"
740 depends on (BF52x || BF53x || BF561 || BF54x)
743 DMA driver for BF5xx.
746 prompt "Uncached SDRAM region"
747 default DMA_UNCACHED_1M
748 depends on BFIN_DMA_5XX
749 config DMA_UNCACHED_2M
750 bool "Enable 2M DMA region"
751 config DMA_UNCACHED_1M
752 bool "Enable 1M DMA region"
753 config DMA_UNCACHED_NONE
754 bool "Disable DMA region"
758 comment "Cache Support"
763 config BFIN_DCACHE_BANKA
764 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
765 depends on BFIN_DCACHE && !BF531
767 config BFIN_ICACHE_LOCK
768 bool "Enable Instruction Cache Locking"
772 depends on BFIN_DCACHE
778 Cached data will be written back to SDRAM only when needed.
779 This can give a nice increase in performance, but beware of
780 broken drivers that do not properly invalidate/flush their
783 Write Through Policy:
784 Cached data will always be written back to SDRAM when the
785 cache is updated. This is a completely safe setting, but
786 performance is worse than Write Back.
788 If you are unsure of the options and you want to be safe,
789 then go with Write Through.
795 Cached data will be written back to SDRAM only when needed.
796 This can give a nice increase in performance, but beware of
797 broken drivers that do not properly invalidate/flush their
800 Write Through Policy:
801 Cached data will always be written back to SDRAM when the
802 cache is updated. This is a completely safe setting, but
803 performance is worse than Write Back.
805 If you are unsure of the options and you want to be safe,
806 then go with Write Through.
811 int "Set the max L1 SRAM pieces"
814 Set the max memory pieces for the L1 SRAM allocation algorithm.
815 Min value is 16. Max value is 1024.
817 comment "Asynchonous Memory Configuration"
819 menu "EBIU_AMGCTL Global Control"
825 bool "DMA has priority over core for ext. accesses"
831 bool "Bank 0 16 bit packing enable"
836 bool "Bank 1 16 bit packing enable"
841 bool "Bank 2 16 bit packing enable"
846 bool "Bank 3 16 bit packing enable"
850 prompt"Enable Asynchonous Memory Banks"
854 bool "Disable All Banks"
860 bool "Enable Bank 0 & 1"
862 config C_AMBEN_B0_B1_B2
863 bool "Enable Bank 0 & 1 & 2"
866 bool "Enable All Banks"
870 menu "EBIU_AMBCTL Control"
888 config EBIU_MBSCTLVAL
889 hex "EBIU Bank Select Control Register"
894 hex "Flash Memory Mode Control Register"
899 hex "Flash Memory Bank Control Register"
904 #############################################################################
905 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
912 source "drivers/pci/Kconfig"
915 bool "Support for hot-pluggable device"
917 Say Y here if you want to plug devices into your computer while
918 the system is running, and be able to use them quickly. In many
919 cases, the devices can likewise be unplugged at any time too.
921 One well known example of this is PCMCIA- or PC-cards, credit-card
922 size devices such as network cards, modems or hard drives which are
923 plugged into slots found on all modern laptop computers. Another
924 example, used on modern desktops as well as laptops, is USB.
926 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
927 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
928 Then your kernel will automatically call out to a user mode "policy
929 agent" (/sbin/hotplug) to load modules and set up software needed
930 to use devices as you hotplug them.
932 source "drivers/pcmcia/Kconfig"
934 source "drivers/pci/hotplug/Kconfig"
938 menu "Executable file formats"
940 source "fs/Kconfig.binfmt"
944 menu "Power management options"
945 source "kernel/power/Kconfig"
948 prompt "Select PM Wakeup Event Source"
949 default PM_WAKEUP_GPIO_BY_SIC_IWR
952 If you have a GPIO already configured as input with the corresponding PORTx_MASK
953 bit set - "Specify Wakeup Event by SIC_IWR value"
955 config PM_WAKEUP_GPIO_BY_SIC_IWR
956 bool "Specify Wakeup Event by SIC_IWR value"
957 config PM_WAKEUP_BY_GPIO
958 bool "Cause Wakeup Event by GPIO"
959 config PM_WAKEUP_GPIO_API
960 bool "Configure Wakeup Event by PM GPIO API"
964 config PM_WAKEUP_SIC_IWR
965 hex "Wakeup Events (SIC_IWR)"
966 depends on PM_WAKEUP_GPIO_BY_SIC_IWR
967 default 0x80000000 if (BF537 || BF536 || BF534)
968 default 0x100000 if (BF533 || BF532 || BF531)
969 default 0x800000 if (BF549 || BF548 || BF547 || BF542)
970 default 0x800000 if (BF527 || BF524 || BF522)
972 config PM_WAKEUP_GPIO_NUMBER
973 int "Wakeup GPIO number"
975 depends on PM_WAKEUP_BY_GPIO
976 default 2 if BFIN537_STAMP
979 prompt "GPIO Polarity"
980 depends on PM_WAKEUP_BY_GPIO
981 default PM_WAKEUP_GPIO_POLAR_H
982 config PM_WAKEUP_GPIO_POLAR_H
984 config PM_WAKEUP_GPIO_POLAR_L
986 config PM_WAKEUP_GPIO_POLAR_EDGE_F
988 config PM_WAKEUP_GPIO_POLAR_EDGE_R
990 config PM_WAKEUP_GPIO_POLAR_EDGE_B
996 if (BF537 || BF533 || BF54x)
998 menu "CPU Frequency scaling"
1000 source "drivers/cpufreq/Kconfig"
1006 If you want to enable this option, you should select the
1007 DPMC driver from Character Devices.
1012 source "net/Kconfig"
1014 source "drivers/Kconfig"
1018 source "kernel/Kconfig.instrumentation"
1020 source "arch/blackfin/Kconfig.debug"
1022 source "security/Kconfig"
1024 source "crypto/Kconfig"
1026 source "lib/Kconfig"