2 * File: arch/blackfin/mach-bf561/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
7 * Description: BF561 startup file
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <linux/init.h>
32 #include <asm/blackfin.h>
33 #include <asm/trace.h>
35 #if CONFIG_BFIN_KERNEL_CLOCK
36 #include <asm/mach/mem_init.h>
44 .extern _bf53x_relocate_l1_mem
46 #define INITIAL_STACK 0xFFB01000
51 /* R0: argument of command line string, passed from uboot, save it */
53 /* Set the SYSCFG register:
54 * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
60 /* Clear Out All the data and pointer Registers */
82 /* Clear Out All the DAG Registers */
98 trace_buffer_start(p0,r0);
102 /* Turn off the icache */
103 p0.l = LO(IMEM_CONTROL);
104 p0.h = HI(IMEM_CONTROL);
119 /* Turn off the dcache */
120 p0.l = LO(DMEM_CONTROL);
121 p0.h = HI(DMEM_CONTROL);
126 /* Anomaly 05000125 */
137 /* Initialise UART - when booting from u-boot, the UART is not disabled
138 * so if we dont initalize here, our serial console gets hosed */
142 w[p0] = r0.L; /* To enable DLL writes */
157 p0.h = hi(UART_GCTL);
158 p0.l = lo(UART_GCTL);
160 w[p0] = r0.L; /* To enable UART clock */
163 /* Initialize stack pointer */
164 sp.l = lo(INITIAL_STACK);
165 sp.h = hi(INITIAL_STACK);
169 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
170 call _bf53x_relocate_l1_mem;
171 #if CONFIG_BFIN_KERNEL_CLOCK
172 call _start_dma_code;
175 /* Code for initializing Async memory banks */
177 p2.h = hi(EBIU_AMBCTL1);
178 p2.l = lo(EBIU_AMBCTL1);
179 r0.h = hi(AMBCTL1VAL);
180 r0.l = lo(AMBCTL1VAL);
184 p2.h = hi(EBIU_AMBCTL0);
185 p2.l = lo(EBIU_AMBCTL0);
186 r0.h = hi(AMBCTL0VAL);
187 r0.l = lo(AMBCTL0VAL);
191 p2.h = hi(EBIU_AMGCTL);
192 p2.l = lo(EBIU_AMGCTL);
197 /* This section keeps the processor in supervisor mode
198 * during kernel boot. Switches to user mode at end of boot.
199 * See page 3-9 of Hardware Reference manual for documentation.
202 /* EVT15 = _real_start */
233 p0.l = lo(WDOGA_CTL);
234 p0.h = hi(WDOGA_CTL);
236 w[p0] = r0; /* watchdog off for now */
239 /* Code update for BSS size == 0
240 * Zero out the bss region.
249 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
253 /* In case there is a NULL pointer reference
254 * Zero out region before stext
264 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
268 /* pass the uboot arguments to the global value command line */
287 * load the current thread pointer and stack
289 r1.l = _init_thread_union;
290 r1.h = _init_thread_union;
298 jump.l _start_kernel;
304 #if CONFIG_BFIN_KERNEL_CLOCK
305 ENTRY(_start_dma_code)
306 p0.h = hi(SICA_IWR0);
307 p0.l = lo(SICA_IWR0);
314 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
315 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
316 * - [7] = output delay (add 200ps of delay to mem signals)
317 * - [6] = input delay (add 200ps of input delay to mem signals)
318 * - [5] = PDWN : 1=All Clocks off
319 * - [3] = STOPCK : 1=Core Clock off
320 * - [1] = PLL_OFF : 1=Disable Power to PLL
321 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
322 * all other bits set to zero
325 p0.h = hi(PLL_LOCKCNT);
326 p0.l = lo(PLL_LOCKCNT);
331 P2.H = hi(EBIU_SDGCTL);
332 P2.L = lo(EBIU_SDGCTL);
338 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
339 r0 = r0 << 9; /* Shift it over, */
340 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
342 r1 = PLL_BYPASS; /* Bypass the PLL? */
343 r1 = r1 << 8; /* Shift it over */
344 r0 = r1 | r0; /* add them all together */
347 p0.l = lo(PLL_CTL); /* Load the address */
348 cli r2; /* Disable interrupts */
350 w[p0] = r0.l; /* Set the value */
351 idle; /* Wait for the PLL to stablize */
352 sti r2; /* Enable interrupts */
359 if ! CC jump .Lcheck_again;
361 /* Configure SCLK & CCLK Dividers */
362 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
368 p0.l = lo(EBIU_SDRRC);
369 p0.h = hi(EBIU_SDRRC);
374 p0.l = LO(EBIU_SDBCTL);
375 p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
380 P2.H = hi(EBIU_SDGCTL);
381 P2.L = lo(EBIU_SDGCTL);
384 p0.h = hi(EBIU_SDSTAT);
385 p0.l = lo(EBIU_SDSTAT);
395 R0.L = lo(mem_SDGCTL);
396 R0.H = hi(mem_SDGCTL);
403 ENDPROC(_start_dma_code)
404 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
407 /* No more interrupts to be handled*/
411 #if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
422 p0.h = hi(FIO_FLAG_C);
423 p0.l = lo(FIO_FLAG_C);
428 /* Clear the IMASK register */
434 /* Clear the ILAT register */
441 /* make sure SYSCR is set to use BMODE */
444 R0.l = 0x20; /* on BF561, disable core b */
448 /* issue a system soft reset */
455 /* clear system soft reset */
460 /* issue core reset */
469 * Set up the usable of RAM stuff. Size of RAM is determined then
470 * an initial stack set up at the end.