2 * File: arch/blackfin/mach-common/ints-priority.c
7 * Description: Set up the interrupt priorities
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2008 Analog Devices Inc.
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
41 #include <linux/kgdb.h>
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
46 #include <asm/irq_handler.h>
49 # define BF537_GENERIC_ERROR_INT_DEMUX
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
67 unsigned long irq_flags = 0x1f;
68 EXPORT_SYMBOL(irq_flags);
70 /* The number of spurious interrupts */
71 atomic_t num_spurious;
74 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
79 /* irq number for request_irq, available in mach-bf5xx/irq.h */
81 /* corresponding bit in the SIC_ISR register */
83 } ivg_table[NR_PERI_INTS];
86 /* position of first irq in ivg_table for given ivg */
89 } ivg7_13[IVG13 - IVG7 + 1];
93 * Search SIC_IAR and fill tables with the irqvalues
94 * and their positions in the SIC_ISR register.
96 static void __init search_IAR(void)
98 unsigned ivg, irq_pos = 0;
99 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
102 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
104 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
105 int iar_shift = (irqn & 7) * 4;
107 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
108 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
109 bfin_read32((unsigned long *)SIC_IAR0 +
110 ((irqn % 32) >> 3) + ((irqn / 32) *
111 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
113 bfin_read32((unsigned long *)SIC_IAR0 +
114 (irqn >> 3)) >> iar_shift)) {
116 ivg_table[irq_pos].irqno = IVG7 + irqn;
117 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
118 ivg7_13[ivg].istop++;
126 * This is for core internal IRQs
129 static void bfin_ack_noop(unsigned int irq)
131 /* Dummy function. */
134 static void bfin_core_mask_irq(unsigned int irq)
136 irq_flags &= ~(1 << irq);
137 if (!irqs_disabled())
141 static void bfin_core_unmask_irq(unsigned int irq)
143 irq_flags |= 1 << irq;
145 * If interrupts are enabled, IMASK must contain the same value
146 * as irq_flags. Make sure that invariant holds. If interrupts
147 * are currently disabled we need not do anything; one of the
148 * callers will take care of setting IMASK to the proper value
149 * when reenabling interrupts.
150 * local_irq_enable just does "STI irq_flags", so it's exactly
153 if (!irqs_disabled())
158 static void bfin_internal_mask_irq(unsigned int irq)
161 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
162 ~(1 << SIC_SYSIRQ(irq)));
164 unsigned mask_bank, mask_bit;
165 mask_bank = SIC_SYSIRQ(irq) / 32;
166 mask_bit = SIC_SYSIRQ(irq) % 32;
167 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
172 static void bfin_internal_unmask_irq(unsigned int irq)
175 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
176 (1 << SIC_SYSIRQ(irq)));
178 unsigned mask_bank, mask_bit;
179 mask_bank = SIC_SYSIRQ(irq) / 32;
180 mask_bit = SIC_SYSIRQ(irq) % 32;
181 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
187 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
189 unsigned bank, bit, wakeup = 0;
191 bank = SIC_SYSIRQ(irq) / 32;
192 bit = SIC_SYSIRQ(irq) % 32;
229 local_irq_save(flags);
232 bfin_sic_iwr[bank] |= (1 << bit);
236 bfin_sic_iwr[bank] &= ~(1 << bit);
237 vr_wakeup &= ~wakeup;
240 local_irq_restore(flags);
246 static struct irq_chip bfin_core_irqchip = {
248 .ack = bfin_ack_noop,
249 .mask = bfin_core_mask_irq,
250 .unmask = bfin_core_unmask_irq,
253 static struct irq_chip bfin_internal_irqchip = {
255 .ack = bfin_ack_noop,
256 .mask = bfin_internal_mask_irq,
257 .unmask = bfin_internal_unmask_irq,
258 .mask_ack = bfin_internal_mask_irq,
259 .disable = bfin_internal_mask_irq,
260 .enable = bfin_internal_unmask_irq,
262 .set_wake = bfin_internal_set_wake,
266 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
267 static int error_int_mask;
269 static void bfin_generic_error_mask_irq(unsigned int irq)
271 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
274 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
277 static void bfin_generic_error_unmask_irq(unsigned int irq)
279 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
280 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
283 static struct irq_chip bfin_generic_error_irqchip = {
285 .ack = bfin_ack_noop,
286 .mask_ack = bfin_generic_error_mask_irq,
287 .mask = bfin_generic_error_mask_irq,
288 .unmask = bfin_generic_error_unmask_irq,
291 static void bfin_demux_error_irq(unsigned int int_err_irq,
292 struct irq_desc *inta_desc)
298 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
299 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
303 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
304 irq = IRQ_SPORT0_ERROR;
305 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
306 irq = IRQ_SPORT1_ERROR;
307 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
309 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
311 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
313 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
314 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
315 irq = IRQ_UART0_ERROR;
316 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
317 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
318 irq = IRQ_UART1_ERROR;
321 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
322 struct irq_desc *desc = irq_desc + irq;
323 desc->handle_irq(irq, desc);
328 bfin_write_PPI_STATUS(PPI_ERR_MASK);
330 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
332 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
335 case IRQ_SPORT0_ERROR:
336 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
339 case IRQ_SPORT1_ERROR:
340 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
344 bfin_write_CAN_GIS(CAN_ERR_MASK);
348 bfin_write_SPI_STAT(SPI_ERR_MASK);
356 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
361 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
362 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
363 __func__, __FILE__, __LINE__);
366 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
368 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
370 struct irq_desc *desc = irq_desc + irq;
371 /* May not call generic set_irq_handler() due to spinlock
373 desc->handle_irq = handle;
376 #if !defined(CONFIG_BF54x)
378 static unsigned short gpio_enabled[GPIO_BANK_NUM];
379 static unsigned short gpio_edge_triggered[GPIO_BANK_NUM];
381 extern void bfin_gpio_irq_prepare(unsigned gpio);
383 static void bfin_gpio_ack_irq(unsigned int irq)
385 u16 gpionr = irq - IRQ_PF0;
387 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
388 set_gpio_data(gpionr, 0);
393 static void bfin_gpio_mask_ack_irq(unsigned int irq)
395 u16 gpionr = irq - IRQ_PF0;
397 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
398 set_gpio_data(gpionr, 0);
402 set_gpio_maska(gpionr, 0);
406 static void bfin_gpio_mask_irq(unsigned int irq)
408 set_gpio_maska(irq - IRQ_PF0, 0);
412 static void bfin_gpio_unmask_irq(unsigned int irq)
414 set_gpio_maska(irq - IRQ_PF0, 1);
418 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
420 u16 gpionr = irq - IRQ_PF0;
422 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
423 bfin_gpio_irq_prepare(gpionr);
425 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
426 bfin_gpio_unmask_irq(irq);
431 static void bfin_gpio_irq_shutdown(unsigned int irq)
433 bfin_gpio_mask_irq(irq);
434 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
437 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
439 u16 gpionr = irq - IRQ_PF0;
441 if (type == IRQ_TYPE_PROBE) {
442 /* only probe unenabled GPIO interrupt lines */
443 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
445 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
448 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
449 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
450 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
451 bfin_gpio_irq_prepare(gpionr);
453 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
455 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
459 set_gpio_inen(gpionr, 0);
460 set_gpio_dir(gpionr, 0);
462 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
463 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
464 set_gpio_both(gpionr, 1);
466 set_gpio_both(gpionr, 0);
468 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
469 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
471 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
473 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
474 set_gpio_edge(gpionr, 1);
475 set_gpio_inen(gpionr, 1);
476 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
477 set_gpio_data(gpionr, 0);
480 set_gpio_edge(gpionr, 0);
481 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
482 set_gpio_inen(gpionr, 1);
487 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
488 bfin_set_irq_handler(irq, handle_edge_irq);
490 bfin_set_irq_handler(irq, handle_level_irq);
496 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
498 unsigned gpio = irq_to_gpio(irq);
501 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
503 gpio_pm_wakeup_free(gpio);
509 static struct irq_chip bfin_gpio_irqchip = {
511 .ack = bfin_gpio_ack_irq,
512 .mask = bfin_gpio_mask_irq,
513 .mask_ack = bfin_gpio_mask_ack_irq,
514 .unmask = bfin_gpio_unmask_irq,
515 .disable = bfin_gpio_mask_irq,
516 .enable = bfin_gpio_unmask_irq,
517 .set_type = bfin_gpio_irq_type,
518 .startup = bfin_gpio_irq_startup,
519 .shutdown = bfin_gpio_irq_shutdown,
521 .set_wake = bfin_gpio_set_wake,
525 static void bfin_demux_gpio_irq(unsigned int inta_irq,
526 struct irq_desc *desc)
528 unsigned int i, gpio, mask, irq, search = 0;
531 #if defined(CONFIG_BF53x)
536 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
541 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
545 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
555 #elif defined(CONFIG_BF561)
572 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
575 mask = get_gpiop_data(i) &
576 (gpio_enabled[gpio_bank(i)] &
581 desc = irq_desc + irq;
582 desc->handle_irq(irq, desc);
589 gpio = irq_to_gpio(irq);
590 mask = get_gpiop_data(gpio) &
591 (gpio_enabled[gpio_bank(gpio)] &
592 get_gpiop_maska(gpio));
596 desc = irq_desc + irq;
597 desc->handle_irq(irq, desc);
606 #else /* CONFIG_BF54x */
608 #define NR_PINT_SYS_IRQS 4
609 #define NR_PINT_BITS 32
611 #define IRQ_NOT_AVAIL 0xFF
613 #define PINT_2_BANK(x) ((x) >> 5)
614 #define PINT_2_BIT(x) ((x) & 0x1F)
615 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
617 static unsigned char irq2pint_lut[NR_PINTS];
618 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
620 static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
621 static unsigned short gpio_enabled[GPIO_BANK_NUM];
625 unsigned int mask_set;
626 unsigned int mask_clear;
627 unsigned int request;
629 unsigned int edge_set;
630 unsigned int edge_clear;
631 unsigned int invert_set;
632 unsigned int invert_clear;
633 unsigned int pinstate;
637 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
638 (struct pin_int_t *)PINT0_MASK_SET,
639 (struct pin_int_t *)PINT1_MASK_SET,
640 (struct pin_int_t *)PINT2_MASK_SET,
641 (struct pin_int_t *)PINT3_MASK_SET,
644 extern void bfin_gpio_irq_prepare(unsigned gpio);
646 inline unsigned short get_irq_base(u8 bank, u8 bmap)
651 if (bank < 2) { /*PA-PB */
652 irq_base = IRQ_PA0 + bmap * 16;
654 irq_base = IRQ_PC0 + bmap * 16;
661 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
662 void init_pint_lut(void)
664 u16 bank, bit, irq_base, bit_pos;
668 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
670 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
672 pint_assign = pint[bank]->assign;
674 for (bit = 0; bit < NR_PINT_BITS; bit++) {
676 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
678 irq_base = get_irq_base(bank, bmap);
680 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
681 bit_pos = bit + bank * NR_PINT_BITS;
683 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
684 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
692 static void bfin_gpio_ack_irq(unsigned int irq)
694 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
695 u32 pintbit = PINT_BIT(pint_val);
696 u8 bank = PINT_2_BANK(pint_val);
698 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
699 if (pint[bank]->invert_set & pintbit)
700 pint[bank]->invert_clear = pintbit;
702 pint[bank]->invert_set = pintbit;
704 pint[bank]->request = pintbit;
709 static void bfin_gpio_mask_ack_irq(unsigned int irq)
711 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
712 u32 pintbit = PINT_BIT(pint_val);
713 u8 bank = PINT_2_BANK(pint_val);
715 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
716 if (pint[bank]->invert_set & pintbit)
717 pint[bank]->invert_clear = pintbit;
719 pint[bank]->invert_set = pintbit;
722 pint[bank]->request = pintbit;
723 pint[bank]->mask_clear = pintbit;
727 static void bfin_gpio_mask_irq(unsigned int irq)
729 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
731 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
735 static void bfin_gpio_unmask_irq(unsigned int irq)
737 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
738 u32 pintbit = PINT_BIT(pint_val);
739 u8 bank = PINT_2_BANK(pint_val);
741 pint[bank]->request = pintbit;
742 pint[bank]->mask_set = pintbit;
746 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
748 u16 gpionr = irq_to_gpio(irq);
749 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
751 if (pint_val == IRQ_NOT_AVAIL) {
753 "GPIO IRQ %d :Not in PINT Assign table "
754 "Reconfigure Interrupt to Port Assignemt\n", irq);
758 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
759 bfin_gpio_irq_prepare(gpionr);
761 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
762 bfin_gpio_unmask_irq(irq);
767 static void bfin_gpio_irq_shutdown(unsigned int irq)
769 u16 gpionr = irq_to_gpio(irq);
771 bfin_gpio_mask_irq(irq);
772 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
775 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
778 u16 gpionr = irq_to_gpio(irq);
779 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
780 u32 pintbit = PINT_BIT(pint_val);
781 u8 bank = PINT_2_BANK(pint_val);
783 if (pint_val == IRQ_NOT_AVAIL)
786 if (type == IRQ_TYPE_PROBE) {
787 /* only probe unenabled GPIO interrupt lines */
788 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
790 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
793 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
794 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
795 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
796 bfin_gpio_irq_prepare(gpionr);
798 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
800 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
804 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
805 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
807 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
809 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
810 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
812 gpio_both_edge_triggered[bank] |= pintbit;
814 if (gpio_get_value(gpionr))
815 pint[bank]->invert_set = pintbit;
817 pint[bank]->invert_clear = pintbit;
819 gpio_both_edge_triggered[bank] &= ~pintbit;
822 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
823 pint[bank]->edge_set = pintbit;
824 bfin_set_irq_handler(irq, handle_edge_irq);
826 pint[bank]->edge_clear = pintbit;
827 bfin_set_irq_handler(irq, handle_level_irq);
836 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
837 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
839 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
842 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
843 u32 bank = PINT_2_BANK(pint_val);
844 u32 pintbit = PINT_BIT(pint_val);
848 pint_irq = IRQ_PINT0;
851 pint_irq = IRQ_PINT2;
854 pint_irq = IRQ_PINT3;
857 pint_irq = IRQ_PINT1;
863 bfin_internal_set_wake(pint_irq, state);
866 pint_wakeup_masks[bank] |= pintbit;
868 pint_wakeup_masks[bank] &= ~pintbit;
873 u32 bfin_pm_setup(void)
877 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
878 val = pint[i]->mask_clear;
879 pint_saved_masks[i] = val;
880 if (val ^ pint_wakeup_masks[i]) {
881 pint[i]->mask_clear = val;
882 pint[i]->mask_set = pint_wakeup_masks[i];
889 void bfin_pm_restore(void)
893 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
894 val = pint_saved_masks[i];
895 if (val ^ pint_wakeup_masks[i]) {
896 pint[i]->mask_clear = pint[i]->mask_clear;
897 pint[i]->mask_set = val;
903 static struct irq_chip bfin_gpio_irqchip = {
905 .ack = bfin_gpio_ack_irq,
906 .mask = bfin_gpio_mask_irq,
907 .mask_ack = bfin_gpio_mask_ack_irq,
908 .unmask = bfin_gpio_unmask_irq,
909 .disable = bfin_gpio_mask_irq,
910 .enable = bfin_gpio_unmask_irq,
911 .set_type = bfin_gpio_irq_type,
912 .startup = bfin_gpio_irq_startup,
913 .shutdown = bfin_gpio_irq_shutdown,
915 .set_wake = bfin_gpio_set_wake,
919 static void bfin_demux_gpio_irq(unsigned int inta_irq,
920 struct irq_desc *desc)
942 pint_val = bank * NR_PINT_BITS;
944 request = pint[bank]->request;
948 irq = pint2irq_lut[pint_val] + SYS_IRQS;
949 desc = irq_desc + irq;
950 desc->handle_irq(irq, desc);
959 void __init init_exception_vectors(void)
961 /* cannot program in software:
962 * evt0 - emulation (jtag)
965 bfin_write_EVT2(evt_nmi);
966 bfin_write_EVT3(trap);
967 bfin_write_EVT5(evt_ivhw);
968 bfin_write_EVT6(evt_timer);
969 bfin_write_EVT7(evt_evt7);
970 bfin_write_EVT8(evt_evt8);
971 bfin_write_EVT9(evt_evt9);
972 bfin_write_EVT10(evt_evt10);
973 bfin_write_EVT11(evt_evt11);
974 bfin_write_EVT12(evt_evt12);
975 bfin_write_EVT13(evt_evt13);
976 bfin_write_EVT14(evt14_softirq);
977 bfin_write_EVT15(evt_system_call);
982 * This function should be called during kernel startup to initialize
983 * the BFin IRQ handling routines.
985 int __init init_arch_irq(void)
988 unsigned long ilat = 0;
989 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
990 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
991 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
992 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
993 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
995 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
998 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1001 local_irq_disable();
1003 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1004 /* Clear EMAC Interrupt Status bits so we can demux it later */
1005 bfin_write_EMAC_SYSTAT(-1);
1009 # ifdef CONFIG_PINTx_REASSIGN
1010 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1011 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1012 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1013 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1015 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1019 for (irq = 0; irq <= SYS_IRQS; irq++) {
1020 if (irq <= IRQ_CORETMR)
1021 set_irq_chip(irq, &bfin_core_irqchip);
1023 set_irq_chip(irq, &bfin_internal_irqchip);
1026 #if defined(CONFIG_BF53x)
1028 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1031 #elif defined(CONFIG_BF54x)
1036 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1037 case IRQ_PORTF_INTA:
1038 case IRQ_PORTG_INTA:
1039 case IRQ_PORTH_INTA:
1040 #elif defined(CONFIG_BF561)
1041 case IRQ_PROG0_INTA:
1042 case IRQ_PROG1_INTA:
1043 case IRQ_PROG2_INTA:
1044 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1045 case IRQ_PORTF_INTA:
1048 set_irq_chained_handler(irq,
1049 bfin_demux_gpio_irq);
1051 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1052 case IRQ_GENERIC_ERROR:
1053 set_irq_handler(irq, bfin_demux_error_irq);
1058 set_irq_handler(irq, handle_simple_irq);
1063 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1064 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1065 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1069 /* if configured as edge, then will be changed to do_edge_IRQ */
1070 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1071 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1075 bfin_write_IMASK(0);
1077 ilat = bfin_read_ILAT();
1079 bfin_write_ILAT(ilat);
1082 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1083 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1084 * local_irq_enable()
1087 /* Therefore it's better to setup IARs before interrupts enabled */
1090 /* Enable interrupts IVG7-15 */
1091 irq_flags = irq_flags | IMASK_IVG15 |
1092 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1093 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1095 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1096 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1097 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1098 #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1099 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1100 * will screw up the bootrom as it relies on MDMA0/1 waking it
1101 * up from IDLE instructions. See this report for more info:
1102 * http://blackfin.uclinux.org/gf/tracker/4323
1104 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1106 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1108 # ifdef CONFIG_BF54x
1109 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1112 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1118 #ifdef CONFIG_DO_IRQ_L1
1119 __attribute__((l1_text))
1121 void do_irq(int vec, struct pt_regs *fp)
1123 if (vec == EVT_IVTMR_P) {
1126 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1127 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1128 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1129 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1130 unsigned long sic_status[3];
1132 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1133 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1135 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1138 if (ivg >= ivg_stop) {
1139 atomic_inc(&num_spurious);
1142 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1146 unsigned long sic_status;
1148 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1151 if (ivg >= ivg_stop) {
1152 atomic_inc(&num_spurious);
1154 } else if (sic_status & ivg->isrflag)
1160 asm_do_IRQ(vec, fp);