2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/interrupt.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/sysdev.h>
28 #include <linux/cpu.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/arch_hooks.h>
38 #include <asm/i8253.h>
40 #include <mach_apic.h>
46 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
47 * IPIs in place of local APIC timers
49 static cpumask_t timer_bcast_ipi;
52 * Knob to control our willingness to enable the local APIC.
54 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
62 static void apic_pm_activate(void);
65 * 'what should we do if we get a hw irq event on an illegal vector'.
66 * each architecture has to answer this themselves.
68 void ack_bad_irq(unsigned int irq)
70 printk("unexpected IRQ trap at vector %02x\n", irq);
72 * Currently unexpected vectors happen only on SMP and APIC.
73 * We _must_ ack these because every local APIC has only N
74 * irq slots per priority level, and a 'hanging, unacked' IRQ
75 * holds up an irq slot - in excessive cases (when multiple
76 * unexpected vectors occur) that might lock up the APIC
78 * But only ack when the APIC is enabled -AK
84 void __init apic_intr_init(void)
89 /* self generated IPI for local APIC timer */
90 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
92 /* IPI vectors for APIC spurious and error interrupts */
93 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
94 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
96 /* thermal monitor LVT interrupt */
97 #ifdef CONFIG_X86_MCE_P4THERMAL
98 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
102 /* Using APIC to generate smp_local_timer_interrupt? */
103 int using_apic_timer = 0;
105 static int enabled_via_apicbase;
107 void enable_NMI_through_LVT0 (void * dummy)
111 ver = apic_read(APIC_LVR);
112 ver = GET_APIC_VERSION(ver);
113 v = APIC_DM_NMI; /* unmask and set to NMI */
114 if (!APIC_INTEGRATED(ver)) /* 82489DX */
115 v |= APIC_LVT_LEVEL_TRIGGER;
116 apic_write_around(APIC_LVT0, v);
119 int get_physical_broadcast(void)
121 unsigned int lvr, version;
122 lvr = apic_read(APIC_LVR);
123 version = GET_APIC_VERSION(lvr);
124 if (!APIC_INTEGRATED(version) || version >= 0x14)
132 unsigned int v, ver, maxlvt;
134 v = apic_read(APIC_LVR);
135 ver = GET_APIC_VERSION(v);
136 /* 82489DXs do not report # of LVT entries. */
137 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
141 void clear_local_APIC(void)
146 maxlvt = get_maxlvt();
149 * Masking an LVT entry on a P6 can trigger a local APIC error
150 * if the vector is zero. Mask LVTERR first to prevent this.
153 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
154 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
157 * Careful: we have to set masks only first to deassert
158 * any level-triggered sources.
160 v = apic_read(APIC_LVTT);
161 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
162 v = apic_read(APIC_LVT0);
163 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
164 v = apic_read(APIC_LVT1);
165 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
167 v = apic_read(APIC_LVTPC);
168 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
171 /* lets not touch this if we didn't frob it */
172 #ifdef CONFIG_X86_MCE_P4THERMAL
174 v = apic_read(APIC_LVTTHMR);
175 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
179 * Clean APIC state for other OSs:
181 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
182 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
183 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
185 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
187 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
189 #ifdef CONFIG_X86_MCE_P4THERMAL
191 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
193 v = GET_APIC_VERSION(apic_read(APIC_LVR));
194 if (APIC_INTEGRATED(v)) { /* !82489DX */
195 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
196 apic_write(APIC_ESR, 0);
201 void __init connect_bsp_APIC(void)
205 * Do not trust the local APIC being empty at bootup.
209 * PIC mode, enable APIC mode in the IMCR, i.e.
210 * connect BSP's local APIC to INT and NMI lines.
212 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
213 "enabling APIC mode.\n");
220 void disconnect_bsp_APIC(int virt_wire_setup)
224 * Put the board back into PIC mode (has an effect
225 * only on certain older boards). Note that APIC
226 * interrupts, including IPIs, won't work beyond
227 * this point! The only exception are INIT IPIs.
229 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
230 "entering PIC mode.\n");
235 /* Go back to Virtual Wire compatibility mode */
238 /* For the spurious interrupt use vector F, and enable it */
239 value = apic_read(APIC_SPIV);
240 value &= ~APIC_VECTOR_MASK;
241 value |= APIC_SPIV_APIC_ENABLED;
243 apic_write_around(APIC_SPIV, value);
245 if (!virt_wire_setup) {
246 /* For LVT0 make it edge triggered, active high, external and enabled */
247 value = apic_read(APIC_LVT0);
248 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
249 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
250 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
251 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
252 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
253 apic_write_around(APIC_LVT0, value);
257 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
260 /* For LVT1 make it edge triggered, active high, nmi and enabled */
261 value = apic_read(APIC_LVT1);
263 APIC_MODE_MASK | APIC_SEND_PENDING |
264 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
265 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
266 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
267 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
268 apic_write_around(APIC_LVT1, value);
272 void disable_local_APIC(void)
279 * Disable APIC (implies clearing of registers
282 value = apic_read(APIC_SPIV);
283 value &= ~APIC_SPIV_APIC_ENABLED;
284 apic_write_around(APIC_SPIV, value);
286 if (enabled_via_apicbase) {
288 rdmsr(MSR_IA32_APICBASE, l, h);
289 l &= ~MSR_IA32_APICBASE_ENABLE;
290 wrmsr(MSR_IA32_APICBASE, l, h);
295 * This is to verify that we're looking at a real local APIC.
296 * Check these against your board if the CPUs aren't getting
297 * started for no apparent reason.
299 int __init verify_local_APIC(void)
301 unsigned int reg0, reg1;
304 * The version register is read-only in a real APIC.
306 reg0 = apic_read(APIC_LVR);
307 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
308 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
309 reg1 = apic_read(APIC_LVR);
310 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
313 * The two version reads above should print the same
314 * numbers. If the second one is different, then we
315 * poke at a non-APIC.
321 * Check if the version looks reasonably.
323 reg1 = GET_APIC_VERSION(reg0);
324 if (reg1 == 0x00 || reg1 == 0xff)
327 if (reg1 < 0x02 || reg1 == 0xff)
331 * The ID register is read/write in a real APIC.
333 reg0 = apic_read(APIC_ID);
334 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
337 * The next two are just to see if we have sane values.
338 * They're only really relevant if we're in Virtual Wire
339 * compatibility mode, but most boxes are anymore.
341 reg0 = apic_read(APIC_LVT0);
342 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
343 reg1 = apic_read(APIC_LVT1);
344 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
349 void __init sync_Arb_IDs(void)
351 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
352 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
353 if (ver >= 0x14) /* P4 or higher */
358 apic_wait_icr_idle();
360 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
361 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
365 extern void __error_in_apic_c (void);
368 * An initial setup of the virtual wire mode.
370 void __init init_bsp_APIC(void)
372 unsigned long value, ver;
375 * Don't do the setup now if we have a SMP BIOS as the
376 * through-I/O-APIC virtual wire mode might be active.
378 if (smp_found_config || !cpu_has_apic)
381 value = apic_read(APIC_LVR);
382 ver = GET_APIC_VERSION(value);
385 * Do not trust the local APIC being empty at bootup.
392 value = apic_read(APIC_SPIV);
393 value &= ~APIC_VECTOR_MASK;
394 value |= APIC_SPIV_APIC_ENABLED;
396 /* This bit is reserved on P4/Xeon and should be cleared */
397 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
398 value &= ~APIC_SPIV_FOCUS_DISABLED;
400 value |= APIC_SPIV_FOCUS_DISABLED;
401 value |= SPURIOUS_APIC_VECTOR;
402 apic_write_around(APIC_SPIV, value);
405 * Set up the virtual wire mode.
407 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
409 if (!APIC_INTEGRATED(ver)) /* 82489DX */
410 value |= APIC_LVT_LEVEL_TRIGGER;
411 apic_write_around(APIC_LVT1, value);
414 void __devinit setup_local_APIC(void)
416 unsigned long oldvalue, value, ver, maxlvt;
418 /* Pound the ESR really hard over the head with a big hammer - mbligh */
420 apic_write(APIC_ESR, 0);
421 apic_write(APIC_ESR, 0);
422 apic_write(APIC_ESR, 0);
423 apic_write(APIC_ESR, 0);
426 value = apic_read(APIC_LVR);
427 ver = GET_APIC_VERSION(value);
429 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
433 * Double-check whether this APIC is really registered.
435 if (!apic_id_registered())
439 * Intel recommends to set DFR, LDR and TPR before enabling
440 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
441 * document number 292116). So here it goes...
446 * Set Task Priority to 'accept all'. We never change this
449 value = apic_read(APIC_TASKPRI);
450 value &= ~APIC_TPRI_MASK;
451 apic_write_around(APIC_TASKPRI, value);
454 * Now that we are all set up, enable the APIC
456 value = apic_read(APIC_SPIV);
457 value &= ~APIC_VECTOR_MASK;
461 value |= APIC_SPIV_APIC_ENABLED;
464 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
465 * certain networking cards. If high frequency interrupts are
466 * happening on a particular IOAPIC pin, plus the IOAPIC routing
467 * entry is masked/unmasked at a high rate as well then sooner or
468 * later IOAPIC line gets 'stuck', no more interrupts are received
469 * from the device. If focus CPU is disabled then the hang goes
472 * [ This bug can be reproduced easily with a level-triggered
473 * PCI Ne2000 networking cards and PII/PIII processors, dual
477 * Actually disabling the focus CPU check just makes the hang less
478 * frequent as it makes the interrupt distributon model be more
479 * like LRU than MRU (the short-term load is more even across CPUs).
480 * See also the comment in end_level_ioapic_irq(). --macro
483 /* Enable focus processor (bit==0) */
484 value &= ~APIC_SPIV_FOCUS_DISABLED;
486 /* Disable focus processor (bit==1) */
487 value |= APIC_SPIV_FOCUS_DISABLED;
490 * Set spurious IRQ vector
492 value |= SPURIOUS_APIC_VECTOR;
493 apic_write_around(APIC_SPIV, value);
498 * set up through-local-APIC on the BP's LINT0. This is not
499 * strictly necessery in pure symmetric-IO mode, but sometimes
500 * we delegate interrupts to the 8259A.
503 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
505 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
506 if (!smp_processor_id() && (pic_mode || !value)) {
507 value = APIC_DM_EXTINT;
508 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
511 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
512 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
515 apic_write_around(APIC_LVT0, value);
518 * only the BP should see the LINT1 NMI signal, obviously.
520 if (!smp_processor_id())
523 value = APIC_DM_NMI | APIC_LVT_MASKED;
524 if (!APIC_INTEGRATED(ver)) /* 82489DX */
525 value |= APIC_LVT_LEVEL_TRIGGER;
526 apic_write_around(APIC_LVT1, value);
528 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
529 maxlvt = get_maxlvt();
530 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
531 apic_write(APIC_ESR, 0);
532 oldvalue = apic_read(APIC_ESR);
534 value = ERROR_APIC_VECTOR; // enables sending errors
535 apic_write_around(APIC_LVTERR, value);
537 * spec says clear errors after enabling vector.
540 apic_write(APIC_ESR, 0);
541 value = apic_read(APIC_ESR);
542 if (value != oldvalue)
543 apic_printk(APIC_VERBOSE, "ESR value before enabling "
544 "vector: 0x%08lx after: 0x%08lx\n",
549 * Something untraceble is creating bad interrupts on
550 * secondary quads ... for the moment, just leave the
551 * ESR disabled - we can't do anything useful with the
552 * errors anyway - mbligh
554 printk("Leaving ESR disabled.\n");
556 printk("No ESR for 82489DX.\n");
559 if (nmi_watchdog == NMI_LOCAL_APIC)
560 setup_apic_nmi_watchdog();
565 * If Linux enabled the LAPIC against the BIOS default
566 * disable it down before re-entering the BIOS on shutdown.
567 * Otherwise the BIOS may get confused and not power-off.
568 * Additionally clear all LVT entries before disable_local_APIC
569 * for the case where Linux didn't enable the LAPIC.
571 void lapic_shutdown(void)
579 if (enabled_via_apicbase)
580 disable_local_APIC();
589 /* r/w apic fields */
590 unsigned int apic_id;
591 unsigned int apic_taskpri;
592 unsigned int apic_ldr;
593 unsigned int apic_dfr;
594 unsigned int apic_spiv;
595 unsigned int apic_lvtt;
596 unsigned int apic_lvtpc;
597 unsigned int apic_lvt0;
598 unsigned int apic_lvt1;
599 unsigned int apic_lvterr;
600 unsigned int apic_tmict;
601 unsigned int apic_tdcr;
602 unsigned int apic_thmr;
605 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
609 if (!apic_pm_state.active)
612 apic_pm_state.apic_id = apic_read(APIC_ID);
613 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
614 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
615 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
616 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
617 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
618 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
619 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
620 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
621 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
622 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
623 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
624 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
626 local_irq_save(flags);
627 disable_local_APIC();
628 local_irq_restore(flags);
632 static int lapic_resume(struct sys_device *dev)
637 if (!apic_pm_state.active)
640 local_irq_save(flags);
643 * Make sure the APICBASE points to the right address
645 * FIXME! This will be wrong if we ever support suspend on
646 * SMP! We'll need to do this as part of the CPU restore!
648 rdmsr(MSR_IA32_APICBASE, l, h);
649 l &= ~MSR_IA32_APICBASE_BASE;
650 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
651 wrmsr(MSR_IA32_APICBASE, l, h);
653 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
654 apic_write(APIC_ID, apic_pm_state.apic_id);
655 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
656 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
657 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
658 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
659 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
660 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
661 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
662 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
663 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
664 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
665 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
666 apic_write(APIC_ESR, 0);
668 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
669 apic_write(APIC_ESR, 0);
671 local_irq_restore(flags);
676 * This device has no shutdown method - fully functioning local APICs
677 * are needed on every CPU up until machine_halt/restart/poweroff.
680 static struct sysdev_class lapic_sysclass = {
681 set_kset_name("lapic"),
682 .resume = lapic_resume,
683 .suspend = lapic_suspend,
686 static struct sys_device device_lapic = {
688 .cls = &lapic_sysclass,
691 static void __devinit apic_pm_activate(void)
693 apic_pm_state.active = 1;
696 static int __init init_lapic_sysfs(void)
702 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
704 error = sysdev_class_register(&lapic_sysclass);
706 error = sysdev_register(&device_lapic);
709 device_initcall(init_lapic_sysfs);
711 #else /* CONFIG_PM */
713 static void apic_pm_activate(void) { }
715 #endif /* CONFIG_PM */
718 * Detect and enable local APICs on non-SMP boards.
719 * Original code written by Keir Fraser.
722 static int __init apic_set_verbosity(char *str)
724 if (strcmp("debug", str) == 0)
725 apic_verbosity = APIC_DEBUG;
726 else if (strcmp("verbose", str) == 0)
727 apic_verbosity = APIC_VERBOSE;
729 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
730 " use apic=verbose or apic=debug\n", str);
735 __setup("apic=", apic_set_verbosity);
737 static int __init detect_init_APIC (void)
741 /* Disabled by kernel option? */
742 if (enable_local_apic < 0)
745 switch (boot_cpu_data.x86_vendor) {
747 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
748 (boot_cpu_data.x86 == 15))
751 case X86_VENDOR_INTEL:
752 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
753 (boot_cpu_data.x86 == 5 && cpu_has_apic))
762 * Over-ride BIOS and try to enable the local
763 * APIC only if "lapic" specified.
765 if (enable_local_apic <= 0) {
766 printk("Local APIC disabled by BIOS -- "
767 "you can enable it with \"lapic\"\n");
771 * Some BIOSes disable the local APIC in the
772 * APIC_BASE MSR. This can only be done in
773 * software for Intel P6 or later and AMD K7
774 * (Model > 1) or later.
776 rdmsr(MSR_IA32_APICBASE, l, h);
777 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
778 printk("Local APIC disabled by BIOS -- reenabling.\n");
779 l &= ~MSR_IA32_APICBASE_BASE;
780 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
781 wrmsr(MSR_IA32_APICBASE, l, h);
782 enabled_via_apicbase = 1;
786 * The APIC feature bit should now be enabled
789 features = cpuid_edx(1);
790 if (!(features & (1 << X86_FEATURE_APIC))) {
791 printk("Could not enable APIC!\n");
794 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
795 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
797 /* The BIOS may have set up the APIC at some other address */
798 rdmsr(MSR_IA32_APICBASE, l, h);
799 if (l & MSR_IA32_APICBASE_ENABLE)
800 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
802 if (nmi_watchdog != NMI_NONE)
803 nmi_watchdog = NMI_LOCAL_APIC;
805 printk("Found and enabled local APIC!\n");
812 printk("No local APIC present or hardware disabled\n");
816 void __init init_apic_mappings(void)
818 unsigned long apic_phys;
821 * If no local APIC can be found then set up a fake all
822 * zeroes page to simulate the local APIC and another
823 * one for the IO-APIC.
825 if (!smp_found_config && detect_init_APIC()) {
826 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
827 apic_phys = __pa(apic_phys);
829 apic_phys = mp_lapic_addr;
831 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
832 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
836 * Fetch the APIC ID of the BSP in case we have a
837 * default configuration (or the MP table is broken).
839 if (boot_cpu_physical_apicid == -1U)
840 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
842 #ifdef CONFIG_X86_IO_APIC
844 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
847 for (i = 0; i < nr_ioapics; i++) {
848 if (smp_found_config) {
849 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
852 "WARNING: bogus zero IO-APIC "
853 "address found in MPTABLE, "
854 "disabling IO/APIC support!\n");
855 smp_found_config = 0;
856 skip_ioapic_setup = 1;
857 goto fake_ioapic_page;
861 ioapic_phys = (unsigned long)
862 alloc_bootmem_pages(PAGE_SIZE);
863 ioapic_phys = __pa(ioapic_phys);
865 set_fixmap_nocache(idx, ioapic_phys);
866 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
867 __fix_to_virt(idx), ioapic_phys);
875 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
876 * per second. We assume that the caller has already set up the local
879 * The APIC timer is not exactly sync with the external timer chip, it
880 * closely follows bus clocks.
884 * The timer chip is already set up at HZ interrupts per second here,
885 * but we do not accept timer interrupts yet. We only allow the BP
888 static unsigned int __devinit get_8254_timer_count(void)
894 spin_lock_irqsave(&i8253_lock, flags);
896 outb_p(0x00, PIT_MODE);
897 count = inb_p(PIT_CH0);
898 count |= inb_p(PIT_CH0) << 8;
900 spin_unlock_irqrestore(&i8253_lock, flags);
905 /* next tick in 8254 can be caught by catching timer wraparound */
906 static void __devinit wait_8254_wraparound(void)
908 unsigned int curr_count, prev_count;
910 curr_count = get_8254_timer_count();
912 prev_count = curr_count;
913 curr_count = get_8254_timer_count();
915 /* workaround for broken Mercury/Neptune */
916 if (prev_count >= curr_count + 0x100)
917 curr_count = get_8254_timer_count();
919 } while (prev_count >= curr_count);
923 * Default initialization for 8254 timers. If we use other timers like HPET,
924 * we override this later
926 void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound;
929 * This function sets up the local APIC timer, with a timeout of
930 * 'clocks' APIC bus clock. During calibration we actually call
931 * this function twice on the boot CPU, once with a bogus timeout
932 * value, second time for real. The other (noncalibrating) CPUs
933 * call this function only once, with the real, calibrated value.
935 * We do reads before writes even if unnecessary, to get around the
936 * P5 APIC double write bug.
939 #define APIC_DIVISOR 16
941 static void __setup_APIC_LVTT(unsigned int clocks)
943 unsigned int lvtt_value, tmp_value, ver;
944 int cpu = smp_processor_id();
946 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
947 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
948 if (!APIC_INTEGRATED(ver))
949 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
951 if (cpu_isset(cpu, timer_bcast_ipi))
952 lvtt_value |= APIC_LVT_MASKED;
954 apic_write_around(APIC_LVTT, lvtt_value);
959 tmp_value = apic_read(APIC_TDCR);
960 apic_write_around(APIC_TDCR, (tmp_value
961 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
964 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
967 static void __devinit setup_APIC_timer(unsigned int clocks)
971 local_irq_save(flags);
974 * Wait for IRQ0's slice:
978 __setup_APIC_LVTT(clocks);
980 local_irq_restore(flags);
984 * In this function we calibrate APIC bus clocks to the external
985 * timer. Unfortunately we cannot use jiffies and the timer irq
986 * to calibrate, since some later bootup code depends on getting
987 * the first irq? Ugh.
989 * We want to do the calibration only once since we
990 * want to have local timer irqs syncron. CPUs connected
991 * by the same APIC bus have the very same bus frequency.
992 * And we want to have irqs off anyways, no accidental
996 static int __init calibrate_APIC_clock(void)
998 unsigned long long t1 = 0, t2 = 0;
1002 const int LOOPS = HZ/10;
1004 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
1007 * Put whatever arbitrary (but long enough) timeout
1008 * value into the APIC clock, we just want to get the
1009 * counter running for calibration.
1011 __setup_APIC_LVTT(1000000000);
1014 * The timer chip counts down to zero. Let's wait
1015 * for a wraparound to start exact measurement:
1016 * (the current tick might have been already half done)
1022 * We wrapped around just now. Let's start:
1026 tt1 = apic_read(APIC_TMCCT);
1029 * Let's wait LOOPS wraprounds:
1031 for (i = 0; i < LOOPS; i++)
1034 tt2 = apic_read(APIC_TMCCT);
1039 * The APIC bus clock counter is 32 bits only, it
1040 * might have overflown, but note that we use signed
1041 * longs, thus no extra care needed.
1043 * underflown to be exact, as the timer counts down ;)
1046 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
1049 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
1051 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
1052 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
1054 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
1056 result/(1000000/HZ),
1057 result%(1000000/HZ));
1062 static unsigned int calibration_result;
1064 void __init setup_boot_APIC_clock(void)
1066 unsigned long flags;
1067 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
1068 using_apic_timer = 1;
1070 local_irq_save(flags);
1072 calibration_result = calibrate_APIC_clock();
1074 * Now set up the timer for real.
1076 setup_APIC_timer(calibration_result);
1078 local_irq_restore(flags);
1081 void __devinit setup_secondary_APIC_clock(void)
1083 setup_APIC_timer(calibration_result);
1086 void disable_APIC_timer(void)
1088 if (using_apic_timer) {
1091 v = apic_read(APIC_LVTT);
1092 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
1096 void enable_APIC_timer(void)
1098 int cpu = smp_processor_id();
1100 if (using_apic_timer &&
1101 !cpu_isset(cpu, timer_bcast_ipi)) {
1104 v = apic_read(APIC_LVTT);
1105 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
1109 void switch_APIC_timer_to_ipi(void *cpumask)
1111 cpumask_t mask = *(cpumask_t *)cpumask;
1112 int cpu = smp_processor_id();
1114 if (cpu_isset(cpu, mask) &&
1115 !cpu_isset(cpu, timer_bcast_ipi)) {
1116 disable_APIC_timer();
1117 cpu_set(cpu, timer_bcast_ipi);
1120 EXPORT_SYMBOL(switch_APIC_timer_to_ipi);
1122 void switch_ipi_to_APIC_timer(void *cpumask)
1124 cpumask_t mask = *(cpumask_t *)cpumask;
1125 int cpu = smp_processor_id();
1127 if (cpu_isset(cpu, mask) &&
1128 cpu_isset(cpu, timer_bcast_ipi)) {
1129 cpu_clear(cpu, timer_bcast_ipi);
1130 enable_APIC_timer();
1133 EXPORT_SYMBOL(switch_ipi_to_APIC_timer);
1138 * Local timer interrupt handler. It does both profiling and
1139 * process statistics/rescheduling.
1141 * We do profiling in every local tick, statistics/rescheduling
1142 * happen only every 'profiling multiplier' ticks. The default
1143 * multiplier is 1 and it can be changed by writing the new multiplier
1144 * value into /proc/profile.
1147 inline void smp_local_timer_interrupt(struct pt_regs * regs)
1149 profile_tick(CPU_PROFILING, regs);
1151 update_process_times(user_mode_vm(regs));
1155 * We take the 'long' return path, and there every subsystem
1156 * grabs the apropriate locks (kernel lock/ irq lock).
1158 * we might want to decouple profiling from the 'long path',
1159 * and do the profiling totally in assembly.
1161 * Currently this isn't too much of an issue (performance wise),
1162 * we can take more than 100K local irqs per second on a 100 MHz P5.
1167 * Local APIC timer interrupt. This is the most natural way for doing
1168 * local interrupts, but local timer interrupts can be emulated by
1169 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1171 * [ if a single-CPU system runs an SMP kernel then we call the local
1172 * interrupt as well. Thus we cannot inline the local irq ... ]
1175 fastcall void smp_apic_timer_interrupt(struct pt_regs *regs)
1177 int cpu = smp_processor_id();
1180 * the NMI deadlock-detector uses this.
1182 per_cpu(irq_stat, cpu).apic_timer_irqs++;
1185 * NOTE! We'd better ACK the irq immediately,
1186 * because timer handling can be slow.
1190 * update_process_times() expects us to have done irq_enter().
1191 * Besides, if we don't timer interrupts ignore the global
1192 * interrupt lock, which is the WrongThing (tm) to do.
1195 smp_local_timer_interrupt(regs);
1200 static void up_apic_timer_interrupt_call(struct pt_regs *regs)
1202 int cpu = smp_processor_id();
1205 * the NMI deadlock-detector uses this.
1207 per_cpu(irq_stat, cpu).apic_timer_irqs++;
1209 smp_local_timer_interrupt(regs);
1213 void smp_send_timer_broadcast_ipi(struct pt_regs *regs)
1217 cpus_and(mask, cpu_online_map, timer_bcast_ipi);
1218 if (!cpus_empty(mask)) {
1220 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
1223 * We can directly call the apic timer interrupt handler
1224 * in UP case. Minus all irq related functions
1226 up_apic_timer_interrupt_call(regs);
1231 int setup_profiling_timer(unsigned int multiplier)
1237 * This interrupt should _never_ happen with our APIC/SMP architecture
1239 fastcall void smp_spurious_interrupt(struct pt_regs *regs)
1245 * Check if this really is a spurious interrupt and ACK it
1246 * if it is a vectored one. Just in case...
1247 * Spurious interrupts should not be ACKed.
1249 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1250 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1253 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1254 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
1255 smp_processor_id());
1260 * This interrupt should never happen with our APIC/SMP architecture
1263 fastcall void smp_error_interrupt(struct pt_regs *regs)
1265 unsigned long v, v1;
1268 /* First tickle the hardware, only then report what went on. -- REW */
1269 v = apic_read(APIC_ESR);
1270 apic_write(APIC_ESR, 0);
1271 v1 = apic_read(APIC_ESR);
1273 atomic_inc(&irq_err_count);
1275 /* Here is what the APIC error bits mean:
1278 2: Send accept error
1279 3: Receive accept error
1281 5: Send illegal vector
1282 6: Received illegal vector
1283 7: Illegal register address
1285 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1286 smp_processor_id(), v , v1);
1291 * This initializes the IO-APIC and APIC hardware if this is
1294 int __init APIC_init_uniprocessor (void)
1296 if (enable_local_apic < 0)
1297 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1299 if (!smp_found_config && !cpu_has_apic)
1303 * Complain if the BIOS pretends there is one.
1305 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1306 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1307 boot_cpu_physical_apicid);
1308 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1312 verify_local_APIC();
1316 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1320 #ifdef CONFIG_X86_IO_APIC
1321 if (smp_found_config)
1322 if (!skip_ioapic_setup && nr_ioapics)
1325 setup_boot_APIC_clock();