1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * linux/arch/i386/kernel/voyager_smp.c
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
12 #include <linux/module.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/mc146818rtc.h>
17 #include <linux/cache.h>
18 #include <linux/interrupt.h>
19 #include <linux/smp_lock.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/bootmem.h>
23 #include <linux/completion.h>
25 #include <asm/voyager.h>
28 #include <asm/pgalloc.h>
29 #include <asm/tlbflush.h>
30 #include <asm/arch_hooks.h>
32 /* TLB state -- visible externally, indexed physically */
33 DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };
35 /* CPU IRQ affinity -- set to all ones initially */
36 static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
38 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
39 * indexed physically */
40 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
41 EXPORT_SYMBOL(cpu_data);
43 /* physical ID of the CPU used to boot the system */
44 unsigned char boot_cpu_id;
46 /* The memory line addresses for the Quad CPIs */
47 struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
49 /* The masks for the Extended VIC processors, filled in by cat_init */
50 __u32 voyager_extended_vic_processors = 0;
52 /* Masks for the extended Quad processors which cannot be VIC booted */
53 __u32 voyager_allowed_boot_processors = 0;
55 /* The mask for the Quad Processors (both extended and non-extended) */
56 __u32 voyager_quad_processors = 0;
58 /* Total count of live CPUs, used in process.c to display
59 * the CPU information and in irq.c for the per CPU irq
60 * activity count. Finally exported by i386_ksyms.c */
61 static int voyager_extended_cpus = 1;
63 /* Have we found an SMP box - used by time.c to do the profiling
64 interrupt for timeslicing; do not set to 1 until the per CPU timer
65 interrupt is active */
66 int smp_found_config = 0;
68 /* Used for the invalidate map that's also checked in the spinlock */
69 static volatile unsigned long smp_invalidate_needed;
71 /* Bitmask of currently online CPUs - used by setup.c for
72 /proc/cpuinfo, visible externally but still physical */
73 cpumask_t cpu_online_map = CPU_MASK_NONE;
74 EXPORT_SYMBOL(cpu_online_map);
76 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
77 * by scheduler but indexed physically */
78 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
81 /* The internal functions */
82 static void send_CPI(__u32 cpuset, __u8 cpi);
83 static void ack_CPI(__u8 cpi);
84 static int ack_QIC_CPI(__u8 cpi);
85 static void ack_special_QIC_CPI(__u8 cpi);
86 static void ack_VIC_CPI(__u8 cpi);
87 static void send_CPI_allbutself(__u8 cpi);
88 static void enable_vic_irq(unsigned int irq);
89 static void disable_vic_irq(unsigned int irq);
90 static unsigned int startup_vic_irq(unsigned int irq);
91 static void enable_local_vic_irq(unsigned int irq);
92 static void disable_local_vic_irq(unsigned int irq);
93 static void before_handle_vic_irq(unsigned int irq);
94 static void after_handle_vic_irq(unsigned int irq);
95 static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
96 static void ack_vic_irq(unsigned int irq);
97 static void vic_enable_cpi(void);
98 static void do_boot_cpu(__u8 cpuid);
99 static void do_quad_bootstrap(void);
101 int hard_smp_processor_id(void);
102 int safe_smp_processor_id(void);
104 /* Inline functions */
106 send_one_QIC_CPI(__u8 cpu, __u8 cpi)
108 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
109 (smp_processor_id() << 16) + cpi;
113 send_QIC_CPI(__u32 cpuset, __u8 cpi)
117 for_each_online_cpu(cpu) {
118 if(cpuset & (1<<cpu)) {
120 if(!cpu_isset(cpu, cpu_online_map))
121 VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));
123 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
129 wrapper_smp_local_timer_interrupt(struct pt_regs *regs)
132 smp_local_timer_interrupt(regs);
137 send_one_CPI(__u8 cpu, __u8 cpi)
139 if(voyager_quad_processors & (1<<cpu))
140 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
142 send_CPI(1<<cpu, cpi);
146 send_CPI_allbutself(__u8 cpi)
148 __u8 cpu = smp_processor_id();
149 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
156 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
157 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
161 is_cpu_extended(void)
163 __u8 cpu = hard_smp_processor_id();
165 return(voyager_extended_vic_processors & (1<<cpu));
169 is_cpu_vic_boot(void)
171 __u8 cpu = hard_smp_processor_id();
173 return(voyager_extended_vic_processors
174 & voyager_allowed_boot_processors & (1<<cpu));
182 case VIC_CPU_BOOT_CPI:
183 if(is_cpu_quad() && !is_cpu_vic_boot())
190 /* These are slightly strange. Even on the Quad card,
191 * They are vectored as VIC CPIs */
193 ack_special_QIC_CPI(cpi);
198 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
203 /* local variables */
205 /* The VIC IRQ descriptors -- these look almost identical to the
206 * 8259 IRQs except that masks and things must be kept per processor
208 static struct hw_interrupt_type vic_irq_type = {
209 .typename = "VIC-level",
210 .startup = startup_vic_irq,
211 .shutdown = disable_vic_irq,
212 .enable = enable_vic_irq,
213 .disable = disable_vic_irq,
214 .ack = before_handle_vic_irq,
215 .end = after_handle_vic_irq,
216 .set_affinity = set_vic_irq_affinity,
219 /* used to count up as CPUs are brought on line (starts at 0) */
220 static int cpucount = 0;
222 /* steal a page from the bottom of memory for the trampoline and
223 * squirrel its address away here. This will be in kernel virtual
225 static __u32 trampoline_base;
227 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
228 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
229 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
230 static DEFINE_PER_CPU(int, prof_counter) = 1;
232 /* the map used to check if a CPU has booted */
233 static __u32 cpu_booted_map;
235 /* the synchronize flag used to hold all secondary CPUs spinning in
236 * a tight loop until the boot sequence is ready for them */
237 static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
239 /* This is for the new dynamic CPU boot code */
240 cpumask_t cpu_callin_map = CPU_MASK_NONE;
241 cpumask_t cpu_callout_map = CPU_MASK_NONE;
242 EXPORT_SYMBOL(cpu_callout_map);
243 cpumask_t cpu_possible_map = CPU_MASK_NONE;
244 EXPORT_SYMBOL(cpu_possible_map);
246 /* The per processor IRQ masks (these are usually kept in sync) */
247 static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
249 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
250 static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
252 /* Lock for enable/disable of VIC interrupts */
253 static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
255 /* The boot processor is correctly set up in PC mode when it
256 * comes up, but the secondaries need their master/slave 8259
257 * pairs initializing correctly */
259 /* Interrupt counters (per cpu) and total - used to try to
260 * even up the interrupt handling routines */
261 static long vic_intr_total = 0;
262 static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
263 static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
265 /* Since we can only use CPI0, we fake all the other CPIs */
266 static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
268 /* debugging routine to read the isr of the cpu's pic */
275 isr = inb(0xa0) << 8;
286 /* not a quad, no setup */
289 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
290 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
292 if(is_cpu_extended()) {
293 /* the QIC duplicate of the VIC base register */
294 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
295 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
297 /* FIXME: should set up the QIC timer and memory parity
298 * error vectors here */
305 outb(1, VIC_REDIRECT_REGISTER_1);
306 /* clear the claim registers for dynamic routing */
307 outb(0, VIC_CLAIM_REGISTER_0);
308 outb(0, VIC_CLAIM_REGISTER_1);
310 outb(0, VIC_PRIORITY_REGISTER);
311 /* Set the Primary and Secondary Microchannel vector
312 * bases to be the same as the ordinary interrupts
314 * FIXME: This would be more efficient using separate
316 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
317 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
318 /* Now initiallise the master PIC belonging to this CPU by
319 * sending the four ICWs */
321 /* ICW1: level triggered, ICW4 needed */
324 /* ICW2: vector base */
325 outb(FIRST_EXTERNAL_VECTOR, 0x21);
327 /* ICW3: slave at line 2 */
330 /* ICW4: 8086 mode */
333 /* now the same for the slave PIC */
335 /* ICW1: level trigger, ICW4 needed */
338 /* ICW2: slave vector base */
339 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
344 /* ICW4: 8086 mode */
349 do_quad_bootstrap(void)
351 if(is_cpu_quad() && is_cpu_vic_boot()) {
354 __u8 cpuid = hard_smp_processor_id();
356 local_irq_save(flags);
358 for(i = 0; i<4; i++) {
359 /* FIXME: this would be >>3 &0x7 on the 32 way */
360 if(((cpuid >> 2) & 0x03) == i)
361 /* don't lower our own mask! */
364 /* masquerade as local Quad CPU */
365 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
366 /* enable the startup CPI */
367 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
369 outb(0, QIC_PROCESSOR_ID);
371 local_irq_restore(flags);
376 /* Set up all the basic stuff: read the SMP config and make all the
377 * SMP information reflect only the boot cpu. All others will be
378 * brought on-line later. */
380 find_smp_config(void)
384 boot_cpu_id = hard_smp_processor_id();
386 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
388 /* initialize the CPU structures (moved from smp_boot_cpus) */
389 for(i=0; i<NR_CPUS; i++) {
390 cpu_irq_affinity[i] = ~0;
392 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
394 /* The boot CPU must be extended */
395 voyager_extended_vic_processors = 1<<boot_cpu_id;
396 /* initially, all of the first 8 cpu's can boot */
397 voyager_allowed_boot_processors = 0xff;
398 /* set up everything for just this CPU, we can alter
399 * this as we start the other CPUs later */
400 /* now get the CPU disposition from the extended CMOS */
401 cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
402 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
403 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
404 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
405 cpu_possible_map = phys_cpu_present_map;
406 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
407 /* Here we set up the VIC to enable SMP */
408 /* enable the CPIs by writing the base vector to their register */
409 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
410 outb(1, VIC_REDIRECT_REGISTER_1);
411 /* set the claim registers for static routing --- Boot CPU gets
412 * all interrupts untill all other CPUs started */
413 outb(0xff, VIC_CLAIM_REGISTER_0);
414 outb(0xff, VIC_CLAIM_REGISTER_1);
415 /* Set the Primary and Secondary Microchannel vector
416 * bases to be the same as the ordinary interrupts
418 * FIXME: This would be more efficient using separate
420 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
421 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
423 /* Finally tell the firmware that we're driving */
424 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
425 VOYAGER_SUS_IN_CONTROL_PORT);
427 current_thread_info()->cpu = boot_cpu_id;
431 * The bootstrap kernel entry code has set these up. Save them
432 * for a given CPU, id is physical */
434 smp_store_cpu_info(int id)
436 struct cpuinfo_x86 *c=&cpu_data[id];
443 /* set up the trampoline and return the physical address of the code */
445 setup_trampoline(void)
447 /* these two are global symbols in trampoline.S */
448 extern __u8 trampoline_end[];
449 extern __u8 trampoline_data[];
451 memcpy((__u8 *)trampoline_base, trampoline_data,
452 trampoline_end - trampoline_data);
453 return virt_to_phys((__u8 *)trampoline_base);
456 /* Routine initially called when a non-boot CPU is brought online */
458 start_secondary(void *unused)
460 __u8 cpuid = hard_smp_processor_id();
461 /* external functions not defined in the headers */
462 extern void calibrate_delay(void);
466 /* OK, we're in the routine */
467 ack_CPI(VIC_CPU_BOOT_CPI);
469 /* setup the 8259 master slave pair belonging to this CPU ---
470 * we won't actually receive any until the boot CPU
471 * relinquishes it's static routing mask */
476 if(is_cpu_quad() && !is_cpu_vic_boot()) {
477 /* clear the boot CPI */
480 dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
481 printk("read dummy %d\n", dummy);
484 /* lower the mask to receive CPIs */
487 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
489 /* enable interrupts */
492 /* get our bogomips */
495 /* save our processor parameters */
496 smp_store_cpu_info(cpuid);
498 /* if we're a quad, we may need to bootstrap other CPUs */
501 /* FIXME: this is rather a poor hack to prevent the CPU
502 * activating softirqs while it's supposed to be waiting for
503 * permission to proceed. Without this, the new per CPU stuff
504 * in the softirqs will fail */
506 cpu_set(cpuid, cpu_callin_map);
508 /* signal that we're done */
511 while (!cpu_isset(cpuid, smp_commenced_mask))
517 cpu_set(cpuid, cpu_online_map);
523 /* Routine to kick start the given CPU and wait for it to report ready
524 * (or timeout in startup). When this routine returns, the requested
525 * CPU is either fully running and configured or known to be dead.
527 * We call this routine sequentially 1 CPU at a time, so no need for
531 do_boot_cpu(__u8 cpu)
533 struct task_struct *idle;
536 int quad_boot = (1<<cpu) & voyager_quad_processors
537 & ~( voyager_extended_vic_processors
538 & voyager_allowed_boot_processors);
540 /* For the 486, we can't use the 4Mb page table trick, so
541 * must map a region of memory */
544 unsigned long *page_table_copies = (unsigned long *)
545 __get_free_page(GFP_KERNEL);
547 pgd_t orig_swapper_pg_dir0;
549 /* This is an area in head.S which was used to set up the
550 * initial kernel stack. We need to alter this to give the
551 * booting CPU a new stack (taken from its idle process) */
556 /* This is the format of the CPI IDT gate (in real mode) which
557 * we're hijacking to boot the CPU */
566 __u32 *hijack_vector;
567 __u32 start_phys_address = setup_trampoline();
569 /* There's a clever trick to this: The linux trampoline is
570 * compiled to begin at absolute location zero, so make the
571 * address zero but have the data segment selector compensate
572 * for the actual address */
573 hijack_source.idt.Offset = start_phys_address & 0x000F;
574 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
577 idle = fork_idle(cpu);
579 panic("failed fork for CPU%d", cpu);
580 idle->thread.eip = (unsigned long) start_secondary;
581 /* init_tasks (in sched.c) is indexed logically */
582 stack_start.esp = (void *) idle->thread.esp;
586 /* Note: Don't modify initial ss override */
587 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
588 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
589 hijack_source.idt.Offset, stack_start.esp));
590 /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently
591 * (so that the booting CPU can find start_32 */
592 orig_swapper_pg_dir0 = swapper_pg_dir[0];
594 if(page_table_copies == NULL)
595 panic("No free memory for 486 page tables\n");
596 for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++)
597 page_table_copies[i] = (i * PAGE_SIZE)
598 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
600 ((unsigned long *)swapper_pg_dir)[0] =
601 ((virt_to_phys(page_table_copies)) & PAGE_MASK)
602 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
604 ((unsigned long *)swapper_pg_dir)[0] =
605 (virt_to_phys(pg0) & PAGE_MASK)
606 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
610 printk("CPU %d: non extended Quad boot\n", cpu);
611 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4);
612 *hijack_vector = hijack_source.val;
614 printk("CPU%d: extended VIC boot\n", cpu);
615 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4);
616 *hijack_vector = hijack_source.val;
617 /* VIC errata, may also receive interrupt at this address */
618 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4);
619 *hijack_vector = hijack_source.val;
621 /* All non-boot CPUs start with interrupts fully masked. Need
622 * to lower the mask of the CPI we're about to send. We do
623 * this in the VIC by masquerading as the processor we're
624 * about to boot and lowering its interrupt mask */
625 local_irq_save(flags);
627 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
629 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
630 /* here we're altering registers belonging to `cpu' */
632 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
633 /* now go back to our original identity */
634 outb(boot_cpu_id, VIC_PROCESSOR_ID);
636 /* and boot the CPU */
638 send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);
641 local_irq_restore(flags);
643 /* now wait for it to become ready (or timeout) */
644 for(timeout = 0; timeout < 50000; timeout++) {
649 /* reset the page table */
650 swapper_pg_dir[0] = orig_swapper_pg_dir0;
653 free_page((unsigned long)page_table_copies);
656 if (cpu_booted_map) {
657 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
658 cpu, smp_processor_id()));
660 printk("CPU%d: ", cpu);
661 print_cpu_info(&cpu_data[cpu]);
663 cpu_set(cpu, cpu_callout_map);
664 cpu_set(cpu, cpu_present_map);
667 printk("CPU%d FAILED TO BOOT: ", cpu);
668 if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5)
671 printk("Not responding.\n");
682 /* CAT BUS initialisation must be done after the memory */
683 /* FIXME: The L4 has a catbus too, it just needs to be
684 * accessed in a totally different way */
685 if(voyager_level == 5) {
688 /* now that the cat has probed the Voyager System Bus, sanity
689 * check the cpu map */
690 if( ((voyager_quad_processors | voyager_extended_vic_processors)
691 & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
693 printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
695 } else if(voyager_level == 4)
696 voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
698 /* this sets up the idle task to run on the current cpu */
699 voyager_extended_cpus = 1;
700 /* Remove the global_irq_holder setting, it triggers a BUG() on
701 * schedule at the moment */
702 //global_irq_holder = boot_cpu_id;
704 /* FIXME: Need to do something about this but currently only works
705 * on CPUs with a tsc which none of mine have.
706 smp_tune_scheduling();
708 smp_store_cpu_info(boot_cpu_id);
709 printk("CPU%d: ", boot_cpu_id);
710 print_cpu_info(&cpu_data[boot_cpu_id]);
713 /* booting on a Quad CPU */
714 printk("VOYAGER SMP: Boot CPU is Quad\n");
719 /* enable our own CPIs */
722 cpu_set(boot_cpu_id, cpu_online_map);
723 cpu_set(boot_cpu_id, cpu_callout_map);
725 /* loop over all the extended VIC CPUs and boot them. The
726 * Quad CPUs must be bootstrapped by their extended VIC cpu */
727 for(i = 0; i < NR_CPUS; i++) {
728 if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
731 /* This udelay seems to be needed for the Quad boots
732 * don't remove unless you know what you're doing */
735 /* we could compute the total bogomips here, but why bother?,
736 * Code added from smpboot.c */
738 unsigned long bogosum = 0;
739 for (i = 0; i < NR_CPUS; i++)
740 if (cpu_isset(i, cpu_online_map))
741 bogosum += cpu_data[i].loops_per_jiffy;
742 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
745 (bogosum/(5000/HZ))%100);
747 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
748 printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);
749 /* that's it, switch to symmetric mode */
750 outb(0, VIC_PRIORITY_REGISTER);
751 outb(0, VIC_CLAIM_REGISTER_0);
752 outb(0, VIC_CLAIM_REGISTER_1);
754 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
757 /* Reload the secondary CPUs task structure (this function does not
760 initialize_secondary(void)
764 set_current(hard_get_current());
768 * We don't actually need to load the full TSS,
769 * basically just the stack pointer and the eip.
776 :"r" (current->thread.esp),"r" (current->thread.eip));
779 /* handle a Voyager SYS_INT -- If we don't, the base board will
782 * System interrupts occur because some problem was detected on the
783 * various busses. To find out what you have to probe all the
784 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
786 smp_vic_sys_interrupt(struct pt_regs *regs)
788 ack_CPI(VIC_SYS_INT);
789 printk("Voyager SYSTEM INTERRUPT\n");
792 /* Handle a voyager CMN_INT; These interrupts occur either because of
793 * a system status change or because a single bit memory error
794 * occurred. FIXME: At the moment, ignore all this. */
796 smp_vic_cmn_interrupt(struct pt_regs *regs)
798 static __u8 in_cmn_int = 0;
799 static DEFINE_SPINLOCK(cmn_int_lock);
801 /* common ints are broadcast, so make sure we only do this once */
802 _raw_spin_lock(&cmn_int_lock);
807 _raw_spin_unlock(&cmn_int_lock);
809 VDEBUG(("Voyager COMMON INTERRUPT\n"));
811 if(voyager_level == 5)
812 voyager_cat_do_common_interrupt();
814 _raw_spin_lock(&cmn_int_lock);
817 _raw_spin_unlock(&cmn_int_lock);
818 ack_CPI(VIC_CMN_INT);
822 * Reschedule call back. Nothing to do, all the work is done
823 * automatically when we return from the interrupt. */
825 smp_reschedule_interrupt(void)
830 static struct mm_struct * flush_mm;
831 static unsigned long flush_va;
832 static DEFINE_SPINLOCK(tlbstate_lock);
833 #define FLUSH_ALL 0xffffffff
836 * We cannot call mmdrop() because we are in interrupt context,
837 * instead update mm->cpu_vm_mask.
839 * We need to reload %cr3 since the page tables may be going
840 * away from under us..
843 leave_mm (unsigned long cpu)
845 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
847 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
848 load_cr3(swapper_pg_dir);
853 * Invalidate call-back
856 smp_invalidate_interrupt(void)
858 __u8 cpu = smp_processor_id();
860 if (!test_bit(cpu, &smp_invalidate_needed))
862 /* This will flood messages. Don't uncomment unless you see
863 * Problems with cross cpu invalidation
864 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
865 smp_processor_id()));
868 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
869 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
870 if (flush_va == FLUSH_ALL)
873 __flush_tlb_one(flush_va);
877 smp_mb__before_clear_bit();
878 clear_bit(cpu, &smp_invalidate_needed);
879 smp_mb__after_clear_bit();
882 /* All the new flush operations for 2.4 */
885 /* This routine is called with a physical cpu mask */
887 flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
894 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
896 if (cpumask & (1 << smp_processor_id()))
901 spin_lock(&tlbstate_lock);
905 atomic_set_mask(cpumask, &smp_invalidate_needed);
907 * We have to send the CPI only to
910 send_CPI(cpumask, VIC_INVALIDATE_CPI);
912 while (smp_invalidate_needed) {
915 printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
920 /* Uncomment only to debug invalidation problems
921 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
926 spin_unlock(&tlbstate_lock);
930 flush_tlb_current_task(void)
932 struct mm_struct *mm = current->mm;
933 unsigned long cpu_mask;
937 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
940 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
947 flush_tlb_mm (struct mm_struct * mm)
949 unsigned long cpu_mask;
953 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
955 if (current->active_mm == mm) {
959 leave_mm(smp_processor_id());
962 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
967 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
969 struct mm_struct *mm = vma->vm_mm;
970 unsigned long cpu_mask;
974 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
975 if (current->active_mm == mm) {
979 leave_mm(smp_processor_id());
983 flush_tlb_others(cpu_mask, mm, va);
987 EXPORT_SYMBOL(flush_tlb_page);
989 /* enable the requested IRQs */
991 smp_enable_irq_interrupt(void)
994 __u8 cpu = get_cpu();
996 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
997 vic_irq_enable_mask[cpu]));
999 spin_lock(&vic_irq_lock);
1000 for(irq = 0; irq < 16; irq++) {
1001 if(vic_irq_enable_mask[cpu] & (1<<irq))
1002 enable_local_vic_irq(irq);
1004 vic_irq_enable_mask[cpu] = 0;
1005 spin_unlock(&vic_irq_lock);
1007 put_cpu_no_resched();
1011 * CPU halt call-back
1014 smp_stop_cpu_function(void *dummy)
1016 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
1017 cpu_clear(smp_processor_id(), cpu_online_map);
1018 local_irq_disable();
1023 static DEFINE_SPINLOCK(call_lock);
1025 struct call_data_struct {
1026 void (*func) (void *info);
1028 volatile unsigned long started;
1029 volatile unsigned long finished;
1033 static struct call_data_struct * call_data;
1035 /* execute a thread on a new CPU. The function to be called must be
1036 * previously set up. This is used to schedule a function for
1037 * execution on all CPU's - set up the function then broadcast a
1038 * function_interrupt CPI to come here on each CPU */
1040 smp_call_function_interrupt(void)
1042 void (*func) (void *info) = call_data->func;
1043 void *info = call_data->info;
1044 /* must take copy of wait because call_data may be replaced
1045 * unless the function is waiting for us to finish */
1046 int wait = call_data->wait;
1047 __u8 cpu = smp_processor_id();
1050 * Notify initiating CPU that I've grabbed the data and am
1051 * about to execute the function
1054 if(!test_and_clear_bit(cpu, &call_data->started)) {
1055 /* If the bit wasn't set, this could be a replay */
1056 printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);
1060 * At this point the info structure may be out of scope unless wait==1
1067 clear_bit(cpu, &call_data->finished);
1071 /* Call this function on all CPUs using the function_interrupt above
1072 <func> The function to run. This must be fast and non-blocking.
1073 <info> An arbitrary pointer to pass to the function.
1074 <retry> If true, keep retrying until ready.
1075 <wait> If true, wait until function has completed on other CPUs.
1076 [RETURNS] 0 on success, else a negative status code. Does not return until
1077 remote CPUs are nearly ready to execute <<func>> or are or have executed.
1080 smp_call_function (void (*func) (void *info), void *info, int retry,
1083 struct call_data_struct data;
1084 __u32 mask = cpus_addr(cpu_online_map)[0];
1086 mask &= ~(1<<smp_processor_id());
1091 /* Can deadlock when called with interrupts disabled */
1092 WARN_ON(irqs_disabled());
1096 data.started = mask;
1099 data.finished = mask;
1101 spin_lock(&call_lock);
1104 /* Send a message to all other CPUs and wait for them to respond */
1105 send_CPI_allbutself(VIC_CALL_FUNCTION_CPI);
1107 /* Wait for response */
1108 while (data.started)
1112 while (data.finished)
1115 spin_unlock(&call_lock);
1119 EXPORT_SYMBOL(smp_call_function);
1121 /* Sorry about the name. In an APIC based system, the APICs
1122 * themselves are programmed to send a timer interrupt. This is used
1123 * by linux to reschedule the processor. Voyager doesn't have this,
1124 * so we use the system clock to interrupt one processor, which in
1125 * turn, broadcasts a timer CPI to all the others --- we receive that
1126 * CPI here. We don't use this actually for counting so losing
1127 * ticks doesn't matter
1129 * FIXME: For those CPU's which actually have a local APIC, we could
1130 * try to use it to trigger this interrupt instead of having to
1131 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1132 * no local APIC, so I can't do this
1134 * This function is currently a placeholder and is unused in the code */
1136 smp_apic_timer_interrupt(struct pt_regs *regs)
1138 wrapper_smp_local_timer_interrupt(regs);
1141 /* All of the QUAD interrupt GATES */
1143 smp_qic_timer_interrupt(struct pt_regs *regs)
1145 ack_QIC_CPI(QIC_TIMER_CPI);
1146 wrapper_smp_local_timer_interrupt(regs);
1150 smp_qic_invalidate_interrupt(struct pt_regs *regs)
1152 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1153 smp_invalidate_interrupt();
1157 smp_qic_reschedule_interrupt(struct pt_regs *regs)
1159 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1160 smp_reschedule_interrupt();
1164 smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1166 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1167 smp_enable_irq_interrupt();
1171 smp_qic_call_function_interrupt(struct pt_regs *regs)
1173 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1174 smp_call_function_interrupt();
1178 smp_vic_cpi_interrupt(struct pt_regs *regs)
1180 __u8 cpu = smp_processor_id();
1183 ack_QIC_CPI(VIC_CPI_LEVEL0);
1185 ack_VIC_CPI(VIC_CPI_LEVEL0);
1187 if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1188 wrapper_smp_local_timer_interrupt(regs);
1189 if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1190 smp_invalidate_interrupt();
1191 if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1192 smp_reschedule_interrupt();
1193 if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1194 smp_enable_irq_interrupt();
1195 if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1196 smp_call_function_interrupt();
1200 do_flush_tlb_all(void* info)
1202 unsigned long cpu = smp_processor_id();
1205 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1210 /* flush the TLB of every active CPU in the system */
1214 on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1217 /* used to set up the trampoline for other CPUs when the memory manager
1220 smp_alloc_memory(void)
1222 trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);
1223 if(__pa(trampoline_base) >= 0x93000)
1227 /* send a reschedule CPI to one CPU by physical CPU number*/
1229 smp_send_reschedule(int cpu)
1231 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1236 hard_smp_processor_id(void)
1239 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1240 if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1241 return cpumask & 0x1F;
1243 for(i = 0; i < 8; i++) {
1244 if(cpumask & (1<<i))
1247 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1252 safe_smp_processor_id(void)
1254 return hard_smp_processor_id();
1257 /* broadcast a halt to all other CPUs */
1261 smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1264 /* this function is triggered in time.c when a clock tick fires
1265 * we need to re-broadcast the tick to all CPUs */
1267 smp_vic_timer_interrupt(struct pt_regs *regs)
1269 send_CPI_allbutself(VIC_TIMER_CPI);
1270 smp_local_timer_interrupt(regs);
1273 /* local (per CPU) timer interrupt. It does both profiling and
1274 * process statistics/rescheduling.
1276 * We do profiling in every local tick, statistics/rescheduling
1277 * happen only every 'profiling multiplier' ticks. The default
1278 * multiplier is 1 and it can be changed by writing the new multiplier
1279 * value into /proc/profile.
1282 smp_local_timer_interrupt(struct pt_regs * regs)
1284 int cpu = smp_processor_id();
1287 profile_tick(CPU_PROFILING, regs);
1288 if (--per_cpu(prof_counter, cpu) <= 0) {
1290 * The multiplier may have changed since the last time we got
1291 * to this point as a result of the user writing to
1292 * /proc/profile. In this case we need to adjust the APIC
1293 * timer accordingly.
1295 * Interrupts are already masked off at this point.
1297 per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);
1298 if (per_cpu(prof_counter, cpu) !=
1299 per_cpu(prof_old_multiplier, cpu)) {
1300 /* FIXME: need to update the vic timer tick here */
1301 per_cpu(prof_old_multiplier, cpu) =
1302 per_cpu(prof_counter, cpu);
1305 update_process_times(user_mode_vm(regs));
1308 if( ((1<<cpu) & voyager_extended_vic_processors) == 0)
1309 /* only extended VIC processors participate in
1310 * interrupt distribution */
1314 * We take the 'long' return path, and there every subsystem
1315 * grabs the apropriate locks (kernel lock/ irq lock).
1317 * we might want to decouple profiling from the 'long path',
1318 * and do the profiling totally in assembly.
1320 * Currently this isn't too much of an issue (performance wise),
1321 * we can take more than 100K local irqs per second on a 100 MHz P5.
1324 if((++vic_tick[cpu] & 0x7) != 0)
1326 /* get here every 16 ticks (about every 1/6 of a second) */
1328 /* Change our priority to give someone else a chance at getting
1329 * the IRQ. The algorithm goes like this:
1331 * In the VIC, the dynamically routed interrupt is always
1332 * handled by the lowest priority eligible (i.e. receiving
1333 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1334 * lowest processor number gets it.
1336 * The priority of a CPU is controlled by a special per-CPU
1337 * VIC priority register which is 3 bits wide 0 being lowest
1338 * and 7 highest priority..
1340 * Therefore we subtract the average number of interrupts from
1341 * the number we've fielded. If this number is negative, we
1342 * lower the activity count and if it is positive, we raise
1345 * I'm afraid this still leads to odd looking interrupt counts:
1346 * the totals are all roughly equal, but the individual ones
1347 * look rather skewed.
1349 * FIXME: This algorithm is total crap when mixed with SMP
1350 * affinity code since we now try to even up the interrupt
1351 * counts when an affinity binding is keeping them on a
1353 weight = (vic_intr_count[cpu]*voyager_extended_cpus
1354 - vic_intr_total) >> 4;
1361 outb((__u8)weight, VIC_PRIORITY_REGISTER);
1363 #ifdef VOYAGER_DEBUG
1364 if((vic_tick[cpu] & 0xFFF) == 0) {
1365 /* print this message roughly every 25 secs */
1366 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1367 cpu, vic_tick[cpu], weight);
1372 /* setup the profiling timer */
1374 setup_profiling_timer(unsigned int multiplier)
1382 * Set the new multiplier for each CPU. CPUs don't start using the
1383 * new values until the next timer interrupt in which they do process
1386 for (i = 0; i < NR_CPUS; ++i)
1387 per_cpu(prof_multiplier, i) = multiplier;
1393 /* The CPIs are handled in the per cpu 8259s, so they must be
1394 * enabled to be received: FIX: enabling the CPIs in the early
1395 * boot sequence interferes with bug checking; enable them later
1397 #define VIC_SET_GATE(cpi, vector) \
1398 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1399 #define QIC_SET_GATE(cpi, vector) \
1400 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1407 /* initialize the per cpu irq mask to all disabled */
1408 for(i = 0; i < NR_CPUS; i++)
1409 vic_irq_mask[i] = 0xFFFF;
1411 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1413 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1414 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1416 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1417 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1418 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1419 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1420 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1423 /* now put the VIC descriptor into the first 48 IRQs
1425 * This is for later: first 16 correspond to PC IRQs; next 16
1426 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1427 for(i = 0; i < 48; i++)
1428 irq_desc[i].chip = &vic_irq_type;
1431 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1432 * processor to receive CPI */
1434 send_CPI(__u32 cpuset, __u8 cpi)
1437 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1439 if(cpi < VIC_START_FAKE_CPI) {
1440 /* fake CPI are only used for booting, so send to the
1441 * extended quads as well---Quads must be VIC booted */
1442 outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);
1446 send_QIC_CPI(quad_cpuset, cpi);
1447 cpuset &= ~quad_cpuset;
1448 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1451 for_each_online_cpu(cpu) {
1452 if(cpuset & (1<<cpu))
1453 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1456 outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1459 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1460 * set the cache line to shared by reading it.
1462 * DON'T make this inline otherwise the cache line read will be
1466 ack_QIC_CPI(__u8 cpi) {
1467 __u8 cpu = hard_smp_processor_id();
1471 outb(1<<cpi, QIC_INTERRUPT_CLEAR1);
1472 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1476 ack_special_QIC_CPI(__u8 cpi)
1480 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1483 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1486 /* also clear at the VIC, just in case (nop for non-extended proc) */
1490 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1492 ack_VIC_CPI(__u8 cpi)
1494 #ifdef VOYAGER_DEBUG
1495 unsigned long flags;
1497 __u8 cpu = smp_processor_id();
1499 local_irq_save(flags);
1500 isr = vic_read_isr();
1501 if((isr & (1<<(cpi &7))) == 0) {
1502 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1505 /* send specific EOI; the two system interrupts have
1506 * bit 4 set for a separate vector but behave as the
1507 * corresponding 3 bit intr */
1508 outb_p(0x60|(cpi & 7),0x20);
1510 #ifdef VOYAGER_DEBUG
1511 if((vic_read_isr() & (1<<(cpi &7))) != 0) {
1512 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1514 local_irq_restore(flags);
1518 /* cribbed with thanks from irq.c */
1519 #define __byte(x,y) (((unsigned char *)&(y))[x])
1520 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1521 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1524 startup_vic_irq(unsigned int irq)
1526 enable_vic_irq(irq);
1531 /* The enable and disable routines. This is where we run into
1532 * conflicting architectural philosophy. Fundamentally, the voyager
1533 * architecture does not expect to have to disable interrupts globally
1534 * (the IRQ controllers belong to each CPU). The processor masquerade
1535 * which is used to start the system shouldn't be used in a running OS
1536 * since it will cause great confusion if two separate CPUs drive to
1537 * the same IRQ controller (I know, I've tried it).
1539 * The solution is a variant on the NCR lazy SPL design:
1541 * 1) To disable an interrupt, do nothing (other than set the
1542 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1544 * 2) If the interrupt dares to come in, raise the local mask against
1545 * it (this will result in all the CPU masks being raised
1548 * 3) To enable the interrupt, lower the mask on the local CPU and
1549 * broadcast an Interrupt enable CPI which causes all other CPUs to
1550 * adjust their masks accordingly. */
1553 enable_vic_irq(unsigned int irq)
1555 /* linux doesn't to processor-irq affinity, so enable on
1556 * all CPUs we know about */
1557 int cpu = smp_processor_id(), real_cpu;
1558 __u16 mask = (1<<irq);
1559 __u32 processorList = 0;
1560 unsigned long flags;
1562 VDEBUG(("VOYAGER: enable_vic_irq(%d) CPU%d affinity 0x%lx\n",
1563 irq, cpu, cpu_irq_affinity[cpu]));
1564 spin_lock_irqsave(&vic_irq_lock, flags);
1565 for_each_online_cpu(real_cpu) {
1566 if(!(voyager_extended_vic_processors & (1<<real_cpu)))
1568 if(!(cpu_irq_affinity[real_cpu] & mask)) {
1569 /* irq has no affinity for this CPU, ignore */
1572 if(real_cpu == cpu) {
1573 enable_local_vic_irq(irq);
1575 else if(vic_irq_mask[real_cpu] & mask) {
1576 vic_irq_enable_mask[real_cpu] |= mask;
1577 processorList |= (1<<real_cpu);
1580 spin_unlock_irqrestore(&vic_irq_lock, flags);
1582 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1586 disable_vic_irq(unsigned int irq)
1588 /* lazy disable, do nothing */
1592 enable_local_vic_irq(unsigned int irq)
1594 __u8 cpu = smp_processor_id();
1595 __u16 mask = ~(1 << irq);
1596 __u16 old_mask = vic_irq_mask[cpu];
1598 vic_irq_mask[cpu] &= mask;
1599 if(vic_irq_mask[cpu] == old_mask)
1602 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1606 outb_p(cached_A1(cpu),0xA1);
1610 outb_p(cached_21(cpu),0x21);
1616 disable_local_vic_irq(unsigned int irq)
1618 __u8 cpu = smp_processor_id();
1619 __u16 mask = (1 << irq);
1620 __u16 old_mask = vic_irq_mask[cpu];
1625 vic_irq_mask[cpu] |= mask;
1626 if(old_mask == vic_irq_mask[cpu])
1629 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1633 outb_p(cached_A1(cpu),0xA1);
1637 outb_p(cached_21(cpu),0x21);
1642 /* The VIC is level triggered, so the ack can only be issued after the
1643 * interrupt completes. However, we do Voyager lazy interrupt
1644 * handling here: It is an extremely expensive operation to mask an
1645 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1646 * this interrupt actually comes in, then we mask and ack here to push
1647 * the interrupt off to another CPU */
1649 before_handle_vic_irq(unsigned int irq)
1651 irq_desc_t *desc = irq_desc + irq;
1652 __u8 cpu = smp_processor_id();
1654 _raw_spin_lock(&vic_irq_lock);
1656 vic_intr_count[cpu]++;
1658 if(!(cpu_irq_affinity[cpu] & (1<<irq))) {
1659 /* The irq is not in our affinity mask, push it off
1660 * onto another CPU */
1661 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1663 disable_local_vic_irq(irq);
1664 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1665 * actually calling the interrupt routine */
1666 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1667 } else if(desc->status & IRQ_DISABLED) {
1668 /* Damn, the interrupt actually arrived, do the lazy
1669 * disable thing. The interrupt routine in irq.c will
1670 * not handle a IRQ_DISABLED interrupt, so nothing more
1671 * need be done here */
1672 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1674 disable_local_vic_irq(irq);
1675 desc->status |= IRQ_REPLAY;
1677 desc->status &= ~IRQ_REPLAY;
1680 _raw_spin_unlock(&vic_irq_lock);
1683 /* Finish the VIC interrupt: basically mask */
1685 after_handle_vic_irq(unsigned int irq)
1687 irq_desc_t *desc = irq_desc + irq;
1689 _raw_spin_lock(&vic_irq_lock);
1691 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1692 #ifdef VOYAGER_DEBUG
1696 desc->status = status;
1697 if ((status & IRQ_DISABLED))
1698 disable_local_vic_irq(irq);
1699 #ifdef VOYAGER_DEBUG
1700 /* DEBUG: before we ack, check what's in progress */
1701 isr = vic_read_isr();
1702 if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {
1704 __u8 cpu = smp_processor_id();
1706 int mask; /* Um... initialize me??? --RR */
1708 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1710 for_each_possible_cpu(real_cpu, mask) {
1712 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1714 isr = vic_read_isr();
1715 if(isr & (1<<irq)) {
1716 printk("VOYAGER SMP: CPU%d ack irq %d\n",
1720 outb(cpu, VIC_PROCESSOR_ID);
1723 #endif /* VOYAGER_DEBUG */
1724 /* as soon as we ack, the interrupt is eligible for
1725 * receipt by another CPU so everything must be in
1728 if(status & IRQ_REPLAY) {
1729 /* replay is set if we disable the interrupt
1730 * in the before_handle_vic_irq() routine, so
1731 * clear the in progress bit here to allow the
1732 * next CPU to handle this correctly */
1733 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1735 #ifdef VOYAGER_DEBUG
1736 isr = vic_read_isr();
1737 if((isr & (1<<irq)) != 0)
1738 printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1740 #endif /* VOYAGER_DEBUG */
1742 _raw_spin_unlock(&vic_irq_lock);
1744 /* All code after this point is out of the main path - the IRQ
1745 * may be intercepted by another CPU if reasserted */
1749 /* Linux processor - interrupt affinity manipulations.
1751 * For each processor, we maintain a 32 bit irq affinity mask.
1752 * Initially it is set to all 1's so every processor accepts every
1753 * interrupt. In this call, we change the processor's affinity mask:
1755 * Change from enable to disable:
1757 * If the interrupt ever comes in to the processor, we will disable it
1758 * and ack it to push it off to another CPU, so just accept the mask here.
1760 * Change from disable to enable:
1762 * change the mask and then do an interrupt enable CPI to re-enable on
1763 * the selected processors */
1766 set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1768 /* Only extended processors handle interrupts */
1769 unsigned long real_mask;
1770 unsigned long irq_mask = 1 << irq;
1773 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1775 if(cpus_addr(mask)[0] == 0)
1776 /* can't have no cpu's to accept the interrupt -- extremely
1777 * bad things will happen */
1781 /* can't change the affinity of the timer IRQ. This
1782 * is due to the constraint in the voyager
1783 * architecture that the CPI also comes in on and IRQ
1784 * line and we have chosen IRQ0 for this. If you
1785 * raise the mask on this interrupt, the processor
1786 * will no-longer be able to accept VIC CPIs */
1790 /* You can only have 32 interrupts in a voyager system
1791 * (and 32 only if you have a secondary microchannel
1795 for_each_online_cpu(cpu) {
1796 unsigned long cpu_mask = 1 << cpu;
1798 if(cpu_mask & real_mask) {
1799 /* enable the interrupt for this cpu */
1800 cpu_irq_affinity[cpu] |= irq_mask;
1802 /* disable the interrupt for this cpu */
1803 cpu_irq_affinity[cpu] &= ~irq_mask;
1806 /* this is magic, we now have the correct affinity maps, so
1807 * enable the interrupt. This will send an enable CPI to
1808 * those cpu's who need to enable it in their local masks,
1809 * causing them to correct for the new affinity . If the
1810 * interrupt is currently globally disabled, it will simply be
1811 * disabled again as it comes in (voyager lazy disable). If
1812 * the affinity map is tightened to disable the interrupt on a
1813 * cpu, it will be pushed off when it comes in */
1814 enable_vic_irq(irq);
1818 ack_vic_irq(unsigned int irq)
1821 outb(0x62,0x20); /* Specific EOI to cascade */
1822 outb(0x60|(irq & 7),0xA0);
1824 outb(0x60 | (irq & 7),0x20);
1828 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1829 * but are not vectored by it. This means that the 8259 mask must be
1830 * lowered to receive them */
1832 vic_enable_cpi(void)
1834 __u8 cpu = smp_processor_id();
1836 /* just take a copy of the current mask (nop for boot cpu) */
1837 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1839 enable_local_vic_irq(VIC_CPI_LEVEL0);
1840 enable_local_vic_irq(VIC_CPI_LEVEL1);
1841 /* for sys int and cmn int */
1842 enable_local_vic_irq(7);
1845 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1846 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1847 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1848 cpu, QIC_CPI_ENABLE));
1851 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1852 cpu, vic_irq_mask[cpu]));
1858 int old_cpu = smp_processor_id(), cpu;
1860 /* dump the interrupt masks of each processor */
1861 for_each_online_cpu(cpu) {
1862 __u16 imr, isr, irr;
1863 unsigned long flags;
1865 local_irq_save(flags);
1866 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1867 imr = (inb(0xa1) << 8) | inb(0x21);
1869 irr = inb(0xa0) << 8;
1873 isr = inb(0xa0) << 8;
1876 outb(old_cpu, VIC_PROCESSOR_ID);
1877 local_irq_restore(flags);
1878 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1879 cpu, vic_irq_mask[cpu], imr, irr, isr);
1881 /* These lines are put in to try to unstick an un ack'd irq */
1884 for(irq=0; irq<16; irq++) {
1885 if(isr & (1<<irq)) {
1886 printk("\tCPU%d: ack irq %d\n",
1888 local_irq_save(flags);
1889 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1892 outb(old_cpu, VIC_PROCESSOR_ID);
1893 local_irq_restore(flags);
1902 smp_voyager_power_off(void *dummy)
1904 if(smp_processor_id() == boot_cpu_id)
1905 voyager_power_off();
1907 smp_stop_cpu_function(NULL);
1911 smp_prepare_cpus(unsigned int max_cpus)
1913 /* FIXME: ignore max_cpus for now */
1917 void __devinit smp_prepare_boot_cpu(void)
1919 cpu_set(smp_processor_id(), cpu_online_map);
1920 cpu_set(smp_processor_id(), cpu_callout_map);
1921 cpu_set(smp_processor_id(), cpu_possible_map);
1922 cpu_set(smp_processor_id(), cpu_present_map);
1926 __cpu_up(unsigned int cpu)
1928 /* This only works at boot for x86. See "rewrite" above. */
1929 if (cpu_isset(cpu, smp_commenced_mask))
1932 /* In case one didn't come up */
1933 if (!cpu_isset(cpu, cpu_callin_map))
1935 /* Unleash the CPU! */
1936 cpu_set(cpu, smp_commenced_mask);
1937 while (!cpu_isset(cpu, cpu_online_map))
1943 smp_cpus_done(unsigned int max_cpus)
1949 smp_setup_processor_id(void)
1951 current_thread_info()->cpu = hard_smp_processor_id();