2 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
3 * Copyright (C) 2004 Intel Corp.
5 * This code is released under the GNU General Public License version 2.
9 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/acpi.h>
18 /* aperture is up to 256MB but BIOS may reserve less */
19 #define MMCONFIG_APER_MIN (2 * 1024*1024)
20 #define MMCONFIG_APER_MAX (256 * 1024*1024)
22 /* Assume systems with more busses have correct MCFG */
23 #define MAX_CHECK_BUS 16
25 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
27 /* The base address of the last MMCONFIG device accessed */
28 static u32 mmcfg_last_accessed_device;
30 static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);
33 * Functions for accessing PCI configuration space with MMCONFIG accesses
35 static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
38 struct acpi_table_mcfg_config *cfg;
40 if (seg == 0 && bus < MAX_CHECK_BUS &&
41 test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots))
46 if (cfg_num >= pci_mmcfg_config_num) {
49 cfg = &pci_mmcfg_config[cfg_num];
50 if (cfg->pci_segment_group_number != seg)
52 if ((cfg->start_bus_number <= bus) &&
53 (cfg->end_bus_number >= bus))
54 return cfg->base_address;
57 /* Handle more broken MCFG tables on Asus etc.
58 They only contain a single entry for bus 0-0. Assume
59 this applies to all busses. */
60 cfg = &pci_mmcfg_config[0];
61 if (pci_mmcfg_config_num == 1 &&
62 cfg->pci_segment_group_number == 0 &&
63 (cfg->start_bus_number | cfg->end_bus_number) == 0)
64 return cfg->base_address;
66 /* Fall back to type 0 */
71 * This is always called under pci_config_lock
73 static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
75 u32 dev_base = base | (bus << 20) | (devfn << 12);
76 if (dev_base != mmcfg_last_accessed_device) {
77 mmcfg_last_accessed_device = dev_base;
78 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
82 static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
83 unsigned int devfn, int reg, int len, u32 *value)
88 if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
93 base = get_base_addr(seg, bus, devfn);
95 return pci_conf1_read(seg,bus,devfn,reg,len,value);
97 spin_lock_irqsave(&pci_config_lock, flags);
99 pci_exp_set_dev_base(base, bus, devfn);
103 *value = readb(mmcfg_virt_addr + reg);
106 *value = readw(mmcfg_virt_addr + reg);
109 *value = readl(mmcfg_virt_addr + reg);
113 spin_unlock_irqrestore(&pci_config_lock, flags);
118 static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
119 unsigned int devfn, int reg, int len, u32 value)
124 if ((bus > 255) || (devfn > 255) || (reg > 4095))
127 base = get_base_addr(seg, bus, devfn);
129 return pci_conf1_write(seg,bus,devfn,reg,len,value);
131 spin_lock_irqsave(&pci_config_lock, flags);
133 pci_exp_set_dev_base(base, bus, devfn);
137 writeb(value, mmcfg_virt_addr + reg);
140 writew(value, mmcfg_virt_addr + reg);
143 writel(value, mmcfg_virt_addr + reg);
147 spin_unlock_irqrestore(&pci_config_lock, flags);
152 static struct pci_raw_ops pci_mmcfg = {
153 .read = pci_mmcfg_read,
154 .write = pci_mmcfg_write,
158 static __init void pci_mmcfg_insert_resources(void)
160 #define PCI_MMCFG_RESOURCE_NAME_LEN 19
162 struct resource *res;
166 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
167 pci_mmcfg_config_num, GFP_KERNEL);
170 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
174 names = (void *)&res[pci_mmcfg_config_num];
175 for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
176 num_buses = pci_mmcfg_config[i].end_bus_number -
177 pci_mmcfg_config[i].start_bus_number + 1;
179 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
180 pci_mmcfg_config[i].pci_segment_group_number);
181 res->start = pci_mmcfg_config[i].base_address;
182 res->end = res->start + (num_buses << 20) - 1;
183 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
184 insert_resource(&iomem_resource, res);
185 names += PCI_MMCFG_RESOURCE_NAME_LEN;
189 /* K8 systems have some devices (typically in the builtin northbridge)
190 that are only accessible using type1
191 Normally this can be expressed in the MCFG by not listing them
192 and assigning suitable _SEGs, but this isn't implemented in some BIOS.
193 Instead try to discover all devices on bus 0 that are unreachable using MM
194 and fallback for them. */
195 static __init void unreachable_devices(void)
200 for (k = 0; k < MAX_CHECK_BUS; k++) {
201 for (i = 0; i < 32; i++) {
205 pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1);
206 if (val1 == 0xffffffff)
209 /* Locking probably not needed, but safer */
210 spin_lock_irqsave(&pci_config_lock, flags);
211 addr = get_base_addr(0, k, PCI_DEVFN(i, 0));
213 pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0));
215 readl((u32 __iomem *)mmcfg_virt_addr) != val1) {
216 set_bit(i + 32*k, fallback_slots);
218 "PCI: No mmconfig possible on %x:%x\n", k, i);
220 spin_unlock_irqrestore(&pci_config_lock, flags);
227 void __init pci_mmcfg_init(int type)
229 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
232 acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
233 if ((pci_mmcfg_config_num == 0) ||
234 (pci_mmcfg_config == NULL) ||
235 (pci_mmcfg_config[0].base_address == 0))
238 /* Only do this check when type 1 works. If it doesn't work
239 assume we run on a Mac and always use MCFG */
240 if (type == 1 && !e820_all_mapped(pci_mmcfg_config[0].base_address,
241 pci_mmcfg_config[0].base_address + MMCONFIG_APER_MIN,
243 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %x is not E820-reserved\n",
244 pci_mmcfg_config[0].base_address);
245 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
249 printk(KERN_INFO "PCI: Using MMCONFIG\n");
250 raw_pci_ops = &pci_mmcfg;
251 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
253 unreachable_devices();
254 pci_mmcfg_insert_resources();