2 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
3 * Copyright (C) 2004 Intel Corp.
5 * This code is released under the GNU General Public License version 2.
9 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/acpi.h>
18 #define MMCONFIG_APER_SIZE (256*1024*1024)
20 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
22 /* The base address of the last MMCONFIG device accessed */
23 static u32 mmcfg_last_accessed_device;
25 static DECLARE_BITMAP(fallback_slots, 32);
28 * Functions for accessing PCI configuration space with MMCONFIG accesses
30 static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
33 struct acpi_table_mcfg_config *cfg;
35 if (seg == 0 && bus == 0 &&
36 test_bit(PCI_SLOT(devfn), fallback_slots))
41 if (cfg_num >= pci_mmcfg_config_num) {
44 cfg = &pci_mmcfg_config[cfg_num];
45 if (cfg->pci_segment_group_number != seg)
47 if ((cfg->start_bus_number <= bus) &&
48 (cfg->end_bus_number >= bus))
49 return cfg->base_address;
52 /* Handle more broken MCFG tables on Asus etc.
53 They only contain a single entry for bus 0-0. Assume
54 this applies to all busses. */
55 cfg = &pci_mmcfg_config[0];
56 if (pci_mmcfg_config_num == 1 &&
57 cfg->pci_segment_group_number == 0 &&
58 (cfg->start_bus_number | cfg->end_bus_number) == 0)
59 return cfg->base_address;
61 /* Fall back to type 0 */
65 static inline void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
67 u32 dev_base = base | (bus << 20) | (devfn << 12);
68 if (dev_base != mmcfg_last_accessed_device) {
69 mmcfg_last_accessed_device = dev_base;
70 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
74 static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
75 unsigned int devfn, int reg, int len, u32 *value)
80 if (!value || (bus > 255) || (devfn > 255) || (reg > 4095))
83 base = get_base_addr(seg, bus, devfn);
85 return pci_conf1_read(seg,bus,devfn,reg,len,value);
87 spin_lock_irqsave(&pci_config_lock, flags);
89 pci_exp_set_dev_base(base, bus, devfn);
93 *value = readb(mmcfg_virt_addr + reg);
96 *value = readw(mmcfg_virt_addr + reg);
99 *value = readl(mmcfg_virt_addr + reg);
103 spin_unlock_irqrestore(&pci_config_lock, flags);
108 static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
109 unsigned int devfn, int reg, int len, u32 value)
114 if ((bus > 255) || (devfn > 255) || (reg > 4095))
117 base = get_base_addr(seg, bus, devfn);
119 return pci_conf1_write(seg,bus,devfn,reg,len,value);
121 spin_lock_irqsave(&pci_config_lock, flags);
123 pci_exp_set_dev_base(base, bus, devfn);
127 writeb(value, mmcfg_virt_addr + reg);
130 writew(value, mmcfg_virt_addr + reg);
133 writel(value, mmcfg_virt_addr + reg);
137 spin_unlock_irqrestore(&pci_config_lock, flags);
142 static struct pci_raw_ops pci_mmcfg = {
143 .read = pci_mmcfg_read,
144 .write = pci_mmcfg_write,
147 /* K8 systems have some devices (typically in the builtin northbridge)
148 that are only accessible using type1
149 Normally this can be expressed in the MCFG by not listing them
150 and assigning suitable _SEGs, but this isn't implemented in some BIOS.
151 Instead try to discover all devices on bus 0 that are unreachable using MM
152 and fallback for them.
153 We only do this for bus 0/seg 0 */
154 static __init void unreachable_devices(void)
159 for (i = 0; i < 32; i++) {
163 pci_conf1_read(0, 0, PCI_DEVFN(i, 0), 0, 4, &val1);
164 if (val1 == 0xffffffff)
167 /* Locking probably not needed, but safer */
168 spin_lock_irqsave(&pci_config_lock, flags);
169 addr = get_base_addr(0, 0, PCI_DEVFN(i, 0));
171 pci_exp_set_dev_base(addr, 0, PCI_DEVFN(i, 0));
172 if (addr == 0 || readl((u32 __iomem *)mmcfg_virt_addr) != val1)
173 set_bit(i, fallback_slots);
174 spin_unlock_irqrestore(&pci_config_lock, flags);
178 void __init pci_mmcfg_init(void)
180 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
183 acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
184 if ((pci_mmcfg_config_num == 0) ||
185 (pci_mmcfg_config == NULL) ||
186 (pci_mmcfg_config[0].base_address == 0))
189 if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
190 pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
192 printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
193 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
197 printk(KERN_INFO "PCI: Using MMCONFIG\n");
198 raw_pci_ops = &pci_mmcfg;
199 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
201 unreachable_devices();