3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
8 * Copyright 2004 Embedded Edge, LLC
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #include <linux/config.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <asm/mach-au1x00/au1000.h>
43 #include <asm/mach-au1x00/au1xxx_dbdma.h>
44 #include <asm/system.h>
46 /* #include <linux/module.h> */
48 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
51 * The Descriptor Based DMA supports up to 16 channels.
53 * There are 32 devices defined. We keep an internal structure
54 * of devices using these channels, along with additional
57 * We allocate the descriptors and allow access to them through various
58 * functions. The drivers allocate the data buffers and assign them
61 static spinlock_t au1xxx_dbdma_spin_lock = SPIN_LOCK_UNLOCKED;
63 /* I couldn't find a macro that did this......
65 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
67 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
68 static int dbdma_initialized=0;
69 static void au1xxx_dbdma_init(void);
71 static dbdev_tab_t dbdev_tab[] = {
72 #ifdef CONFIG_SOC_AU1550
74 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
75 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
76 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
77 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
80 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
81 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
82 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
83 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
86 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
87 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
88 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
89 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
90 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
91 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
94 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
95 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
98 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
99 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
102 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
103 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
106 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
107 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
109 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
110 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
113 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
114 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
117 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
118 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
120 #endif /* CONFIG_SOC_AU1550 */
122 #ifdef CONFIG_SOC_AU1200
123 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
124 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
125 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
126 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
128 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
129 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
131 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
132 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
133 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
134 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
136 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
137 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
138 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
139 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
141 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
142 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
144 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
145 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
146 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
148 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
149 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
150 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
152 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
153 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
154 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
155 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
157 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
159 #endif // CONFIG_SOC_AU1200
161 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
162 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
164 /* Provide 16 user definable device types */
165 { 0, 0, 0, 0, 0, 0, 0 },
166 { 0, 0, 0, 0, 0, 0, 0 },
167 { 0, 0, 0, 0, 0, 0, 0 },
168 { 0, 0, 0, 0, 0, 0, 0 },
169 { 0, 0, 0, 0, 0, 0, 0 },
170 { 0, 0, 0, 0, 0, 0, 0 },
171 { 0, 0, 0, 0, 0, 0, 0 },
172 { 0, 0, 0, 0, 0, 0, 0 },
173 { 0, 0, 0, 0, 0, 0, 0 },
174 { 0, 0, 0, 0, 0, 0, 0 },
175 { 0, 0, 0, 0, 0, 0, 0 },
176 { 0, 0, 0, 0, 0, 0, 0 },
177 { 0, 0, 0, 0, 0, 0, 0 },
178 { 0, 0, 0, 0, 0, 0, 0 },
179 { 0, 0, 0, 0, 0, 0, 0 },
180 { 0, 0, 0, 0, 0, 0, 0 },
183 #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
185 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
188 find_dbdev_id (u32 id)
192 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
201 au1xxx_ddma_add_device(dbdev_tab_t *dev)
205 static u16 new_id=0x1000;
207 p = find_dbdev_id(0);
210 memcpy(p, dev, sizeof(dbdev_tab_t));
211 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
215 printk("add_device: id:%x flags:%x padd:%x\n",
216 p->dev_id, p->dev_flags, p->dev_physaddr );
222 EXPORT_SYMBOL(au1xxx_ddma_add_device);
224 /* Allocate a channel and return a non-zero descriptor if successful.
227 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
228 void (*callback)(int, void *, struct pt_regs *), void *callparam)
234 dbdev_tab_t *stp, *dtp;
238 /* We do the intialization on the first channel allocation.
239 * We have to wait because of the interrupt handler initialization
240 * which can't be done successfully during board set up.
242 if (!dbdma_initialized)
244 dbdma_initialized = 1;
246 if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
247 if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
252 /* Check to see if we can get both channels.
254 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
255 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
256 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
258 stp->dev_flags |= DEV_FLAGS_INUSE;
259 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
260 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
261 /* Got destination */
262 dtp->dev_flags |= DEV_FLAGS_INUSE;
265 /* Can't get dest. Release src.
267 stp->dev_flags &= ~DEV_FLAGS_INUSE;
274 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
277 /* Let's see if we can allocate a channel for it.
281 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
282 for (i=0; i<NUM_DBDMA_CHANS; i++) {
283 if (chan_tab_ptr[i] == NULL) {
284 /* If kmalloc fails, it is caught below same
285 * as a channel not available.
288 kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
289 chan_tab_ptr[i] = ctp;
293 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
296 memset(ctp, 0, sizeof(chan_tab_t));
297 ctp->chan_index = chan = i;
298 dcp = DDMA_CHANNEL_BASE;
299 dcp += (0x0100 * chan);
300 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
301 cp = (au1x_dma_chan_t *)dcp;
303 ctp->chan_dest = dtp;
304 ctp->chan_callback = callback;
305 ctp->chan_callparam = callparam;
307 /* Initialize channel configuration.
310 if (stp->dev_intlevel)
312 if (stp->dev_intpolarity)
314 if (dtp->dev_intlevel)
316 if (dtp->dev_intpolarity)
318 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
319 (dtp->dev_flags & DEV_FLAGS_SYNC))
324 /* Return a non-zero value that can be used to
325 * find the channel information in subsequent
328 rv = (u32)(&chan_tab_ptr[chan]);
331 /* Release devices */
332 stp->dev_flags &= ~DEV_FLAGS_INUSE;
333 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
338 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
340 /* Set the device width if source or destination is a FIFO.
341 * Should be 8, 16, or 32 bits.
344 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
348 dbdev_tab_t *stp, *dtp;
350 ctp = *((chan_tab_t **)chanid);
352 dtp = ctp->chan_dest;
355 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
356 rv = stp->dev_devwidth;
357 stp->dev_devwidth = bits;
359 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
360 rv = dtp->dev_devwidth;
361 dtp->dev_devwidth = bits;
366 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
368 /* Allocate a descriptor ring, initializing as much as possible.
371 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
374 u32 desc_base, srcid, destid;
375 u32 cmd0, cmd1, src1, dest1;
378 dbdev_tab_t *stp, *dtp;
379 au1x_ddma_desc_t *dp;
381 /* I guess we could check this to be within the
382 * range of the table......
384 ctp = *((chan_tab_t **)chanid);
386 dtp = ctp->chan_dest;
388 /* The descriptors must be 32-byte aligned. There is a
389 * possibility the allocation will give us such an address,
390 * and if we try that first we are likely to not waste larger
393 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
398 if (desc_base & 0x1f) {
399 /* Lost....do it again, allocate extra, and round
402 kfree((const void *)desc_base);
403 i = entries * sizeof(au1x_ddma_desc_t);
404 i += (sizeof(au1x_ddma_desc_t) - 1);
405 if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
408 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
410 dp = (au1x_ddma_desc_t *)desc_base;
412 /* Keep track of the base descriptor.
414 ctp->chan_desc_base = dp;
416 /* Initialize the rings with as much information as we know.
419 destid = dtp->dev_id;
421 cmd0 = cmd1 = src1 = dest1 = 0;
424 cmd0 |= DSCR_CMD0_SID(srcid);
425 cmd0 |= DSCR_CMD0_DID(destid);
426 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
427 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_CURRENT);
429 switch (stp->dev_devwidth) {
431 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
434 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
438 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
442 switch (dtp->dev_devwidth) {
444 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
447 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
451 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
455 /* If the device is marked as an in/out FIFO, ensure it is
458 if (stp->dev_flags & DEV_FLAGS_IN)
459 cmd0 |= DSCR_CMD0_SN; /* Source in fifo */
460 if (dtp->dev_flags & DEV_FLAGS_OUT)
461 cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */
463 /* Set up source1. For now, assume no stride and increment.
464 * A channel attribute update can change this later.
466 switch (stp->dev_tsize) {
468 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
471 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
474 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
478 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
482 /* If source input is fifo, set static address.
484 if (stp->dev_flags & DEV_FLAGS_IN) {
485 if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
486 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
488 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
491 if (stp->dev_physaddr)
492 src0 = stp->dev_physaddr;
494 /* Set up dest1. For now, assume no stride and increment.
495 * A channel attribute update can change this later.
497 switch (dtp->dev_tsize) {
499 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
502 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
505 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
509 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
513 /* If destination output is fifo, set static address.
515 if (dtp->dev_flags & DEV_FLAGS_OUT) {
516 if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
517 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
519 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
521 if (dtp->dev_physaddr)
522 dest0 = dtp->dev_physaddr;
525 printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
526 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
528 for (i=0; i<entries; i++) {
529 dp->dscr_cmd0 = cmd0;
530 dp->dscr_cmd1 = cmd1;
531 dp->dscr_source0 = src0;
532 dp->dscr_source1 = src1;
533 dp->dscr_dest0 = dest0;
534 dp->dscr_dest1 = dest1;
536 dp->sw_context = dp->sw_status = 0;
537 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
541 /* Make last descrptor point to the first.
544 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
545 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
547 return (u32)(ctp->chan_desc_base);
549 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
551 /* Put a source buffer into the DMA ring.
552 * This updates the source pointer and byte count. Normally used
553 * for memory to fifo transfers.
556 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
559 au1x_ddma_desc_t *dp;
561 /* I guess we could check this to be within the
562 * range of the table......
564 ctp = *((chan_tab_t **)chanid);
566 /* We should have multiple callers for a particular channel,
567 * an interrupt doesn't affect this pointer nor the descriptor,
568 * so no locking should be needed.
572 /* If the descriptor is valid, we are way ahead of the DMA
573 * engine, so just return an error condition.
575 if (dp->dscr_cmd0 & DSCR_CMD0_V) {
579 /* Load up buffer address and byte count.
581 dp->dscr_source0 = virt_to_phys(buf);
582 dp->dscr_cmd1 = nbytes;
584 if (flags & DDMA_FLAGS_IE)
585 dp->dscr_cmd0 |= DSCR_CMD0_IE;
586 if (flags & DDMA_FLAGS_NOIE)
587 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
588 /* Get next descriptor pointer.
590 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
593 * There is an errata on the Au1200/Au1550 parts that could result
594 * in "stale" data being DMA'd. It has to do with the snoop logic on
595 * the dache eviction buffer. NONCOHERENT_IO is on by default for
596 * these parts. If it is fixedin the future, these dma_cache_inv will
597 * just be nothing more than empty macros. See io.h.
599 dma_cache_wback_inv(buf,nbytes);
600 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
602 dma_cache_wback_inv(dp, sizeof(dp));
603 ctp->chan_ptr->ddma_dbell = 0;
605 /* return something not zero.
609 EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
611 /* Put a destination buffer into the DMA ring.
612 * This updates the destination pointer and byte count. Normally used
613 * to place an empty buffer into the ring for fifo to memory transfers.
616 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
619 au1x_ddma_desc_t *dp;
621 /* I guess we could check this to be within the
622 * range of the table......
624 ctp = *((chan_tab_t **)chanid);
626 /* We should have multiple callers for a particular channel,
627 * an interrupt doesn't affect this pointer nor the descriptor,
628 * so no locking should be needed.
632 /* If the descriptor is valid, we are way ahead of the DMA
633 * engine, so just return an error condition.
635 if (dp->dscr_cmd0 & DSCR_CMD0_V)
638 /* Load up buffer address and byte count */
641 if (flags & DDMA_FLAGS_IE)
642 dp->dscr_cmd0 |= DSCR_CMD0_IE;
643 if (flags & DDMA_FLAGS_NOIE)
644 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
646 dp->dscr_dest0 = virt_to_phys(buf);
647 dp->dscr_cmd1 = nbytes;
649 printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
650 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
651 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
654 * There is an errata on the Au1200/Au1550 parts that could result in
655 * "stale" data being DMA'd. It has to do with the snoop logic on the
656 * dache eviction buffer. NONCOHERENT_IO is on by default for these
657 * parts. If it is fixedin the future, these dma_cache_inv will just
658 * be nothing more than empty macros. See io.h.
660 dma_cache_inv(buf,nbytes);
661 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
663 dma_cache_wback_inv(dp, sizeof(dp));
664 ctp->chan_ptr->ddma_dbell = 0;
666 /* Get next descriptor pointer.
668 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
670 /* return something not zero.
674 EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
676 /* Get a destination buffer into the DMA ring.
677 * Normally used to get a full buffer from the ring during fifo
678 * to memory transfers. This does not set the valid bit, you will
679 * have to put another destination buffer to keep the DMA going.
682 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
685 au1x_ddma_desc_t *dp;
688 /* I guess we could check this to be within the
689 * range of the table......
691 ctp = *((chan_tab_t **)chanid);
693 /* We should have multiple callers for a particular channel,
694 * an interrupt doesn't affect this pointer nor the descriptor,
695 * so no locking should be needed.
699 /* If the descriptor is valid, we are way ahead of the DMA
700 * engine, so just return an error condition.
702 if (dp->dscr_cmd0 & DSCR_CMD0_V)
705 /* Return buffer address and byte count.
707 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
708 *nbytes = dp->dscr_cmd1;
711 /* Get next descriptor pointer.
713 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
715 /* return something not zero.
721 au1xxx_dbdma_stop(u32 chanid)
725 int halt_timeout = 0;
727 ctp = *((chan_tab_t **)chanid);
730 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
732 while (!(cp->ddma_stat & DDMA_STAT_H)) {
735 if (halt_timeout > 100) {
736 printk("warning: DMA channel won't halt\n");
740 /* clear current desc valid and doorbell */
741 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
744 EXPORT_SYMBOL(au1xxx_dbdma_stop);
746 /* Start using the current descriptor pointer. If the dbdma encounters
747 * a not valid descriptor, it will stop. In this case, we can just
748 * continue by adding a buffer to the list and starting again.
751 au1xxx_dbdma_start(u32 chanid)
756 ctp = *((chan_tab_t **)chanid);
758 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
759 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
764 EXPORT_SYMBOL(au1xxx_dbdma_start);
767 au1xxx_dbdma_reset(u32 chanid)
770 au1x_ddma_desc_t *dp;
772 au1xxx_dbdma_stop(chanid);
774 ctp = *((chan_tab_t **)chanid);
775 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
777 /* Run through the descriptors and reset the valid indicator.
779 dp = ctp->chan_desc_base;
782 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
783 /* reset our SW status -- this is used to determine
784 * if a descriptor is in use by upper level SW. Since
785 * posting can reset 'V' bit.
788 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
789 } while (dp != ctp->chan_desc_base);
791 EXPORT_SYMBOL(au1xxx_dbdma_reset);
794 au1xxx_get_dma_residue(u32 chanid)
800 ctp = *((chan_tab_t **)chanid);
803 /* This is only valid if the channel is stopped.
805 rv = cp->ddma_bytecnt;
812 au1xxx_dbdma_chan_free(u32 chanid)
815 dbdev_tab_t *stp, *dtp;
817 ctp = *((chan_tab_t **)chanid);
819 dtp = ctp->chan_dest;
821 au1xxx_dbdma_stop(chanid);
823 if (ctp->chan_desc_base != NULL)
824 kfree(ctp->chan_desc_base);
826 stp->dev_flags &= ~DEV_FLAGS_INUSE;
827 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
828 chan_tab_ptr[ctp->chan_index] = NULL;
832 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
835 dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
840 au1x_ddma_desc_t *dp;
843 intstat = dbdma_gptr->ddma_intstat;
845 chan_index = au_ffs(intstat) - 1;
847 ctp = chan_tab_ptr[chan_index];
856 if (ctp->chan_callback)
857 (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
859 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
862 static void au1xxx_dbdma_init(void)
866 dbdma_gptr->ddma_config = 0;
867 dbdma_gptr->ddma_throttle = 0;
868 dbdma_gptr->ddma_inten = 0xffff;
871 #if defined(CONFIG_SOC_AU1550)
872 irq_nr = AU1550_DDMA_INT;
873 #elif defined(CONFIG_SOC_AU1200)
874 irq_nr = AU1200_DDMA_INT;
876 #error Unknown Au1x00 SOC
879 if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
880 "Au1xxx dbdma", (void *)dbdma_gptr))
881 printk("Can't get 1550 dbdma irq");
885 au1xxx_dbdma_dump(u32 chanid)
888 au1x_ddma_desc_t *dp;
889 dbdev_tab_t *stp, *dtp;
893 ctp = *((chan_tab_t **)chanid);
895 dtp = ctp->chan_dest;
898 printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
899 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab);
900 printk("desc base %x, get %x, put %x, cur %x\n",
901 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
902 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
904 printk("dbdma chan %x\n", (u32)cp);
905 printk("cfg %08x, desptr %08x, statptr %08x\n",
906 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
907 printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
908 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt);
911 /* Run through the descriptors
913 dp = ctp->chan_desc_base;
916 printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
917 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
918 printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
919 dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
920 printk("stat %08x, nxtptr %08x\n",
921 dp->dscr_stat, dp->dscr_nxtptr);
922 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
923 } while (dp != ctp->chan_desc_base);
926 /* Put a descriptor into the DMA ring.
927 * This updates the source/destination pointers and byte count.
930 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
933 au1x_ddma_desc_t *dp;
936 /* I guess we could check this to be within the
937 * range of the table......
939 ctp = *((chan_tab_t **)chanid);
941 /* We should have multiple callers for a particular channel,
942 * an interrupt doesn't affect this pointer nor the descriptor,
943 * so no locking should be needed.
947 /* If the descriptor is valid, we are way ahead of the DMA
948 * engine, so just return an error condition.
950 if (dp->dscr_cmd0 & DSCR_CMD0_V)
953 /* Load up buffer addresses and byte count.
955 dp->dscr_dest0 = dscr->dscr_dest0;
956 dp->dscr_source0 = dscr->dscr_source0;
957 dp->dscr_dest1 = dscr->dscr_dest1;
958 dp->dscr_source1 = dscr->dscr_source1;
959 dp->dscr_cmd1 = dscr->dscr_cmd1;
960 nbytes = dscr->dscr_cmd1;
961 /* Allow the caller to specifiy if an interrupt is generated */
962 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
963 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
964 ctp->chan_ptr->ddma_dbell = 0;
966 /* Get next descriptor pointer.
968 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
970 /* return something not zero.
975 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */