2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 #include <linux/init.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
16 #include <asm/irqflags.h>
17 #include <asm/regdef.h>
18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h>
20 #include <asm/stackframe.h>
23 #define PANIC_PIC(msg) \
36 NESTED(except_vec0_generic, 0, sp)
37 PANIC_PIC("Exception vector 0 called")
38 END(except_vec0_generic)
40 NESTED(except_vec1_generic, 0, sp)
41 PANIC_PIC("Exception vector 1 called")
42 END(except_vec1_generic)
45 * General exception vector for all other CPUs.
47 * Be careful when changing this, it has to be at most 128 bytes
48 * to fit into space reserved for the exception handler.
50 NESTED(except_vec3_generic, 0, sp)
53 #if R5432_CP0_INTERRUPT_WAR
61 PTR_L k0, exception_handlers(k1)
64 END(except_vec3_generic)
67 * General exception handler for CPUs with virtual coherency exception.
69 * Be careful when changing this, it has to be at most 256 (as a special
70 * exception) bytes to fit into space reserved for the exception handler.
72 NESTED(except_vec3_r4000, 0, sp)
82 beq k1, k0, handle_vced
84 beq k1, k0, handle_vcei
89 PTR_L k0, exception_handlers(k1)
93 * Big shit, we now may have two dirty primary cache lines for the same
94 * physical address. We can safely invalidate the line pointed to by
95 * c0_badvaddr because after return from this exception handler the
96 * load / store will be re-executed.
100 li k1, -4 # Is this ...
101 and k0, k1 # ... really needed?
103 cache Index_Store_Tag_D, (k0)
104 cache Hit_Writeback_Inv_SD, (k0)
105 #ifdef CONFIG_PROC_FS
106 PTR_LA k0, vced_count
114 MFC0 k0, CP0_BADVADDR
115 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
116 #ifdef CONFIG_PROC_FS
117 PTR_LA k0, vcei_count
124 END(except_vec3_r4000)
129 NESTED(handle_int, PT_SIZE, sp)
134 LONG_L s0, TI_REGS($28)
135 LONG_S sp, TI_REGS($28)
136 PTR_LA ra, ret_from_irq
143 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
144 * This is a dedicated interrupt exception vector which reduces the
145 * interrupt processing overhead. The jump instruction will be replaced
146 * at the initialization time.
148 * Be careful when changing this, it has to be at most 128 bytes
149 * to fit into space reserved for the exception handler.
151 NESTED(except_vec4, 0, sp)
152 1: j 1b /* Dummy, will be replaced */
156 * EJTAG debug exception handler.
157 * The EJTAG debug exception entry point is 0xbfc00480, which
158 * normally is in the boot PROM, so the boot PROM must do a
159 * unconditional jump to this vector.
161 NESTED(except_vec_ejtag_debug, 0, sp)
162 j ejtag_debug_handler
163 END(except_vec_ejtag_debug)
168 * Vectored interrupt handler.
169 * This prototype is copied to ebase + n*IntCtl.VS and patched
170 * to invoke the handler
172 NESTED(except_vec_vi, 0, sp)
177 #ifdef CONFIG_MIPS_MT_SMTC
179 * To keep from blindly blocking *all* interrupts
180 * during service by SMTC kernel, we also want to
181 * pass the IM value to be cleared.
183 EXPORT(except_vec_vi_mori)
185 #endif /* CONFIG_MIPS_MT_SMTC */
186 EXPORT(except_vec_vi_lui)
187 lui v0, 0 /* Patched */
188 j except_vec_vi_handler
189 EXPORT(except_vec_vi_ori)
190 ori v0, 0 /* Patched */
193 EXPORT(except_vec_vi_end)
196 * Common Vectored Interrupt code
197 * Complete the register saves and invoke the handler which is passed in $v0
199 NESTED(except_vec_vi_handler, 0, sp)
202 #ifdef CONFIG_MIPS_MT_SMTC
204 * SMTC has an interesting problem that interrupts are level-triggered,
205 * and the CLI macro will clear EXL, potentially causing a duplicate
206 * interrupt service invocation. So we need to clear the associated
207 * IM bit of Status prior to doing CLI, and restore it after the
208 * service routine has been invoked - we must assume that the
209 * service routine will have cleared the state, and any active
210 * level represents a new or otherwised unserviced event...
214 mfc0 t2, CP0_TCCONTEXT
216 mtc0 t0, CP0_TCCONTEXT
220 #endif /* CONFIG_MIPS_MT_SMTC */
224 LONG_L s0, TI_REGS($28)
225 LONG_S sp, TI_REGS($28)
226 PTR_LA ra, ret_from_irq
228 END(except_vec_vi_handler)
231 * EJTAG debug exception handler.
233 NESTED(ejtag_debug_handler, PT_SIZE, sp)
239 sll k0, k0, 30 # Check for SDBBP.
240 bgez k0, ejtag_return
242 PTR_LA k0, ejtag_debug_buffer
246 jal ejtag_exception_handler
248 PTR_LA k0, ejtag_debug_buffer
256 END(ejtag_debug_handler)
259 * This buffer is reserved for the use of the EJTAG debug
263 EXPORT(ejtag_debug_buffer)
270 * NMI debug exception handler for MIPS reference boards.
271 * The NMI debug exception entry point is 0xbfc00000, which
272 * normally is in the boot PROM, so the boot PROM must do a
273 * unconditional jump to this vector.
275 NESTED(except_vec_nmi, 0, sp)
281 NESTED(nmi_handler, PT_SIZE, sp)
286 jal nmi_exception_handler
293 .macro __build_clear_none
296 .macro __build_clear_sti
301 .macro __build_clear_cli
306 .macro __build_clear_fpe
315 .macro __build_clear_ade
316 MFC0 t0, CP0_BADVADDR
317 PTR_S t0, PT_BVADDR(sp)
321 .macro __BUILD_silent exception
324 /* Gas tries to parse the PRINT argument as a string containing
325 string escapes and emits bogus warnings if it believes to
326 recognize an unknown escape code. So make the arguments
327 start with an n and gas will believe \n is ok ... */
328 .macro __BUILD_verbose nexception
329 LONG_L a1, PT_EPC(sp)
331 PRINT("Got \nexception at %08lx\012")
334 PRINT("Got \nexception at %016lx\012")
338 .macro __BUILD_count exception
339 LONG_L t0,exception_count_\exception
341 LONG_S t0,exception_count_\exception
342 .comm exception_count\exception, 8, 8
345 .macro __BUILD_HANDLER exception handler clear verbose ext
347 NESTED(handle_\exception, PT_SIZE, sp)
350 FEXPORT(handle_\exception\ext)
353 __BUILD_\verbose \exception
355 PTR_LA ra, ret_from_exception
357 END(handle_\exception)
360 .macro BUILD_HANDLER exception handler clear verbose
361 __BUILD_HANDLER \exception \handler \clear \verbose _int
364 BUILD_HANDLER adel ade ade silent /* #4 */
365 BUILD_HANDLER ades ade ade silent /* #5 */
366 BUILD_HANDLER ibe be cli silent /* #6 */
367 BUILD_HANDLER dbe be cli silent /* #7 */
368 BUILD_HANDLER bp bp sti silent /* #9 */
369 BUILD_HANDLER ri ri sti silent /* #10 */
370 BUILD_HANDLER cpu cpu sti silent /* #11 */
371 BUILD_HANDLER ov ov sti silent /* #12 */
372 BUILD_HANDLER tr tr sti silent /* #13 */
373 BUILD_HANDLER fpe fpe fpe silent /* #15 */
374 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
375 BUILD_HANDLER watch watch sti verbose /* #23 */
376 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
377 BUILD_HANDLER mt mt sti silent /* #25 */
378 BUILD_HANDLER dsp dsp sti silent /* #26 */
379 BUILD_HANDLER reserved reserved sti verbose /* others */
382 /* A temporary overflow handler used by check_daddi(). */
386 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */