2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/bug.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/types.h>
43 #include <asm/stacktrace.h>
45 extern asmlinkage void handle_int(void);
46 extern asmlinkage void handle_tlbm(void);
47 extern asmlinkage void handle_tlbl(void);
48 extern asmlinkage void handle_tlbs(void);
49 extern asmlinkage void handle_adel(void);
50 extern asmlinkage void handle_ades(void);
51 extern asmlinkage void handle_ibe(void);
52 extern asmlinkage void handle_dbe(void);
53 extern asmlinkage void handle_sys(void);
54 extern asmlinkage void handle_bp(void);
55 extern asmlinkage void handle_ri(void);
56 extern asmlinkage void handle_ri_rdhwr_vivt(void);
57 extern asmlinkage void handle_ri_rdhwr(void);
58 extern asmlinkage void handle_cpu(void);
59 extern asmlinkage void handle_ov(void);
60 extern asmlinkage void handle_tr(void);
61 extern asmlinkage void handle_fpe(void);
62 extern asmlinkage void handle_mdmx(void);
63 extern asmlinkage void handle_watch(void);
64 extern asmlinkage void handle_mt(void);
65 extern asmlinkage void handle_dsp(void);
66 extern asmlinkage void handle_mcheck(void);
67 extern asmlinkage void handle_reserved(void);
69 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
70 struct mips_fpu_struct *ctx, int has_fpu);
72 void (*board_watchpoint_handler)(struct pt_regs *regs);
73 void (*board_be_init)(void);
74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
75 void (*board_nmi_handler_setup)(void);
76 void (*board_ejtag_handler_setup)(void);
77 void (*board_bind_eic_interrupt)(int irq, int regset);
80 static void show_raw_backtrace(unsigned long reg29)
82 unsigned long *sp = (unsigned long *)reg29;
85 printk("Call Trace:");
86 #ifdef CONFIG_KALLSYMS
89 while (!kstack_end(sp)) {
91 if (__kernel_text_address(addr))
97 #ifdef CONFIG_KALLSYMS
99 static int __init set_raw_show_trace(char *str)
104 __setup("raw_show_trace", set_raw_show_trace);
107 static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
109 unsigned long sp = regs->regs[29];
110 unsigned long ra = regs->regs[31];
111 unsigned long pc = regs->cp0_epc;
113 if (raw_show_trace || !__kernel_text_address(pc)) {
114 show_raw_backtrace(sp);
117 printk("Call Trace:\n");
120 pc = unwind_stack(task, &sp, pc, &ra);
126 * This routine abuses get_user()/put_user() to reference pointers
127 * with at least a bit of error checking ...
129 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
131 const int field = 2 * sizeof(unsigned long);
134 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
138 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
139 if (i && ((i % (64 / field)) == 0))
146 if (__get_user(stackdata, sp++)) {
147 printk(" (Bad stack address)");
151 printk(" %0*lx", field, stackdata);
155 show_backtrace(task, regs);
158 void show_stack(struct task_struct *task, unsigned long *sp)
162 regs.regs[29] = (unsigned long)sp;
166 if (task && task != current) {
167 regs.regs[29] = task->thread.reg29;
169 regs.cp0_epc = task->thread.reg31;
171 prepare_frametrace(®s);
174 show_stacktrace(task, ®s);
178 * The architecture-independent dump_stack generator
180 void dump_stack(void)
184 prepare_frametrace(®s);
185 show_backtrace(current, ®s);
188 EXPORT_SYMBOL(dump_stack);
190 static void show_code(unsigned int __user *pc)
196 for(i = -3 ; i < 6 ; i++) {
198 if (__get_user(insn, pc + i)) {
199 printk(" (Bad address in epc)\n");
202 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
206 void show_regs(struct pt_regs *regs)
208 const int field = 2 * sizeof(unsigned long);
209 unsigned int cause = regs->cp0_cause;
212 printk("Cpu %d\n", smp_processor_id());
215 * Saved main processor registers
217 for (i = 0; i < 32; ) {
221 printk(" %0*lx", field, 0UL);
222 else if (i == 26 || i == 27)
223 printk(" %*s", field, "");
225 printk(" %0*lx", field, regs->regs[i]);
232 #ifdef CONFIG_CPU_HAS_SMARTMIPS
233 printk("Acx : %0*lx\n", field, regs->acx);
235 printk("Hi : %0*lx\n", field, regs->hi);
236 printk("Lo : %0*lx\n", field, regs->lo);
239 * Saved cp0 registers
241 printk("epc : %0*lx ", field, regs->cp0_epc);
242 print_symbol("%s ", regs->cp0_epc);
243 printk(" %s\n", print_tainted());
244 printk("ra : %0*lx ", field, regs->regs[31]);
245 print_symbol("%s\n", regs->regs[31]);
247 printk("Status: %08x ", (uint32_t) regs->cp0_status);
249 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
250 if (regs->cp0_status & ST0_KUO)
252 if (regs->cp0_status & ST0_IEO)
254 if (regs->cp0_status & ST0_KUP)
256 if (regs->cp0_status & ST0_IEP)
258 if (regs->cp0_status & ST0_KUC)
260 if (regs->cp0_status & ST0_IEC)
263 if (regs->cp0_status & ST0_KX)
265 if (regs->cp0_status & ST0_SX)
267 if (regs->cp0_status & ST0_UX)
269 switch (regs->cp0_status & ST0_KSU) {
274 printk("SUPERVISOR ");
283 if (regs->cp0_status & ST0_ERL)
285 if (regs->cp0_status & ST0_EXL)
287 if (regs->cp0_status & ST0_IE)
292 printk("Cause : %08x\n", cause);
294 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
295 if (1 <= cause && cause <= 5)
296 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
298 printk("PrId : %08x\n", read_c0_prid());
301 void show_registers(struct pt_regs *regs)
305 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
306 current->comm, current->pid, current_thread_info(), current);
307 show_stacktrace(current, regs);
308 show_code((unsigned int __user *) regs->cp0_epc);
312 static DEFINE_SPINLOCK(die_lock);
314 void __noreturn die(const char * str, struct pt_regs * regs)
316 static int die_counter;
317 #ifdef CONFIG_MIPS_MT_SMTC
318 unsigned long dvpret = dvpe();
319 #endif /* CONFIG_MIPS_MT_SMTC */
322 spin_lock_irq(&die_lock);
324 #ifdef CONFIG_MIPS_MT_SMTC
325 mips_mt_regdump(dvpret);
326 #endif /* CONFIG_MIPS_MT_SMTC */
327 printk("%s[#%d]:\n", str, ++die_counter);
328 show_registers(regs);
329 add_taint(TAINT_DIE);
330 spin_unlock_irq(&die_lock);
333 panic("Fatal exception in interrupt");
336 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
338 panic("Fatal exception");
344 extern const struct exception_table_entry __start___dbe_table[];
345 extern const struct exception_table_entry __stop___dbe_table[];
348 " .section __dbe_table, \"a\"\n"
351 /* Given an address, look for it in the exception tables. */
352 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
354 const struct exception_table_entry *e;
356 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
358 e = search_module_dbetables(addr);
362 asmlinkage void do_be(struct pt_regs *regs)
364 const int field = 2 * sizeof(unsigned long);
365 const struct exception_table_entry *fixup = NULL;
366 int data = regs->cp0_cause & 4;
367 int action = MIPS_BE_FATAL;
369 /* XXX For now. Fixme, this searches the wrong table ... */
370 if (data && !user_mode(regs))
371 fixup = search_dbe_tables(exception_epc(regs));
374 action = MIPS_BE_FIXUP;
376 if (board_be_handler)
377 action = board_be_handler(regs, fixup != NULL);
380 case MIPS_BE_DISCARD:
384 regs->cp0_epc = fixup->nextinsn;
393 * Assume it would be too dangerous to continue ...
395 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
396 data ? "Data" : "Instruction",
397 field, regs->cp0_epc, field, regs->regs[31]);
398 die_if_kernel("Oops", regs);
399 force_sig(SIGBUS, current);
406 #define OPCODE 0xfc000000
407 #define BASE 0x03e00000
408 #define RT 0x001f0000
409 #define OFFSET 0x0000ffff
410 #define LL 0xc0000000
411 #define SC 0xe0000000
412 #define SPEC3 0x7c000000
413 #define RD 0x0000f800
414 #define FUNC 0x0000003f
415 #define RDHWR 0x0000003b
418 * The ll_bit is cleared by r*_switch.S
421 unsigned long ll_bit;
423 static struct task_struct *ll_task = NULL;
425 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
427 unsigned long value, __user *vaddr;
432 * analyse the ll instruction that just caused a ri exception
433 * and put the referenced address to addr.
436 /* sign extend offset */
437 offset = opcode & OFFSET;
441 vaddr = (unsigned long __user *)
442 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
444 if ((unsigned long)vaddr & 3) {
448 if (get_user(value, vaddr)) {
455 if (ll_task == NULL || ll_task == current) {
464 compute_return_epc(regs);
466 regs->regs[(opcode & RT) >> 16] = value;
471 force_sig(signal, current);
474 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
476 unsigned long __user *vaddr;
482 * analyse the sc instruction that just caused a ri exception
483 * and put the referenced address to addr.
486 /* sign extend offset */
487 offset = opcode & OFFSET;
491 vaddr = (unsigned long __user *)
492 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
493 reg = (opcode & RT) >> 16;
495 if ((unsigned long)vaddr & 3) {
502 if (ll_bit == 0 || ll_task != current) {
503 compute_return_epc(regs);
511 if (put_user(regs->regs[reg], vaddr)) {
516 compute_return_epc(regs);
522 force_sig(signal, current);
526 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
527 * opcodes are supposed to result in coprocessor unusable exceptions if
528 * executed on ll/sc-less processors. That's the theory. In practice a
529 * few processors such as NEC's VR4100 throw reserved instruction exceptions
530 * instead, so we're doing the emulation thing in both exception handlers.
532 static inline int simulate_llsc(struct pt_regs *regs)
536 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
539 if ((opcode & OPCODE) == LL) {
540 simulate_ll(regs, opcode);
543 if ((opcode & OPCODE) == SC) {
544 simulate_sc(regs, opcode);
548 return -EFAULT; /* Strange things going on ... */
551 force_sig(SIGSEGV, current);
556 * Simulate trapping 'rdhwr' instructions to provide user accessible
557 * registers not implemented in hardware. The only current use of this
558 * is the thread area pointer.
560 static inline int simulate_rdhwr(struct pt_regs *regs)
562 struct thread_info *ti = task_thread_info(current);
565 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
568 if (unlikely(compute_return_epc(regs)))
571 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
572 int rd = (opcode & RD) >> 11;
573 int rt = (opcode & RT) >> 16;
576 regs->regs[rt] = ti->tp_value;
587 force_sig(SIGSEGV, current);
591 asmlinkage void do_ov(struct pt_regs *regs)
595 die_if_kernel("Integer overflow", regs);
597 info.si_code = FPE_INTOVF;
598 info.si_signo = SIGFPE;
600 info.si_addr = (void __user *) regs->cp0_epc;
601 force_sig_info(SIGFPE, &info, current);
605 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
607 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
611 die_if_kernel("FP exception in kernel code", regs);
613 if (fcr31 & FPU_CSR_UNI_X) {
617 * Unimplemented operation exception. If we've got the full
618 * software emulator on-board, let's use it...
620 * Force FPU to dump state into task/thread context. We're
621 * moving a lot of data here for what is probably a single
622 * instruction, but the alternative is to pre-decode the FP
623 * register operands before invoking the emulator, which seems
624 * a bit extreme for what should be an infrequent event.
626 /* Ensure 'resume' not overwrite saved fp context again. */
629 /* Run the emulator */
630 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1);
633 * We can't allow the emulated instruction to leave any of
634 * the cause bit set in $fcr31.
636 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
638 /* Restore the hardware register state */
639 own_fpu(1); /* Using the FPU again. */
641 /* If something went wrong, signal */
643 force_sig(sig, current);
646 } else if (fcr31 & FPU_CSR_INV_X)
647 info.si_code = FPE_FLTINV;
648 else if (fcr31 & FPU_CSR_DIV_X)
649 info.si_code = FPE_FLTDIV;
650 else if (fcr31 & FPU_CSR_OVF_X)
651 info.si_code = FPE_FLTOVF;
652 else if (fcr31 & FPU_CSR_UDF_X)
653 info.si_code = FPE_FLTUND;
654 else if (fcr31 & FPU_CSR_INE_X)
655 info.si_code = FPE_FLTRES;
657 info.si_code = __SI_FAULT;
658 info.si_signo = SIGFPE;
660 info.si_addr = (void __user *) regs->cp0_epc;
661 force_sig_info(SIGFPE, &info, current);
664 asmlinkage void do_bp(struct pt_regs *regs)
666 unsigned int opcode, bcode;
669 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
673 * There is the ancient bug in the MIPS assemblers that the break
674 * code starts left to bit 16 instead to bit 6 in the opcode.
675 * Gas is bug-compatible, but not always, grrr...
676 * We handle both cases with a simple heuristics. --macro
678 bcode = ((opcode >> 6) & ((1 << 20) - 1));
679 if (bcode < (1 << 10))
683 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
684 * insns, even for break codes that indicate arithmetic failures.
686 * But should we continue the brokenness??? --macro
689 case BRK_OVERFLOW << 10:
690 case BRK_DIVZERO << 10:
691 die_if_kernel("Break instruction in kernel code", regs);
692 if (bcode == (BRK_DIVZERO << 10))
693 info.si_code = FPE_INTDIV;
695 info.si_code = FPE_INTOVF;
696 info.si_signo = SIGFPE;
698 info.si_addr = (void __user *) regs->cp0_epc;
699 force_sig_info(SIGFPE, &info, current);
702 die("Kernel bug detected", regs);
705 die_if_kernel("Break instruction in kernel code", regs);
706 force_sig(SIGTRAP, current);
711 force_sig(SIGSEGV, current);
714 asmlinkage void do_tr(struct pt_regs *regs)
716 unsigned int opcode, tcode = 0;
719 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
722 /* Immediate versions don't provide a code. */
723 if (!(opcode & OPCODE))
724 tcode = ((opcode >> 6) & ((1 << 10) - 1));
727 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
728 * insns, even for trap codes that indicate arithmetic failures.
730 * But should we continue the brokenness??? --macro
735 die_if_kernel("Trap instruction in kernel code", regs);
736 if (tcode == BRK_DIVZERO)
737 info.si_code = FPE_INTDIV;
739 info.si_code = FPE_INTOVF;
740 info.si_signo = SIGFPE;
742 info.si_addr = (void __user *) regs->cp0_epc;
743 force_sig_info(SIGFPE, &info, current);
746 die("Kernel bug detected", regs);
749 die_if_kernel("Trap instruction in kernel code", regs);
750 force_sig(SIGTRAP, current);
755 force_sig(SIGSEGV, current);
758 asmlinkage void do_ri(struct pt_regs *regs)
760 die_if_kernel("Reserved instruction in kernel code", regs);
763 if (!simulate_llsc(regs))
766 if (!simulate_rdhwr(regs))
769 force_sig(SIGILL, current);
773 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
774 * emulated more than some threshold number of instructions, force migration to
775 * a "CPU" that has FP support.
777 static void mt_ase_fp_affinity(void)
779 #ifdef CONFIG_MIPS_MT_FPAFF
780 if (mt_fpemul_threshold > 0 &&
781 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
783 * If there's no FPU present, or if the application has already
784 * restricted the allowed set to exclude any CPUs with FPUs,
785 * we'll skip the procedure.
787 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
790 cpus_and(tmask, current->thread.user_cpus_allowed,
792 set_cpus_allowed(current, tmask);
793 set_thread_flag(TIF_FPUBOUND);
796 #endif /* CONFIG_MIPS_MT_FPAFF */
799 asmlinkage void do_cpu(struct pt_regs *regs)
803 die_if_kernel("do_cpu invoked from kernel context!", regs);
805 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
810 if (!simulate_llsc(regs))
813 if (!simulate_rdhwr(regs))
819 if (used_math()) /* Using the FPU again. */
821 else { /* First time FPU user. */
826 if (!raw_cpu_has_fpu) {
828 sig = fpu_emulator_cop1Handler(regs,
829 ¤t->thread.fpu, 0);
831 force_sig(sig, current);
833 mt_ase_fp_affinity();
843 force_sig(SIGILL, current);
846 asmlinkage void do_mdmx(struct pt_regs *regs)
848 force_sig(SIGILL, current);
851 asmlinkage void do_watch(struct pt_regs *regs)
853 if (board_watchpoint_handler) {
854 (*board_watchpoint_handler)(regs);
859 * We use the watch exception where available to detect stack
864 panic("Caught WATCH exception - probably caused by stack overflow.");
867 asmlinkage void do_mcheck(struct pt_regs *regs)
869 const int field = 2 * sizeof(unsigned long);
870 int multi_match = regs->cp0_status & ST0_TS;
875 printk("Index : %0x\n", read_c0_index());
876 printk("Pagemask: %0x\n", read_c0_pagemask());
877 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
878 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
879 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
884 show_code((unsigned int __user *) regs->cp0_epc);
887 * Some chips may have other causes of machine check (e.g. SB1
890 panic("Caught Machine Check exception - %scaused by multiple "
891 "matching entries in the TLB.",
892 (multi_match) ? "" : "not ");
895 asmlinkage void do_mt(struct pt_regs *regs)
899 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
900 >> VPECONTROL_EXCPT_SHIFT;
903 printk(KERN_DEBUG "Thread Underflow\n");
906 printk(KERN_DEBUG "Thread Overflow\n");
909 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
912 printk(KERN_DEBUG "Gating Storage Exception\n");
915 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
918 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
921 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
925 die_if_kernel("MIPS MT Thread exception in kernel", regs);
927 force_sig(SIGILL, current);
931 asmlinkage void do_dsp(struct pt_regs *regs)
934 panic("Unexpected DSP exception\n");
936 force_sig(SIGILL, current);
939 asmlinkage void do_reserved(struct pt_regs *regs)
942 * Game over - no way to handle this if it ever occurs. Most probably
943 * caused by a new unknown cpu type or after another deadly
944 * hard/software error.
947 panic("Caught reserved exception %ld - should not happen.",
948 (regs->cp0_cause & 0x7f) >> 2);
952 * Some MIPS CPUs can enable/disable for cache parity detection, but do
955 static inline void parity_protection_init(void)
957 switch (current_cpu_data.cputype) {
961 write_c0_ecc(0x80000000);
962 back_to_back_c0_hazard();
963 /* Set the PE bit (bit 31) in the c0_errctl register. */
964 printk(KERN_INFO "Cache parity protection %sabled\n",
965 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
969 /* Clear the DE bit (bit 16) in the c0_status register. */
970 printk(KERN_INFO "Enable cache parity protection for "
971 "MIPS 20KC/25KF CPUs.\n");
972 clear_c0_status(ST0_DE);
979 asmlinkage void cache_parity_error(void)
981 const int field = 2 * sizeof(unsigned long);
982 unsigned int reg_val;
984 /* For the moment, report the problem and hang. */
985 printk("Cache error exception:\n");
986 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
987 reg_val = read_c0_cacheerr();
988 printk("c0_cacheerr == %08x\n", reg_val);
990 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
991 reg_val & (1<<30) ? "secondary" : "primary",
992 reg_val & (1<<31) ? "data" : "insn");
993 printk("Error bits: %s%s%s%s%s%s%s\n",
994 reg_val & (1<<29) ? "ED " : "",
995 reg_val & (1<<28) ? "ET " : "",
996 reg_val & (1<<26) ? "EE " : "",
997 reg_val & (1<<25) ? "EB " : "",
998 reg_val & (1<<24) ? "EI " : "",
999 reg_val & (1<<23) ? "E1 " : "",
1000 reg_val & (1<<22) ? "E0 " : "");
1001 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1003 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1004 if (reg_val & (1<<22))
1005 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1007 if (reg_val & (1<<23))
1008 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1011 panic("Can't handle the cache error!");
1015 * SDBBP EJTAG debug exception handler.
1016 * We skip the instruction and return to the next instruction.
1018 void ejtag_exception_handler(struct pt_regs *regs)
1020 const int field = 2 * sizeof(unsigned long);
1021 unsigned long depc, old_epc;
1024 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1025 depc = read_c0_depc();
1026 debug = read_c0_debug();
1027 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1028 if (debug & 0x80000000) {
1030 * In branch delay slot.
1031 * We cheat a little bit here and use EPC to calculate the
1032 * debug return address (DEPC). EPC is restored after the
1035 old_epc = regs->cp0_epc;
1036 regs->cp0_epc = depc;
1037 __compute_return_epc(regs);
1038 depc = regs->cp0_epc;
1039 regs->cp0_epc = old_epc;
1042 write_c0_depc(depc);
1045 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1046 write_c0_debug(debug | 0x100);
1051 * NMI exception handler.
1053 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1056 printk("NMI taken!!!!\n");
1060 #define VECTORSPACING 0x100 /* for EI/VI mode */
1062 unsigned long ebase;
1063 unsigned long exception_handlers[32];
1064 unsigned long vi_handlers[64];
1067 * As a side effect of the way this is implemented we're limited
1068 * to interrupt handlers in the address range from
1069 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1071 void *set_except_vector(int n, void *addr)
1073 unsigned long handler = (unsigned long) addr;
1074 unsigned long old_handler = exception_handlers[n];
1076 exception_handlers[n] = handler;
1077 if (n == 0 && cpu_has_divec) {
1078 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1079 (0x03ffffff & (handler >> 2));
1080 flush_icache_range(ebase + 0x200, ebase + 0x204);
1082 return (void *)old_handler;
1085 #ifdef CONFIG_CPU_MIPSR2_SRS
1087 * MIPSR2 shadow register set allocation
1091 static struct shadow_registers {
1093 * Number of shadow register sets supported
1095 unsigned long sr_supported;
1097 * Bitmap of allocated shadow registers
1099 unsigned long sr_allocated;
1102 static void mips_srs_init(void)
1104 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1105 printk(KERN_INFO "%ld MIPSR2 register sets available\n",
1106 shadow_registers.sr_supported);
1107 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1110 int mips_srs_max(void)
1112 return shadow_registers.sr_supported;
1115 int mips_srs_alloc(void)
1117 struct shadow_registers *sr = &shadow_registers;
1121 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1122 if (set >= sr->sr_supported)
1125 if (test_and_set_bit(set, &sr->sr_allocated))
1131 void mips_srs_free(int set)
1133 struct shadow_registers *sr = &shadow_registers;
1135 clear_bit(set, &sr->sr_allocated);
1138 static asmlinkage void do_default_vi(void)
1140 show_regs(get_irq_regs());
1141 panic("Caught unexpected vectored interrupt.");
1144 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1146 unsigned long handler;
1147 unsigned long old_handler = vi_handlers[n];
1151 if (!cpu_has_veic && !cpu_has_vint)
1155 handler = (unsigned long) do_default_vi;
1158 handler = (unsigned long) addr;
1159 vi_handlers[n] = (unsigned long) addr;
1161 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1163 if (srs >= mips_srs_max())
1164 panic("Shadow register set %d not supported", srs);
1167 if (board_bind_eic_interrupt)
1168 board_bind_eic_interrupt (n, srs);
1169 } else if (cpu_has_vint) {
1170 /* SRSMap is only defined if shadow sets are implemented */
1171 if (mips_srs_max() > 1)
1172 change_c0_srsmap (0xf << n*4, srs << n*4);
1177 * If no shadow set is selected then use the default handler
1178 * that does normal register saving and a standard interrupt exit
1181 extern char except_vec_vi, except_vec_vi_lui;
1182 extern char except_vec_vi_ori, except_vec_vi_end;
1183 #ifdef CONFIG_MIPS_MT_SMTC
1185 * We need to provide the SMTC vectored interrupt handler
1186 * not only with the address of the handler, but with the
1187 * Status.IM bit to be masked before going there.
1189 extern char except_vec_vi_mori;
1190 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1191 #endif /* CONFIG_MIPS_MT_SMTC */
1192 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1193 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1194 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1196 if (handler_len > VECTORSPACING) {
1198 * Sigh... panicing won't help as the console
1199 * is probably not configured :(
1201 panic ("VECTORSPACING too small");
1204 memcpy (b, &except_vec_vi, handler_len);
1205 #ifdef CONFIG_MIPS_MT_SMTC
1206 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1208 w = (u32 *)(b + mori_offset);
1209 *w = (*w & 0xffff0000) | (0x100 << n);
1210 #endif /* CONFIG_MIPS_MT_SMTC */
1211 w = (u32 *)(b + lui_offset);
1212 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1213 w = (u32 *)(b + ori_offset);
1214 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1215 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1219 * In other cases jump directly to the interrupt handler
1221 * It is the handlers responsibility to save registers if required
1222 * (eg hi/lo) and return from the exception using "eret"
1225 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1227 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1230 return (void *)old_handler;
1233 void *set_vi_handler(int n, vi_handler_t addr)
1235 return set_vi_srs_handler(n, addr, 0);
1240 static inline void mips_srs_init(void)
1244 #endif /* CONFIG_CPU_MIPSR2_SRS */
1247 * This is used by native signal handling
1249 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1250 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1252 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1253 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1255 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1256 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1259 static int smp_save_fp_context(struct sigcontext __user *sc)
1261 return raw_cpu_has_fpu
1262 ? _save_fp_context(sc)
1263 : fpu_emulator_save_context(sc);
1266 static int smp_restore_fp_context(struct sigcontext __user *sc)
1268 return raw_cpu_has_fpu
1269 ? _restore_fp_context(sc)
1270 : fpu_emulator_restore_context(sc);
1274 static inline void signal_init(void)
1277 /* For now just do the cpu_has_fpu check when the functions are invoked */
1278 save_fp_context = smp_save_fp_context;
1279 restore_fp_context = smp_restore_fp_context;
1282 save_fp_context = _save_fp_context;
1283 restore_fp_context = _restore_fp_context;
1285 save_fp_context = fpu_emulator_save_context;
1286 restore_fp_context = fpu_emulator_restore_context;
1291 #ifdef CONFIG_MIPS32_COMPAT
1294 * This is used by 32-bit signal stuff on the 64-bit kernel
1296 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1297 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1299 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1300 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1302 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1303 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1305 static inline void signal32_init(void)
1308 save_fp_context32 = _save_fp_context32;
1309 restore_fp_context32 = _restore_fp_context32;
1311 save_fp_context32 = fpu_emulator_save_context32;
1312 restore_fp_context32 = fpu_emulator_restore_context32;
1317 extern void cpu_cache_init(void);
1318 extern void tlb_init(void);
1319 extern void flush_tlb_handlers(void);
1321 void __init per_cpu_trap_init(void)
1323 unsigned int cpu = smp_processor_id();
1324 unsigned int status_set = ST0_CU0;
1325 #ifdef CONFIG_MIPS_MT_SMTC
1326 int secondaryTC = 0;
1327 int bootTC = (cpu == 0);
1330 * Only do per_cpu_trap_init() for first TC of Each VPE.
1331 * Note that this hack assumes that the SMTC init code
1332 * assigns TCs consecutively and in ascending order.
1335 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1336 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1338 #endif /* CONFIG_MIPS_MT_SMTC */
1341 * Disable coprocessors and select 32-bit or 64-bit addressing
1342 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1343 * flag that some firmware may have left set and the TS bit (for
1344 * IP27). Set XX for ISA IV code to work.
1347 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1349 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1350 status_set |= ST0_XX;
1351 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1355 set_c0_status(ST0_MX);
1357 #ifdef CONFIG_CPU_MIPSR2
1358 if (cpu_has_mips_r2) {
1359 unsigned int enable = 0x0000000f;
1361 if (cpu_has_userlocal)
1362 enable |= (1 << 29);
1364 write_c0_hwrena(enable);
1368 #ifdef CONFIG_MIPS_MT_SMTC
1370 #endif /* CONFIG_MIPS_MT_SMTC */
1372 if (cpu_has_veic || cpu_has_vint) {
1373 write_c0_ebase (ebase);
1374 /* Setting vector spacing enables EI/VI mode */
1375 change_c0_intctl (0x3e0, VECTORSPACING);
1377 if (cpu_has_divec) {
1378 if (cpu_has_mipsmt) {
1379 unsigned int vpflags = dvpe();
1380 set_c0_cause(CAUSEF_IV);
1383 set_c0_cause(CAUSEF_IV);
1387 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1389 * o read IntCtl.IPTI to determine the timer interrupt
1390 * o read IntCtl.IPPCI to determine the performance counter interrupt
1392 if (cpu_has_mips_r2) {
1393 cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
1394 cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
1395 if (cp0_perfcount_irq == cp0_compare_irq)
1396 cp0_perfcount_irq = -1;
1398 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1399 cp0_perfcount_irq = -1;
1402 #ifdef CONFIG_MIPS_MT_SMTC
1404 #endif /* CONFIG_MIPS_MT_SMTC */
1406 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1407 TLBMISS_HANDLER_SETUP();
1409 atomic_inc(&init_mm.mm_count);
1410 current->active_mm = &init_mm;
1411 BUG_ON(current->mm);
1412 enter_lazy_tlb(&init_mm, current);
1414 #ifdef CONFIG_MIPS_MT_SMTC
1416 #endif /* CONFIG_MIPS_MT_SMTC */
1419 #ifdef CONFIG_MIPS_MT_SMTC
1420 } else if (!secondaryTC) {
1422 * First TC in non-boot VPE must do subset of tlb_init()
1423 * for MMU countrol registers.
1425 write_c0_pagemask(PM_DEFAULT_MASK);
1428 #endif /* CONFIG_MIPS_MT_SMTC */
1431 /* Install CPU exception handler */
1432 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1434 memcpy((void *)(ebase + offset), addr, size);
1435 flush_icache_range(ebase + offset, ebase + offset + size);
1438 /* Install uncached CPU exception handler */
1439 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1442 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1445 unsigned long uncached_ebase = TO_UNCAC(ebase);
1448 memcpy((void *)(uncached_ebase + offset), addr, size);
1451 static int __initdata rdhwr_noopt;
1452 static int __init set_rdhwr_noopt(char *str)
1458 __setup("rdhwr_noopt", set_rdhwr_noopt);
1460 void __init trap_init(void)
1462 extern char except_vec3_generic, except_vec3_r4000;
1463 extern char except_vec4;
1466 if (cpu_has_veic || cpu_has_vint)
1467 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1473 per_cpu_trap_init();
1476 * Copy the generic exception handlers to their final destination.
1477 * This will be overriden later as suitable for a particular
1480 set_handler(0x180, &except_vec3_generic, 0x80);
1483 * Setup default vectors
1485 for (i = 0; i <= 31; i++)
1486 set_except_vector(i, handle_reserved);
1489 * Copy the EJTAG debug exception vector handler code to it's final
1492 if (cpu_has_ejtag && board_ejtag_handler_setup)
1493 board_ejtag_handler_setup ();
1496 * Only some CPUs have the watch exceptions.
1499 set_except_vector(23, handle_watch);
1502 * Initialise interrupt handlers
1504 if (cpu_has_veic || cpu_has_vint) {
1505 int nvec = cpu_has_veic ? 64 : 8;
1506 for (i = 0; i < nvec; i++)
1507 set_vi_handler(i, NULL);
1509 else if (cpu_has_divec)
1510 set_handler(0x200, &except_vec4, 0x8);
1513 * Some CPUs can enable/disable for cache parity detection, but does
1514 * it different ways.
1516 parity_protection_init();
1519 * The Data Bus Errors / Instruction Bus Errors are signaled
1520 * by external hardware. Therefore these two exceptions
1521 * may have board specific handlers.
1526 set_except_vector(0, handle_int);
1527 set_except_vector(1, handle_tlbm);
1528 set_except_vector(2, handle_tlbl);
1529 set_except_vector(3, handle_tlbs);
1531 set_except_vector(4, handle_adel);
1532 set_except_vector(5, handle_ades);
1534 set_except_vector(6, handle_ibe);
1535 set_except_vector(7, handle_dbe);
1537 set_except_vector(8, handle_sys);
1538 set_except_vector(9, handle_bp);
1539 set_except_vector(10, rdhwr_noopt ? handle_ri :
1540 (cpu_has_vtag_icache ?
1541 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1542 set_except_vector(11, handle_cpu);
1543 set_except_vector(12, handle_ov);
1544 set_except_vector(13, handle_tr);
1546 if (current_cpu_data.cputype == CPU_R6000 ||
1547 current_cpu_data.cputype == CPU_R6000A) {
1549 * The R6000 is the only R-series CPU that features a machine
1550 * check exception (similar to the R4000 cache error) and
1551 * unaligned ldc1/sdc1 exception. The handlers have not been
1552 * written yet. Well, anyway there is no R6000 machine on the
1553 * current list of targets for Linux/MIPS.
1554 * (Duh, crap, there is someone with a triple R6k machine)
1556 //set_except_vector(14, handle_mc);
1557 //set_except_vector(15, handle_ndc);
1561 if (board_nmi_handler_setup)
1562 board_nmi_handler_setup();
1564 if (cpu_has_fpu && !cpu_has_nofpuex)
1565 set_except_vector(15, handle_fpe);
1567 set_except_vector(22, handle_mdmx);
1570 set_except_vector(24, handle_mcheck);
1573 set_except_vector(25, handle_mt);
1575 set_except_vector(26, handle_dsp);
1578 /* Special exception: R4[04]00 uses also the divec space. */
1579 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1580 else if (cpu_has_4kex)
1581 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1583 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1586 #ifdef CONFIG_MIPS32_COMPAT
1590 flush_icache_range(ebase, ebase + 0x400);
1591 flush_tlb_handlers();