2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
29 #include <asm/bootinfo.h>
30 #include <asm/branch.h>
31 #include <asm/break.h>
35 #include <asm/mipsregs.h>
36 #include <asm/mipsmtregs.h>
37 #include <asm/module.h>
38 #include <asm/pgtable.h>
39 #include <asm/ptrace.h>
40 #include <asm/sections.h>
41 #include <asm/system.h>
42 #include <asm/tlbdebug.h>
43 #include <asm/traps.h>
44 #include <asm/uaccess.h>
45 #include <asm/mmu_context.h>
46 #include <asm/types.h>
47 #include <asm/stacktrace.h>
49 extern void check_wait(void);
50 extern asmlinkage void r4k_wait(void);
51 extern asmlinkage void rollback_handle_int(void);
52 extern asmlinkage void handle_int(void);
53 extern asmlinkage void handle_tlbm(void);
54 extern asmlinkage void handle_tlbl(void);
55 extern asmlinkage void handle_tlbs(void);
56 extern asmlinkage void handle_adel(void);
57 extern asmlinkage void handle_ades(void);
58 extern asmlinkage void handle_ibe(void);
59 extern asmlinkage void handle_dbe(void);
60 extern asmlinkage void handle_sys(void);
61 extern asmlinkage void handle_bp(void);
62 extern asmlinkage void handle_ri(void);
63 extern asmlinkage void handle_ri_rdhwr_vivt(void);
64 extern asmlinkage void handle_ri_rdhwr(void);
65 extern asmlinkage void handle_cpu(void);
66 extern asmlinkage void handle_ov(void);
67 extern asmlinkage void handle_tr(void);
68 extern asmlinkage void handle_fpe(void);
69 extern asmlinkage void handle_mdmx(void);
70 extern asmlinkage void handle_watch(void);
71 extern asmlinkage void handle_mt(void);
72 extern asmlinkage void handle_dsp(void);
73 extern asmlinkage void handle_mcheck(void);
74 extern asmlinkage void handle_reserved(void);
76 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
77 struct mips_fpu_struct *ctx, int has_fpu);
79 void (*board_be_init)(void);
80 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
81 void (*board_nmi_handler_setup)(void);
82 void (*board_ejtag_handler_setup)(void);
83 void (*board_bind_eic_interrupt)(int irq, int regset);
86 static void show_raw_backtrace(unsigned long reg29)
88 unsigned long *sp = (unsigned long *)(reg29 & ~3);
91 printk("Call Trace:");
92 #ifdef CONFIG_KALLSYMS
95 while (!kstack_end(sp)) {
96 unsigned long __user *p =
97 (unsigned long __user *)(unsigned long)sp++;
98 if (__get_user(addr, p)) {
99 printk(" (Bad stack address)");
102 if (__kernel_text_address(addr))
108 #ifdef CONFIG_KALLSYMS
110 static int __init set_raw_show_trace(char *str)
115 __setup("raw_show_trace", set_raw_show_trace);
118 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
120 unsigned long sp = regs->regs[29];
121 unsigned long ra = regs->regs[31];
122 unsigned long pc = regs->cp0_epc;
124 if (raw_show_trace || !__kernel_text_address(pc)) {
125 show_raw_backtrace(sp);
128 printk("Call Trace:\n");
131 pc = unwind_stack(task, &sp, pc, &ra);
137 * This routine abuses get_user()/put_user() to reference pointers
138 * with at least a bit of error checking ...
140 static void show_stacktrace(struct task_struct *task,
141 const struct pt_regs *regs)
143 const int field = 2 * sizeof(unsigned long);
146 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
150 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
151 if (i && ((i % (64 / field)) == 0))
158 if (__get_user(stackdata, sp++)) {
159 printk(" (Bad stack address)");
163 printk(" %0*lx", field, stackdata);
167 show_backtrace(task, regs);
170 void show_stack(struct task_struct *task, unsigned long *sp)
174 regs.regs[29] = (unsigned long)sp;
178 if (task && task != current) {
179 regs.regs[29] = task->thread.reg29;
181 regs.cp0_epc = task->thread.reg31;
183 prepare_frametrace(®s);
186 show_stacktrace(task, ®s);
190 * The architecture-independent dump_stack generator
192 void dump_stack(void)
196 prepare_frametrace(®s);
197 show_backtrace(current, ®s);
200 EXPORT_SYMBOL(dump_stack);
202 static void show_code(unsigned int __user *pc)
205 unsigned short __user *pc16 = NULL;
209 if ((unsigned long)pc & 1)
210 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
211 for(i = -3 ; i < 6 ; i++) {
213 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
214 printk(" (Bad address in epc)\n");
217 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
221 static void __show_regs(const struct pt_regs *regs)
223 const int field = 2 * sizeof(unsigned long);
224 unsigned int cause = regs->cp0_cause;
227 printk("Cpu %d\n", smp_processor_id());
230 * Saved main processor registers
232 for (i = 0; i < 32; ) {
236 printk(" %0*lx", field, 0UL);
237 else if (i == 26 || i == 27)
238 printk(" %*s", field, "");
240 printk(" %0*lx", field, regs->regs[i]);
247 #ifdef CONFIG_CPU_HAS_SMARTMIPS
248 printk("Acx : %0*lx\n", field, regs->acx);
250 printk("Hi : %0*lx\n", field, regs->hi);
251 printk("Lo : %0*lx\n", field, regs->lo);
254 * Saved cp0 registers
256 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
257 (void *) regs->cp0_epc);
258 printk(" %s\n", print_tainted());
259 printk("ra : %0*lx %pS\n", field, regs->regs[31],
260 (void *) regs->regs[31]);
262 printk("Status: %08x ", (uint32_t) regs->cp0_status);
264 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
265 if (regs->cp0_status & ST0_KUO)
267 if (regs->cp0_status & ST0_IEO)
269 if (regs->cp0_status & ST0_KUP)
271 if (regs->cp0_status & ST0_IEP)
273 if (regs->cp0_status & ST0_KUC)
275 if (regs->cp0_status & ST0_IEC)
278 if (regs->cp0_status & ST0_KX)
280 if (regs->cp0_status & ST0_SX)
282 if (regs->cp0_status & ST0_UX)
284 switch (regs->cp0_status & ST0_KSU) {
289 printk("SUPERVISOR ");
298 if (regs->cp0_status & ST0_ERL)
300 if (regs->cp0_status & ST0_EXL)
302 if (regs->cp0_status & ST0_IE)
307 printk("Cause : %08x\n", cause);
309 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
310 if (1 <= cause && cause <= 5)
311 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
313 printk("PrId : %08x (%s)\n", read_c0_prid(),
318 * FIXME: really the generic show_regs should take a const pointer argument.
320 void show_regs(struct pt_regs *regs)
322 __show_regs((struct pt_regs *)regs);
325 void show_registers(const struct pt_regs *regs)
327 const int field = 2 * sizeof(unsigned long);
331 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
332 current->comm, current->pid, current_thread_info(), current,
333 field, current_thread_info()->tp_value);
334 if (cpu_has_userlocal) {
337 tls = read_c0_userlocal();
338 if (tls != current_thread_info()->tp_value)
339 printk("*HwTLS: %0*lx\n", field, tls);
342 show_stacktrace(current, regs);
343 show_code((unsigned int __user *) regs->cp0_epc);
347 static DEFINE_SPINLOCK(die_lock);
349 void __noreturn die(const char * str, const struct pt_regs * regs)
351 static int die_counter;
352 #ifdef CONFIG_MIPS_MT_SMTC
353 unsigned long dvpret = dvpe();
354 #endif /* CONFIG_MIPS_MT_SMTC */
357 spin_lock_irq(&die_lock);
359 #ifdef CONFIG_MIPS_MT_SMTC
360 mips_mt_regdump(dvpret);
361 #endif /* CONFIG_MIPS_MT_SMTC */
362 printk("%s[#%d]:\n", str, ++die_counter);
363 show_registers(regs);
364 add_taint(TAINT_DIE);
365 spin_unlock_irq(&die_lock);
368 panic("Fatal exception in interrupt");
371 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
373 panic("Fatal exception");
379 extern struct exception_table_entry __start___dbe_table[];
380 extern struct exception_table_entry __stop___dbe_table[];
383 " .section __dbe_table, \"a\"\n"
386 /* Given an address, look for it in the exception tables. */
387 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
389 const struct exception_table_entry *e;
391 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
393 e = search_module_dbetables(addr);
397 asmlinkage void do_be(struct pt_regs *regs)
399 const int field = 2 * sizeof(unsigned long);
400 const struct exception_table_entry *fixup = NULL;
401 int data = regs->cp0_cause & 4;
402 int action = MIPS_BE_FATAL;
404 /* XXX For now. Fixme, this searches the wrong table ... */
405 if (data && !user_mode(regs))
406 fixup = search_dbe_tables(exception_epc(regs));
409 action = MIPS_BE_FIXUP;
411 if (board_be_handler)
412 action = board_be_handler(regs, fixup != NULL);
415 case MIPS_BE_DISCARD:
419 regs->cp0_epc = fixup->nextinsn;
428 * Assume it would be too dangerous to continue ...
430 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
431 data ? "Data" : "Instruction",
432 field, regs->cp0_epc, field, regs->regs[31]);
433 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0)
437 die_if_kernel("Oops", regs);
438 force_sig(SIGBUS, current);
442 * ll/sc, rdhwr, sync emulation
445 #define OPCODE 0xfc000000
446 #define BASE 0x03e00000
447 #define RT 0x001f0000
448 #define OFFSET 0x0000ffff
449 #define LL 0xc0000000
450 #define SC 0xe0000000
451 #define SPEC0 0x00000000
452 #define SPEC3 0x7c000000
453 #define RD 0x0000f800
454 #define FUNC 0x0000003f
455 #define SYNC 0x0000000f
456 #define RDHWR 0x0000003b
459 * The ll_bit is cleared by r*_switch.S
462 unsigned long ll_bit;
464 static struct task_struct *ll_task = NULL;
466 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
468 unsigned long value, __user *vaddr;
472 * analyse the ll instruction that just caused a ri exception
473 * and put the referenced address to addr.
476 /* sign extend offset */
477 offset = opcode & OFFSET;
481 vaddr = (unsigned long __user *)
482 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
484 if ((unsigned long)vaddr & 3)
486 if (get_user(value, vaddr))
491 if (ll_task == NULL || ll_task == current) {
500 regs->regs[(opcode & RT) >> 16] = value;
505 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
507 unsigned long __user *vaddr;
512 * analyse the sc instruction that just caused a ri exception
513 * and put the referenced address to addr.
516 /* sign extend offset */
517 offset = opcode & OFFSET;
521 vaddr = (unsigned long __user *)
522 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
523 reg = (opcode & RT) >> 16;
525 if ((unsigned long)vaddr & 3)
530 if (ll_bit == 0 || ll_task != current) {
538 if (put_user(regs->regs[reg], vaddr))
547 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
548 * opcodes are supposed to result in coprocessor unusable exceptions if
549 * executed on ll/sc-less processors. That's the theory. In practice a
550 * few processors such as NEC's VR4100 throw reserved instruction exceptions
551 * instead, so we're doing the emulation thing in both exception handlers.
553 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
555 if ((opcode & OPCODE) == LL)
556 return simulate_ll(regs, opcode);
557 if ((opcode & OPCODE) == SC)
558 return simulate_sc(regs, opcode);
560 return -1; /* Must be something else ... */
564 * Simulate trapping 'rdhwr' instructions to provide user accessible
565 * registers not implemented in hardware.
567 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
569 struct thread_info *ti = task_thread_info(current);
571 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
572 int rd = (opcode & RD) >> 11;
573 int rt = (opcode & RT) >> 16;
575 case 0: /* CPU number */
576 regs->regs[rt] = smp_processor_id();
578 case 1: /* SYNCI length */
579 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
580 current_cpu_data.icache.linesz);
582 case 2: /* Read count register */
583 regs->regs[rt] = read_c0_count();
585 case 3: /* Count register resolution */
586 switch (current_cpu_data.cputype) {
596 regs->regs[rt] = ti->tp_value;
607 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
609 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
612 return -1; /* Must be something else ... */
615 asmlinkage void do_ov(struct pt_regs *regs)
619 die_if_kernel("Integer overflow", regs);
621 info.si_code = FPE_INTOVF;
622 info.si_signo = SIGFPE;
624 info.si_addr = (void __user *) regs->cp0_epc;
625 force_sig_info(SIGFPE, &info, current);
629 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
631 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
635 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0)
638 die_if_kernel("FP exception in kernel code", regs);
640 if (fcr31 & FPU_CSR_UNI_X) {
644 * Unimplemented operation exception. If we've got the full
645 * software emulator on-board, let's use it...
647 * Force FPU to dump state into task/thread context. We're
648 * moving a lot of data here for what is probably a single
649 * instruction, but the alternative is to pre-decode the FP
650 * register operands before invoking the emulator, which seems
651 * a bit extreme for what should be an infrequent event.
653 /* Ensure 'resume' not overwrite saved fp context again. */
656 /* Run the emulator */
657 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1);
660 * We can't allow the emulated instruction to leave any of
661 * the cause bit set in $fcr31.
663 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
665 /* Restore the hardware register state */
666 own_fpu(1); /* Using the FPU again. */
668 /* If something went wrong, signal */
670 force_sig(sig, current);
673 } else if (fcr31 & FPU_CSR_INV_X)
674 info.si_code = FPE_FLTINV;
675 else if (fcr31 & FPU_CSR_DIV_X)
676 info.si_code = FPE_FLTDIV;
677 else if (fcr31 & FPU_CSR_OVF_X)
678 info.si_code = FPE_FLTOVF;
679 else if (fcr31 & FPU_CSR_UDF_X)
680 info.si_code = FPE_FLTUND;
681 else if (fcr31 & FPU_CSR_INE_X)
682 info.si_code = FPE_FLTRES;
684 info.si_code = __SI_FAULT;
685 info.si_signo = SIGFPE;
687 info.si_addr = (void __user *) regs->cp0_epc;
688 force_sig_info(SIGFPE, &info, current);
691 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
697 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
701 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
702 * insns, even for trap and break codes that indicate arithmetic
703 * failures. Weird ...
704 * But should we continue the brokenness??? --macro
709 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
710 die_if_kernel(b, regs);
711 if (code == BRK_DIVZERO)
712 info.si_code = FPE_INTDIV;
714 info.si_code = FPE_INTOVF;
715 info.si_signo = SIGFPE;
717 info.si_addr = (void __user *) regs->cp0_epc;
718 force_sig_info(SIGFPE, &info, current);
721 die_if_kernel("Kernel bug detected", regs);
722 force_sig(SIGTRAP, current);
725 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
726 die_if_kernel(b, regs);
727 force_sig(SIGTRAP, current);
731 asmlinkage void do_bp(struct pt_regs *regs)
733 unsigned int opcode, bcode;
735 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
739 * There is the ancient bug in the MIPS assemblers that the break
740 * code starts left to bit 16 instead to bit 6 in the opcode.
741 * Gas is bug-compatible, but not always, grrr...
742 * We handle both cases with a simple heuristics. --macro
744 bcode = ((opcode >> 6) & ((1 << 20) - 1));
745 if (bcode >= (1 << 10))
748 do_trap_or_bp(regs, bcode, "Break");
752 force_sig(SIGSEGV, current);
755 asmlinkage void do_tr(struct pt_regs *regs)
757 unsigned int opcode, tcode = 0;
759 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
762 /* Immediate versions don't provide a code. */
763 if (!(opcode & OPCODE))
764 tcode = ((opcode >> 6) & ((1 << 10) - 1));
766 do_trap_or_bp(regs, tcode, "Trap");
770 force_sig(SIGSEGV, current);
773 asmlinkage void do_ri(struct pt_regs *regs)
775 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
776 unsigned long old_epc = regs->cp0_epc;
777 unsigned int opcode = 0;
780 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0)
784 die_if_kernel("Reserved instruction in kernel code", regs);
786 if (unlikely(compute_return_epc(regs) < 0))
789 if (unlikely(get_user(opcode, epc) < 0))
792 if (!cpu_has_llsc && status < 0)
793 status = simulate_llsc(regs, opcode);
796 status = simulate_rdhwr(regs, opcode);
799 status = simulate_sync(regs, opcode);
804 if (unlikely(status > 0)) {
805 regs->cp0_epc = old_epc; /* Undo skip-over. */
806 force_sig(status, current);
811 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
812 * emulated more than some threshold number of instructions, force migration to
813 * a "CPU" that has FP support.
815 static void mt_ase_fp_affinity(void)
817 #ifdef CONFIG_MIPS_MT_FPAFF
818 if (mt_fpemul_threshold > 0 &&
819 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
821 * If there's no FPU present, or if the application has already
822 * restricted the allowed set to exclude any CPUs with FPUs,
823 * we'll skip the procedure.
825 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
828 cpus_and(tmask, current->thread.user_cpus_allowed,
830 set_cpus_allowed(current, tmask);
831 set_thread_flag(TIF_FPUBOUND);
834 #endif /* CONFIG_MIPS_MT_FPAFF */
837 asmlinkage void do_cpu(struct pt_regs *regs)
839 unsigned int __user *epc;
840 unsigned long old_epc;
845 die_if_kernel("do_cpu invoked from kernel context!", regs);
847 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
851 epc = (unsigned int __user *)exception_epc(regs);
852 old_epc = regs->cp0_epc;
856 if (unlikely(compute_return_epc(regs) < 0))
859 if (unlikely(get_user(opcode, epc) < 0))
862 if (!cpu_has_llsc && status < 0)
863 status = simulate_llsc(regs, opcode);
866 status = simulate_rdhwr(regs, opcode);
871 if (unlikely(status > 0)) {
872 regs->cp0_epc = old_epc; /* Undo skip-over. */
873 force_sig(status, current);
879 if (used_math()) /* Using the FPU again. */
881 else { /* First time FPU user. */
886 if (!raw_cpu_has_fpu) {
888 sig = fpu_emulator_cop1Handler(regs,
889 ¤t->thread.fpu, 0);
891 force_sig(sig, current);
893 mt_ase_fp_affinity();
903 force_sig(SIGILL, current);
906 asmlinkage void do_mdmx(struct pt_regs *regs)
908 force_sig(SIGILL, current);
911 asmlinkage void do_watch(struct pt_regs *regs)
914 * We use the watch exception where available to detect stack
919 panic("Caught WATCH exception - probably caused by stack overflow.");
922 asmlinkage void do_mcheck(struct pt_regs *regs)
924 const int field = 2 * sizeof(unsigned long);
925 int multi_match = regs->cp0_status & ST0_TS;
930 printk("Index : %0x\n", read_c0_index());
931 printk("Pagemask: %0x\n", read_c0_pagemask());
932 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
933 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
934 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
939 show_code((unsigned int __user *) regs->cp0_epc);
942 * Some chips may have other causes of machine check (e.g. SB1
945 panic("Caught Machine Check exception - %scaused by multiple "
946 "matching entries in the TLB.",
947 (multi_match) ? "" : "not ");
950 asmlinkage void do_mt(struct pt_regs *regs)
954 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
955 >> VPECONTROL_EXCPT_SHIFT;
958 printk(KERN_DEBUG "Thread Underflow\n");
961 printk(KERN_DEBUG "Thread Overflow\n");
964 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
967 printk(KERN_DEBUG "Gating Storage Exception\n");
970 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
973 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
976 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
980 die_if_kernel("MIPS MT Thread exception in kernel", regs);
982 force_sig(SIGILL, current);
986 asmlinkage void do_dsp(struct pt_regs *regs)
989 panic("Unexpected DSP exception\n");
991 force_sig(SIGILL, current);
994 asmlinkage void do_reserved(struct pt_regs *regs)
997 * Game over - no way to handle this if it ever occurs. Most probably
998 * caused by a new unknown cpu type or after another deadly
999 * hard/software error.
1002 panic("Caught reserved exception %ld - should not happen.",
1003 (regs->cp0_cause & 0x7f) >> 2);
1006 static int __initdata l1parity = 1;
1007 static int __init nol1parity(char *s)
1012 __setup("nol1par", nol1parity);
1013 static int __initdata l2parity = 1;
1014 static int __init nol2parity(char *s)
1019 __setup("nol2par", nol2parity);
1022 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1023 * it different ways.
1025 static inline void parity_protection_init(void)
1027 switch (current_cpu_type()) {
1033 #define ERRCTL_PE 0x80000000
1034 #define ERRCTL_L2P 0x00800000
1035 unsigned long errctl;
1036 unsigned int l1parity_present, l2parity_present;
1038 errctl = read_c0_ecc();
1039 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1041 /* probe L1 parity support */
1042 write_c0_ecc(errctl | ERRCTL_PE);
1043 back_to_back_c0_hazard();
1044 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1046 /* probe L2 parity support */
1047 write_c0_ecc(errctl|ERRCTL_L2P);
1048 back_to_back_c0_hazard();
1049 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1051 if (l1parity_present && l2parity_present) {
1053 errctl |= ERRCTL_PE;
1054 if (l1parity ^ l2parity)
1055 errctl |= ERRCTL_L2P;
1056 } else if (l1parity_present) {
1058 errctl |= ERRCTL_PE;
1059 } else if (l2parity_present) {
1061 errctl |= ERRCTL_L2P;
1063 /* No parity available */
1066 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1068 write_c0_ecc(errctl);
1069 back_to_back_c0_hazard();
1070 errctl = read_c0_ecc();
1071 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1073 if (l1parity_present)
1074 printk(KERN_INFO "Cache parity protection %sabled\n",
1075 (errctl & ERRCTL_PE) ? "en" : "dis");
1077 if (l2parity_present) {
1078 if (l1parity_present && l1parity)
1079 errctl ^= ERRCTL_L2P;
1080 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1081 (errctl & ERRCTL_L2P) ? "en" : "dis");
1087 write_c0_ecc(0x80000000);
1088 back_to_back_c0_hazard();
1089 /* Set the PE bit (bit 31) in the c0_errctl register. */
1090 printk(KERN_INFO "Cache parity protection %sabled\n",
1091 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1095 /* Clear the DE bit (bit 16) in the c0_status register. */
1096 printk(KERN_INFO "Enable cache parity protection for "
1097 "MIPS 20KC/25KF CPUs.\n");
1098 clear_c0_status(ST0_DE);
1105 asmlinkage void cache_parity_error(void)
1107 const int field = 2 * sizeof(unsigned long);
1108 unsigned int reg_val;
1110 /* For the moment, report the problem and hang. */
1111 printk("Cache error exception:\n");
1112 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1113 reg_val = read_c0_cacheerr();
1114 printk("c0_cacheerr == %08x\n", reg_val);
1116 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1117 reg_val & (1<<30) ? "secondary" : "primary",
1118 reg_val & (1<<31) ? "data" : "insn");
1119 printk("Error bits: %s%s%s%s%s%s%s\n",
1120 reg_val & (1<<29) ? "ED " : "",
1121 reg_val & (1<<28) ? "ET " : "",
1122 reg_val & (1<<26) ? "EE " : "",
1123 reg_val & (1<<25) ? "EB " : "",
1124 reg_val & (1<<24) ? "EI " : "",
1125 reg_val & (1<<23) ? "E1 " : "",
1126 reg_val & (1<<22) ? "E0 " : "");
1127 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1129 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1130 if (reg_val & (1<<22))
1131 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1133 if (reg_val & (1<<23))
1134 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1137 panic("Can't handle the cache error!");
1141 * SDBBP EJTAG debug exception handler.
1142 * We skip the instruction and return to the next instruction.
1144 void ejtag_exception_handler(struct pt_regs *regs)
1146 const int field = 2 * sizeof(unsigned long);
1147 unsigned long depc, old_epc;
1150 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1151 depc = read_c0_depc();
1152 debug = read_c0_debug();
1153 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1154 if (debug & 0x80000000) {
1156 * In branch delay slot.
1157 * We cheat a little bit here and use EPC to calculate the
1158 * debug return address (DEPC). EPC is restored after the
1161 old_epc = regs->cp0_epc;
1162 regs->cp0_epc = depc;
1163 __compute_return_epc(regs);
1164 depc = regs->cp0_epc;
1165 regs->cp0_epc = old_epc;
1168 write_c0_depc(depc);
1171 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1172 write_c0_debug(debug | 0x100);
1177 * NMI exception handler.
1179 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1182 printk("NMI taken!!!!\n");
1186 #define VECTORSPACING 0x100 /* for EI/VI mode */
1188 unsigned long ebase;
1189 unsigned long exception_handlers[32];
1190 unsigned long vi_handlers[64];
1193 * As a side effect of the way this is implemented we're limited
1194 * to interrupt handlers in the address range from
1195 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1197 void *set_except_vector(int n, void *addr)
1199 unsigned long handler = (unsigned long) addr;
1200 unsigned long old_handler = exception_handlers[n];
1202 exception_handlers[n] = handler;
1203 if (n == 0 && cpu_has_divec) {
1204 *(u32 *)(ebase + 0x200) = 0x08000000 |
1205 (0x03ffffff & (handler >> 2));
1206 local_flush_icache_range(ebase + 0x200, ebase + 0x204);
1208 return (void *)old_handler;
1211 static asmlinkage void do_default_vi(void)
1213 show_regs(get_irq_regs());
1214 panic("Caught unexpected vectored interrupt.");
1217 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1219 unsigned long handler;
1220 unsigned long old_handler = vi_handlers[n];
1221 int srssets = current_cpu_data.srsets;
1225 if (!cpu_has_veic && !cpu_has_vint)
1229 handler = (unsigned long) do_default_vi;
1232 handler = (unsigned long) addr;
1233 vi_handlers[n] = (unsigned long) addr;
1235 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1238 panic("Shadow register set %d not supported", srs);
1241 if (board_bind_eic_interrupt)
1242 board_bind_eic_interrupt(n, srs);
1243 } else if (cpu_has_vint) {
1244 /* SRSMap is only defined if shadow sets are implemented */
1246 change_c0_srsmap(0xf << n*4, srs << n*4);
1251 * If no shadow set is selected then use the default handler
1252 * that does normal register saving and a standard interrupt exit
1255 extern char except_vec_vi, except_vec_vi_lui;
1256 extern char except_vec_vi_ori, except_vec_vi_end;
1257 extern char rollback_except_vec_vi;
1258 char *vec_start = (cpu_wait == r4k_wait) ?
1259 &rollback_except_vec_vi : &except_vec_vi;
1260 #ifdef CONFIG_MIPS_MT_SMTC
1262 * We need to provide the SMTC vectored interrupt handler
1263 * not only with the address of the handler, but with the
1264 * Status.IM bit to be masked before going there.
1266 extern char except_vec_vi_mori;
1267 const int mori_offset = &except_vec_vi_mori - vec_start;
1268 #endif /* CONFIG_MIPS_MT_SMTC */
1269 const int handler_len = &except_vec_vi_end - vec_start;
1270 const int lui_offset = &except_vec_vi_lui - vec_start;
1271 const int ori_offset = &except_vec_vi_ori - vec_start;
1273 if (handler_len > VECTORSPACING) {
1275 * Sigh... panicing won't help as the console
1276 * is probably not configured :(
1278 panic("VECTORSPACING too small");
1281 memcpy(b, vec_start, handler_len);
1282 #ifdef CONFIG_MIPS_MT_SMTC
1283 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1285 w = (u32 *)(b + mori_offset);
1286 *w = (*w & 0xffff0000) | (0x100 << n);
1287 #endif /* CONFIG_MIPS_MT_SMTC */
1288 w = (u32 *)(b + lui_offset);
1289 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1290 w = (u32 *)(b + ori_offset);
1291 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1292 local_flush_icache_range((unsigned long)b,
1293 (unsigned long)(b+handler_len));
1297 * In other cases jump directly to the interrupt handler
1299 * It is the handlers responsibility to save registers if required
1300 * (eg hi/lo) and return from the exception using "eret"
1303 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1305 local_flush_icache_range((unsigned long)b,
1306 (unsigned long)(b+8));
1309 return (void *)old_handler;
1312 void *set_vi_handler(int n, vi_handler_t addr)
1314 return set_vi_srs_handler(n, addr, 0);
1318 * This is used by native signal handling
1320 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1321 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1323 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1324 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1326 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1327 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1330 static int smp_save_fp_context(struct sigcontext __user *sc)
1332 return raw_cpu_has_fpu
1333 ? _save_fp_context(sc)
1334 : fpu_emulator_save_context(sc);
1337 static int smp_restore_fp_context(struct sigcontext __user *sc)
1339 return raw_cpu_has_fpu
1340 ? _restore_fp_context(sc)
1341 : fpu_emulator_restore_context(sc);
1345 static inline void signal_init(void)
1348 /* For now just do the cpu_has_fpu check when the functions are invoked */
1349 save_fp_context = smp_save_fp_context;
1350 restore_fp_context = smp_restore_fp_context;
1353 save_fp_context = _save_fp_context;
1354 restore_fp_context = _restore_fp_context;
1356 save_fp_context = fpu_emulator_save_context;
1357 restore_fp_context = fpu_emulator_restore_context;
1362 #ifdef CONFIG_MIPS32_COMPAT
1365 * This is used by 32-bit signal stuff on the 64-bit kernel
1367 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1368 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1370 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1371 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1373 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1374 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1376 static inline void signal32_init(void)
1379 save_fp_context32 = _save_fp_context32;
1380 restore_fp_context32 = _restore_fp_context32;
1382 save_fp_context32 = fpu_emulator_save_context32;
1383 restore_fp_context32 = fpu_emulator_restore_context32;
1388 extern void cpu_cache_init(void);
1389 extern void tlb_init(void);
1390 extern void flush_tlb_handlers(void);
1395 int cp0_compare_irq;
1398 * Performance counter IRQ or -1 if shared with timer
1400 int cp0_perfcount_irq;
1401 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1403 static int __cpuinitdata noulri;
1405 static int __init ulri_disable(char *s)
1407 pr_info("Disabling ulri\n");
1412 __setup("noulri", ulri_disable);
1414 void __cpuinit per_cpu_trap_init(void)
1416 unsigned int cpu = smp_processor_id();
1417 unsigned int status_set = ST0_CU0;
1418 #ifdef CONFIG_MIPS_MT_SMTC
1419 int secondaryTC = 0;
1420 int bootTC = (cpu == 0);
1423 * Only do per_cpu_trap_init() for first TC of Each VPE.
1424 * Note that this hack assumes that the SMTC init code
1425 * assigns TCs consecutively and in ascending order.
1428 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1429 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1431 #endif /* CONFIG_MIPS_MT_SMTC */
1434 * Disable coprocessors and select 32-bit or 64-bit addressing
1435 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1436 * flag that some firmware may have left set and the TS bit (for
1437 * IP27). Set XX for ISA IV code to work.
1440 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1442 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1443 status_set |= ST0_XX;
1445 status_set |= ST0_MX;
1447 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1450 if (cpu_has_mips_r2) {
1451 unsigned int enable = 0x0000000f;
1453 if (!noulri && cpu_has_userlocal)
1454 enable |= (1 << 29);
1456 write_c0_hwrena(enable);
1459 #ifdef CONFIG_MIPS_MT_SMTC
1461 #endif /* CONFIG_MIPS_MT_SMTC */
1463 if (cpu_has_veic || cpu_has_vint) {
1464 write_c0_ebase(ebase);
1465 /* Setting vector spacing enables EI/VI mode */
1466 change_c0_intctl(0x3e0, VECTORSPACING);
1468 if (cpu_has_divec) {
1469 if (cpu_has_mipsmt) {
1470 unsigned int vpflags = dvpe();
1471 set_c0_cause(CAUSEF_IV);
1474 set_c0_cause(CAUSEF_IV);
1478 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1480 * o read IntCtl.IPTI to determine the timer interrupt
1481 * o read IntCtl.IPPCI to determine the performance counter interrupt
1483 if (cpu_has_mips_r2) {
1484 cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
1485 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
1486 if (cp0_perfcount_irq == cp0_compare_irq)
1487 cp0_perfcount_irq = -1;
1489 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1490 cp0_perfcount_irq = -1;
1493 #ifdef CONFIG_MIPS_MT_SMTC
1495 #endif /* CONFIG_MIPS_MT_SMTC */
1497 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1498 TLBMISS_HANDLER_SETUP();
1500 atomic_inc(&init_mm.mm_count);
1501 current->active_mm = &init_mm;
1502 BUG_ON(current->mm);
1503 enter_lazy_tlb(&init_mm, current);
1505 #ifdef CONFIG_MIPS_MT_SMTC
1507 #endif /* CONFIG_MIPS_MT_SMTC */
1510 #ifdef CONFIG_MIPS_MT_SMTC
1511 } else if (!secondaryTC) {
1513 * First TC in non-boot VPE must do subset of tlb_init()
1514 * for MMU countrol registers.
1516 write_c0_pagemask(PM_DEFAULT_MASK);
1519 #endif /* CONFIG_MIPS_MT_SMTC */
1522 /* Install CPU exception handler */
1523 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1525 memcpy((void *)(ebase + offset), addr, size);
1526 local_flush_icache_range(ebase + offset, ebase + offset + size);
1529 static char panic_null_cerr[] __cpuinitdata =
1530 "Trying to set NULL cache error exception handler";
1532 /* Install uncached CPU exception handler */
1533 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1537 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1540 unsigned long uncached_ebase = TO_UNCAC(ebase);
1544 panic(panic_null_cerr);
1546 memcpy((void *)(uncached_ebase + offset), addr, size);
1549 static int __initdata rdhwr_noopt;
1550 static int __init set_rdhwr_noopt(char *str)
1556 __setup("rdhwr_noopt", set_rdhwr_noopt);
1558 void __init trap_init(void)
1560 extern char except_vec3_generic, except_vec3_r4000;
1561 extern char except_vec4;
1566 rollback = (cpu_wait == r4k_wait);
1568 #if defined(CONFIG_KGDB)
1569 if (kgdb_early_setup)
1570 return; /* Already done */
1573 if (cpu_has_veic || cpu_has_vint)
1574 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1578 per_cpu_trap_init();
1581 * Copy the generic exception handlers to their final destination.
1582 * This will be overriden later as suitable for a particular
1585 set_handler(0x180, &except_vec3_generic, 0x80);
1588 * Setup default vectors
1590 for (i = 0; i <= 31; i++)
1591 set_except_vector(i, handle_reserved);
1594 * Copy the EJTAG debug exception vector handler code to it's final
1597 if (cpu_has_ejtag && board_ejtag_handler_setup)
1598 board_ejtag_handler_setup();
1601 * Only some CPUs have the watch exceptions.
1604 set_except_vector(23, handle_watch);
1607 * Initialise interrupt handlers
1609 if (cpu_has_veic || cpu_has_vint) {
1610 int nvec = cpu_has_veic ? 64 : 8;
1611 for (i = 0; i < nvec; i++)
1612 set_vi_handler(i, NULL);
1614 else if (cpu_has_divec)
1615 set_handler(0x200, &except_vec4, 0x8);
1618 * Some CPUs can enable/disable for cache parity detection, but does
1619 * it different ways.
1621 parity_protection_init();
1624 * The Data Bus Errors / Instruction Bus Errors are signaled
1625 * by external hardware. Therefore these two exceptions
1626 * may have board specific handlers.
1631 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1632 set_except_vector(1, handle_tlbm);
1633 set_except_vector(2, handle_tlbl);
1634 set_except_vector(3, handle_tlbs);
1636 set_except_vector(4, handle_adel);
1637 set_except_vector(5, handle_ades);
1639 set_except_vector(6, handle_ibe);
1640 set_except_vector(7, handle_dbe);
1642 set_except_vector(8, handle_sys);
1643 set_except_vector(9, handle_bp);
1644 set_except_vector(10, rdhwr_noopt ? handle_ri :
1645 (cpu_has_vtag_icache ?
1646 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1647 set_except_vector(11, handle_cpu);
1648 set_except_vector(12, handle_ov);
1649 set_except_vector(13, handle_tr);
1651 if (current_cpu_type() == CPU_R6000 ||
1652 current_cpu_type() == CPU_R6000A) {
1654 * The R6000 is the only R-series CPU that features a machine
1655 * check exception (similar to the R4000 cache error) and
1656 * unaligned ldc1/sdc1 exception. The handlers have not been
1657 * written yet. Well, anyway there is no R6000 machine on the
1658 * current list of targets for Linux/MIPS.
1659 * (Duh, crap, there is someone with a triple R6k machine)
1661 //set_except_vector(14, handle_mc);
1662 //set_except_vector(15, handle_ndc);
1666 if (board_nmi_handler_setup)
1667 board_nmi_handler_setup();
1669 if (cpu_has_fpu && !cpu_has_nofpuex)
1670 set_except_vector(15, handle_fpe);
1672 set_except_vector(22, handle_mdmx);
1675 set_except_vector(24, handle_mcheck);
1678 set_except_vector(25, handle_mt);
1680 set_except_vector(26, handle_dsp);
1683 /* Special exception: R4[04]00 uses also the divec space. */
1684 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1685 else if (cpu_has_4kex)
1686 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1688 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1691 #ifdef CONFIG_MIPS32_COMPAT
1695 local_flush_icache_range(ebase, ebase + 0x400);
1696 flush_tlb_handlers();
1698 sort_extable(__start___dbe_table, __stop___dbe_table);