1 #include <linux/types.h>
2 #include <linux/init.h>
3 #include <linux/kernel_stat.h>
4 #include <linux/sched.h>
5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/mc146818rtc.h>
8 #include <linux/mipsregs.h>
10 #include <linux/timex.h>
12 #include <asm/hardirq.h>
13 #include <asm/div64.h>
17 #include <asm/mc146818-time.h>
18 #include <asm/msc01_ic.h>
20 #include <asm/mips-boards/generic.h>
21 #include <asm/mips-boards/prom.h>
22 #include <asm/mips-boards/simint.h>
25 unsigned long cpu_khz;
27 irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
30 int cpu = smp_processor_id();
33 * CPU 0 handles the global timer interrupt job
34 * resets count/compare registers to trigger next timer int.
36 #ifndef CONFIG_MIPS_MT_SMTC
38 timer_interrupt(irq, dev_id);
40 /* Everyone else needs to reset the timer int here as
41 ll_local_timer_interrupt doesn't */
43 * FIXME: need to cope with counter underflow.
44 * More support needs to be added to kernel/time for
45 * counter/timer interrupts on multiple CPU's
47 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
51 * In SMTC system, one Count/Compare set exists per VPE.
52 * Which TC within a VPE gets the interrupt is essentially
53 * random - we only know that it shouldn't be one with
54 * IXMT set. Whichever TC gets the interrupt needs to
55 * send special interprocessor interrupts to the other
56 * TCs to make sure that they schedule, etc.
58 * That code is specific to the SMTC kernel, not to
59 * the simulation platform, so it's invoked from
60 * the general MIPS timer_interrupt routine.
62 * We have a problem in that the interrupt vector code
63 * had to turn off the timer IM bit to avoid redundant
64 * entries, but we may never get to mips_cpu_irq_end
65 * to turn it back on again if the scheduler gets
66 * involved. So we clear the pending timer here,
67 * and re-enable the mask...
71 write_c0_compare (read_c0_count() - 1);
72 clear_c0_cause(0x100 << cp0_compare_irq);
73 set_c0_status(0x100 << cp0_compare_irq);
77 if (cpu_data[cpu].vpe_id == 0)
78 timer_interrupt(irq, dev_id);
80 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
81 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
83 #endif /* CONFIG_MIPS_MT_SMTC */
86 * every CPU should do profiling and process accounting
88 local_timer_interrupt (irq, dev_id);
92 return timer_interrupt (irq, dev_id);
99 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
101 static unsigned int __init estimate_cpu_frequency(void)
103 unsigned int prid = read_c0_prid() & 0xffff00;
108 * hardwire the board frequency to 12MHz.
111 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
112 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
119 local_irq_save(flags);
121 /* Start counter exactly on falling edge of update flag */
122 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
123 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
125 /* Start r4k counter. */
128 /* Read counter exactly on falling edge of update flag */
129 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
130 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
132 count = read_c0_count();
134 /* restore interrupts */
135 local_irq_restore(flags);
138 mips_hpt_frequency = count;
140 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
141 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
144 count += 5000; /* round */
145 count -= count%10000;
150 void __init sim_time_init(void)
152 unsigned int est_freq, flags;
154 local_irq_save(flags);
156 /* Set Data mode - binary. */
157 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
159 est_freq = estimate_cpu_frequency ();
161 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
162 (est_freq % 1000000) * 100 / 1000000);
164 cpu_khz = est_freq / 1000;
166 local_irq_restore(flags);
169 static int mips_cpu_timer_irq;
171 static void mips_timer_dispatch(void)
173 do_IRQ(mips_cpu_timer_irq);
177 void __init plat_timer_setup(struct irqaction *irq)
180 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
181 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
184 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
185 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
188 /* we are using the cpu counter for timer interrupts */
189 irq->handler = sim_timer_interrupt;
190 setup_irq(mips_cpu_timer_irq, irq);
193 /* irq_desc(riptor) is a global resource, when the interrupt overlaps
194 on seperate cpu's the first one tries to handle the second interrupt.
195 The effect is that the int remains disabled on the second cpu.
196 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
197 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
198 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);