2 * MPC8548 CDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "MPC8548CDS", "MPC85xxCDS";
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot
37 device_type = "memory";
38 reg = <00000000 08000000>; // 128M at 0x0
45 ranges = <00001000 e0001000 000ff000
46 80000000 80000000 10000000
47 e2000000 e2000000 00800000
48 90000000 90000000 10000000
49 e2800000 e2800000 00800000
50 a0000000 a0000000 20000000
51 e3000000 e3000000 01000000>;
52 reg = <e0000000 00001000>; // CCSRBAR
55 memory-controller@2000 {
56 compatible = "fsl,8548-memory-controller";
58 interrupt-parent = <&mpic>;
62 l2-cache-controller@20000 {
63 compatible = "fsl,8548-l2-cache-controller";
65 cache-line-size = <20>; // 32 bytes
66 cache-size = <80000>; // L2, 512K
67 interrupt-parent = <&mpic>;
73 compatible = "fsl-i2c";
76 interrupt-parent = <&mpic>;
84 compatible = "gianfar";
86 phy0: ethernet-phy@0 {
87 interrupt-parent = <&mpic>;
90 device_type = "ethernet-phy";
92 phy1: ethernet-phy@1 {
93 interrupt-parent = <&mpic>;
96 device_type = "ethernet-phy";
98 phy2: ethernet-phy@2 {
99 interrupt-parent = <&mpic>;
102 device_type = "ethernet-phy";
104 phy3: ethernet-phy@3 {
105 interrupt-parent = <&mpic>;
108 device_type = "ethernet-phy";
113 #address-cells = <1>;
115 device_type = "network";
117 compatible = "gianfar";
119 local-mac-address = [ 00 00 00 00 00 00 ];
120 interrupts = <1d 2 1e 2 22 2>;
121 interrupt-parent = <&mpic>;
122 phy-handle = <&phy0>;
126 #address-cells = <1>;
128 device_type = "network";
130 compatible = "gianfar";
132 local-mac-address = [ 00 00 00 00 00 00 ];
133 interrupts = <23 2 24 2 28 2>;
134 interrupt-parent = <&mpic>;
135 phy-handle = <&phy1>;
138 /* eTSEC 3/4 are currently broken
140 #address-cells = <1>;
142 device_type = "network";
144 compatible = "gianfar";
146 local-mac-address = [ 00 00 00 00 00 00 ];
147 interrupts = <1f 2 20 2 21 2>;
148 interrupt-parent = <&mpic>;
149 phy-handle = <&phy2>;
153 #address-cells = <1>;
155 device_type = "network";
157 compatible = "gianfar";
159 local-mac-address = [ 00 00 00 00 00 00 ];
160 interrupts = <25 2 26 2 27 2>;
161 interrupt-parent = <&mpic>;
162 phy-handle = <&phy3>;
167 device_type = "serial";
168 compatible = "ns16550";
169 reg = <4500 100>; // reg base, size
170 clock-frequency = <0>; // should we fill in in uboot?
172 interrupt-parent = <&mpic>;
176 device_type = "serial";
177 compatible = "ns16550";
178 reg = <4600 100>; // reg base, size
179 clock-frequency = <0>; // should we fill in in uboot?
181 interrupt-parent = <&mpic>;
184 global-utilities@e0000 { //global utilities reg
185 compatible = "fsl,mpc8548-guts";
191 interrupt-map-mask = <f800 0 0 7>;
193 /* IDSEL 0x4 (PCIX Slot 2) */
194 02000 0 0 1 &mpic 0 1
195 02000 0 0 2 &mpic 1 1
196 02000 0 0 3 &mpic 2 1
197 02000 0 0 4 &mpic 3 1
199 /* IDSEL 0x5 (PCIX Slot 3) */
200 02800 0 0 1 &mpic 1 1
201 02800 0 0 2 &mpic 2 1
202 02800 0 0 3 &mpic 3 1
203 02800 0 0 4 &mpic 0 1
205 /* IDSEL 0x6 (PCIX Slot 4) */
206 03000 0 0 1 &mpic 2 1
207 03000 0 0 2 &mpic 3 1
208 03000 0 0 3 &mpic 0 1
209 03000 0 0 4 &mpic 1 1
211 /* IDSEL 0x8 (PCIX Slot 5) */
212 04000 0 0 1 &mpic 0 1
213 04000 0 0 2 &mpic 1 1
214 04000 0 0 3 &mpic 2 1
215 04000 0 0 4 &mpic 3 1
217 /* IDSEL 0xC (Tsi310 bridge) */
218 06000 0 0 1 &mpic 0 1
219 06000 0 0 2 &mpic 1 1
220 06000 0 0 3 &mpic 2 1
221 06000 0 0 4 &mpic 3 1
223 /* IDSEL 0x14 (Slot 2) */
224 0a000 0 0 1 &mpic 0 1
225 0a000 0 0 2 &mpic 1 1
226 0a000 0 0 3 &mpic 2 1
227 0a000 0 0 4 &mpic 3 1
229 /* IDSEL 0x15 (Slot 3) */
230 0a800 0 0 1 &mpic 1 1
231 0a800 0 0 2 &mpic 2 1
232 0a800 0 0 3 &mpic 3 1
233 0a800 0 0 4 &mpic 0 1
235 /* IDSEL 0x16 (Slot 4) */
236 0b000 0 0 1 &mpic 2 1
237 0b000 0 0 2 &mpic 3 1
238 0b000 0 0 3 &mpic 0 1
239 0b000 0 0 4 &mpic 1 1
241 /* IDSEL 0x18 (Slot 5) */
242 0c000 0 0 1 &mpic 0 1
243 0c000 0 0 2 &mpic 1 1
244 0c000 0 0 3 &mpic 2 1
245 0c000 0 0 4 &mpic 3 1
247 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
248 0E000 0 0 1 &mpic 0 1
249 0E000 0 0 2 &mpic 1 1
250 0E000 0 0 3 &mpic 2 1
251 0E000 0 0 4 &mpic 3 1>;
253 interrupt-parent = <&mpic>;
256 ranges = <02000000 0 80000000 80000000 0 10000000
257 01000000 0 00000000 e2000000 0 00800000>;
258 clock-frequency = <3f940aa>;
259 #interrupt-cells = <1>;
261 #address-cells = <3>;
263 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
267 interrupt-map-mask = <f800 0 0 7>;
270 /* IDSEL 0x00 (PrPMC Site) */
276 /* IDSEL 0x04 (VIA chip) */
282 /* IDSEL 0x05 (8139) */
285 /* IDSEL 0x06 (Slot 6) */
291 /* IDESL 0x07 (Slot 7) */
295 3800 0 0 4 &mpic 2 1>;
297 reg = <e000 0 0 0 0>;
298 #interrupt-cells = <1>;
300 #address-cells = <3>;
301 ranges = <02000000 0 80000000
307 clock-frequency = <1fca055>;
311 #interrupt-cells = <2>;
313 #address-cells = <2>;
314 reg = <2000 0 0 0 0>;
315 ranges = <1 0 01000000 0 0 00001000>;
316 interrupt-parent = <&i8259>;
318 i8259: interrupt-controller@20 {
319 interrupt-controller;
320 device_type = "interrupt-controller";
324 #address-cells = <0>;
325 #interrupt-cells = <2>;
326 compatible = "chrp,iic";
328 interrupt-parent = <&mpic>;
332 compatible = "pnpPNP,b00";
340 interrupt-map-mask = <f800 0 0 7>;
347 a800 0 0 4 &mpic 3 1>;
349 interrupt-parent = <&mpic>;
352 ranges = <02000000 0 90000000 90000000 0 10000000
353 01000000 0 00000000 e2800000 0 00800000>;
354 clock-frequency = <3f940aa>;
355 #interrupt-cells = <1>;
357 #address-cells = <3>;
359 compatible = "fsl,mpc8540-pci";
364 interrupt-map-mask = <f800 0 0 7>;
367 /* IDSEL 0x0 (PEX) */
368 00000 0 0 1 &mpic 0 1
369 00000 0 0 2 &mpic 1 1
370 00000 0 0 3 &mpic 2 1
371 00000 0 0 4 &mpic 3 1>;
373 interrupt-parent = <&mpic>;
376 ranges = <02000000 0 a0000000 a0000000 0 20000000
377 01000000 0 00000000 e3000000 0 08000000>;
378 clock-frequency = <1fca055>;
379 #interrupt-cells = <1>;
381 #address-cells = <3>;
383 compatible = "fsl,mpc8548-pcie";
388 clock-frequency = <0>;
389 interrupt-controller;
390 #address-cells = <0>;
391 #interrupt-cells = <2>;
393 compatible = "chrp,open-pic";
394 device_type = "open-pic";