2 * arch/ppc64/kernel/head.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
26 #include <linux/config.h>
27 #include <linux/threads.h>
31 #include <asm/systemcfg.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/asm-offsets.h>
35 #include <asm/cputable.h>
36 #include <asm/setup.h>
37 #include <asm/hvcall.h>
38 #include <asm/iSeries/LparMap.h>
40 #ifdef CONFIG_PPC_ISERIES
41 #define DO_SOFT_DISABLE
45 * We layout physical memory as follows:
46 * 0x0000 - 0x00ff : Secondary processor spin code
47 * 0x0100 - 0x2fff : pSeries Interrupt prologs
48 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
49 * 0x6000 - 0x6fff : Initial (CPU0) segment table
50 * 0x7000 - 0x7fff : FWNMI data area
51 * 0x8000 - : Early init and support code
59 * SPRG0 reserved for hypervisor
60 * SPRG1 temp - used to save gpr
61 * SPRG2 temp - used to save gpr
62 * SPRG3 virt addr of paca
66 * Entering into this code we make the following assumptions:
68 * 1. The MMU is off & open firmware is running in real mode.
69 * 2. The kernel is entered at __start
72 * 1. The MMU is on (as it always is for iSeries)
73 * 2. The kernel is entered at system_reset_iSeries
79 #ifdef CONFIG_PPC_MULTIPLATFORM
81 /* NOP this out unconditionally */
83 b .__start_initialization_multiplatform
85 #endif /* CONFIG_PPC_MULTIPLATFORM */
87 /* Catch branch to 0 in real mode */
90 #ifdef CONFIG_PPC_ISERIES
92 * At offset 0x20, there is a pointer to iSeries LPAR data.
93 * This is required by the hypervisor
96 .llong hvReleaseData-KERNELBASE
99 * At offset 0x28 and 0x30 are offsets to the mschunks_map
100 * array (used by the iSeries LPAR debugger to do translation
101 * between physical addresses and absolute addresses) and
102 * to the pidhash table (also used by the debugger)
104 .llong mschunks_map-KERNELBASE
105 .llong 0 /* pidhash-KERNELBASE SFRXXX */
107 /* Offset 0x38 - Pointer to start of embedded System.map */
108 .globl embedded_sysmap_start
109 embedded_sysmap_start:
111 /* Offset 0x40 - Pointer to end of embedded System.map */
112 .globl embedded_sysmap_end
116 #endif /* CONFIG_PPC_ISERIES */
118 /* Secondary processors spin on this value until it goes to 1. */
119 .globl __secondary_hold_spinloop
120 __secondary_hold_spinloop:
123 /* Secondary processors write this value with their cpu # */
124 /* after they enter the spin loop immediately below. */
125 .globl __secondary_hold_acknowledge
126 __secondary_hold_acknowledge:
131 * The following code is used on pSeries to hold secondary processors
132 * in a spin loop after they have been freed from OpenFirmware, but
133 * before the bulk of the kernel has been relocated. This code
134 * is relocated to physical address 0x60 before prom_init is run.
135 * All of it must fit below the first exception vector at 0x100.
137 _GLOBAL(__secondary_hold)
140 mtmsrd r24 /* RI on */
142 /* Grab our linux cpu number */
145 /* Tell the master cpu we're here */
146 /* Relocation is off & we are located at an address less */
147 /* than 0x100, so only need to grab low order offset. */
148 std r24,__secondary_hold_acknowledge@l(0)
151 /* All secondary cpus wait here until told to start. */
152 100: ld r4,__secondary_hold_spinloop@l(0)
161 b .pSeries_secondary_smp_init
167 /* This value is used to mark exception frames on the stack. */
170 .tc ID_72656773_68657265[TC],0x7265677368657265
174 * The following macros define the code that appears as
175 * the prologue to each of the exception handlers. They
176 * are split into two parts to allow a single kernel binary
177 * to be used for pSeries and iSeries.
178 * LOL. One day... - paulus
182 * We make as much of the exception code common between native
183 * exception handlers (including pSeries LPAR) and iSeries LPAR
184 * implementations as possible.
188 * This is the start of the interrupt handlers for pSeries
189 * This code runs with relocation off.
197 #define EX_R3 40 /* SLB miss saves R3, but not SRR0 */
199 #define EX_LR 48 /* SLB miss saves LR, but not DAR */
203 #define EXCEPTION_PROLOG_PSERIES(area, label) \
204 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
205 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
206 std r10,area+EX_R10(r13); \
207 std r11,area+EX_R11(r13); \
208 std r12,area+EX_R12(r13); \
209 mfspr r9,SPRN_SPRG1; \
210 std r9,area+EX_R13(r13); \
212 clrrdi r12,r13,32; /* get high part of &label */ \
214 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
215 ori r12,r12,(label)@l; /* virt addr of handler */ \
216 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
217 mtspr SPRN_SRR0,r12; \
218 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
219 mtspr SPRN_SRR1,r10; \
221 b . /* prevent speculative execution */
224 * This is the start of the interrupt handlers for iSeries
225 * This code runs with relocation on.
227 #define EXCEPTION_PROLOG_ISERIES_1(area) \
228 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
229 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
230 std r10,area+EX_R10(r13); \
231 std r11,area+EX_R11(r13); \
232 std r12,area+EX_R12(r13); \
233 mfspr r9,SPRN_SPRG1; \
234 std r9,area+EX_R13(r13); \
237 #define EXCEPTION_PROLOG_ISERIES_2 \
239 ld r11,PACALPPACA+LPPACASRR0(r13); \
240 ld r12,PACALPPACA+LPPACASRR1(r13); \
241 ori r10,r10,MSR_RI; \
245 * The common exception prolog is used for all except a few exceptions
246 * such as a segment miss on a kernel address. We have to be prepared
247 * to take another exception from the point where we first touch the
248 * kernel stack onwards.
250 * On entry r13 points to the paca, r9-r13 are saved in the paca,
251 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
252 * SRR1, and relocation is on.
254 #define EXCEPTION_PROLOG_COMMON(n, area) \
255 andi. r10,r12,MSR_PR; /* See if coming from user */ \
256 mr r10,r1; /* Save r1 */ \
257 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
259 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
260 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
261 bge- cr1,bad_stack; /* abort if it is */ \
262 std r9,_CCR(r1); /* save CR in stackframe */ \
263 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
264 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
265 std r10,0(r1); /* make stack chain pointer */ \
266 std r0,GPR0(r1); /* save r0 in stackframe */ \
267 std r10,GPR1(r1); /* save r1 in stackframe */ \
268 std r2,GPR2(r1); /* save r2 in stackframe */ \
269 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
270 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
271 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
272 ld r10,area+EX_R10(r13); \
275 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
276 ld r10,area+EX_R12(r13); \
277 ld r11,area+EX_R13(r13); \
281 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
282 mflr r9; /* save LR in stackframe */ \
284 mfctr r10; /* save CTR in stackframe */ \
286 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
289 std r9,_TRAP(r1); /* set trap number */ \
291 ld r11,exception_marker@toc(r2); \
292 std r10,RESULT(r1); /* clear regs->result */ \
293 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
298 #define STD_EXCEPTION_PSERIES(n, label) \
300 .globl label##_pSeries; \
303 mtspr SPRN_SPRG1,r13; /* save r13 */ \
305 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
307 #define STD_EXCEPTION_ISERIES(n, label, area) \
308 .globl label##_iSeries; \
311 mtspr SPRN_SPRG1,r13; /* save r13 */ \
313 EXCEPTION_PROLOG_ISERIES_1(area); \
314 EXCEPTION_PROLOG_ISERIES_2; \
317 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
318 .globl label##_iSeries; \
321 mtspr SPRN_SPRG1,r13; /* save r13 */ \
323 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
324 lbz r10,PACAPROCENABLED(r13); \
326 beq- label##_iSeries_masked; \
327 EXCEPTION_PROLOG_ISERIES_2; \
330 #ifdef DO_SOFT_DISABLE
331 #define DISABLE_INTS \
332 lbz r10,PACAPROCENABLED(r13); \
336 stb r11,PACAPROCENABLED(r13); \
337 ori r10,r10,MSR_EE; \
340 #define ENABLE_INTS \
341 lbz r10,PACAPROCENABLED(r13); \
344 ori r11,r11,MSR_EE; \
347 #else /* hard enable/disable interrupts */
350 #define ENABLE_INTS \
353 rlwimi r11,r12,0,MSR_EE; \
358 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
360 .globl label##_common; \
362 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
365 addi r3,r1,STACK_FRAME_OVERHEAD; \
369 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
371 .globl label##_common; \
373 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
375 addi r3,r1,STACK_FRAME_OVERHEAD; \
377 b .ret_from_except_lite
380 * Start of pSeries system interrupt routines
383 .globl __start_interrupts
386 STD_EXCEPTION_PSERIES(0x100, system_reset)
389 _machine_check_pSeries:
391 mtspr SPRN_SPRG1,r13 /* save r13 */
393 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
396 .globl data_access_pSeries
405 rlwimi r13,r12,16,0x20
408 beq .do_stab_bolted_pSeries
411 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
412 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
415 .globl data_access_slb_pSeries
416 data_access_slb_pSeries:
420 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
421 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
422 std r10,PACA_EXSLB+EX_R10(r13)
423 std r11,PACA_EXSLB+EX_R11(r13)
424 std r12,PACA_EXSLB+EX_R12(r13)
425 std r3,PACA_EXSLB+EX_R3(r13)
427 std r9,PACA_EXSLB+EX_R13(r13)
429 mfspr r12,SPRN_SRR1 /* and SRR1 */
431 b .do_slb_miss /* Rel. branch works in real mode */
433 STD_EXCEPTION_PSERIES(0x400, instruction_access)
436 .globl instruction_access_slb_pSeries
437 instruction_access_slb_pSeries:
441 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
442 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
443 std r10,PACA_EXSLB+EX_R10(r13)
444 std r11,PACA_EXSLB+EX_R11(r13)
445 std r12,PACA_EXSLB+EX_R12(r13)
446 std r3,PACA_EXSLB+EX_R3(r13)
448 std r9,PACA_EXSLB+EX_R13(r13)
450 mfspr r12,SPRN_SRR1 /* and SRR1 */
451 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
452 b .do_slb_miss /* Rel. branch works in real mode */
454 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
455 STD_EXCEPTION_PSERIES(0x600, alignment)
456 STD_EXCEPTION_PSERIES(0x700, program_check)
457 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
458 STD_EXCEPTION_PSERIES(0x900, decrementer)
459 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
460 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
463 .globl system_call_pSeries
472 oris r12,r12,system_call_common@h
473 ori r12,r12,system_call_common@l
475 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
479 b . /* prevent speculative execution */
481 STD_EXCEPTION_PSERIES(0xd00, single_step)
482 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
484 /* We need to deal with the Altivec unavailable exception
485 * here which is at 0xf20, thus in the middle of the
486 * prolog code of the PerformanceMonitor one. A little
487 * trickery is thus necessary
490 b performance_monitor_pSeries
492 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
494 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
495 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
499 /*** pSeries interrupt support ***/
501 /* moved from 0xf00 */
502 STD_EXCEPTION_PSERIES(., performance_monitor)
505 _GLOBAL(do_stab_bolted_pSeries)
508 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
511 * Vectors for the FWNMI option. Share common code.
513 .globl system_reset_fwnmi
516 mtspr SPRN_SPRG1,r13 /* save r13 */
518 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
520 .globl machine_check_fwnmi
523 mtspr SPRN_SPRG1,r13 /* save r13 */
525 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
527 #ifdef CONFIG_PPC_ISERIES
528 /*** ISeries-LPAR interrupt handlers ***/
530 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
532 .globl data_access_iSeries
540 rlwimi r13,r12,16,0x20
543 beq .do_stab_bolted_iSeries
546 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
547 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
548 EXCEPTION_PROLOG_ISERIES_2
551 .do_stab_bolted_iSeries:
554 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
555 EXCEPTION_PROLOG_ISERIES_2
558 .globl data_access_slb_iSeries
559 data_access_slb_iSeries:
560 mtspr SPRN_SPRG1,r13 /* save r13 */
561 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
562 std r3,PACA_EXSLB+EX_R3(r13)
563 ld r12,PACALPPACA+LPPACASRR1(r13)
567 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
569 .globl instruction_access_slb_iSeries
570 instruction_access_slb_iSeries:
571 mtspr SPRN_SPRG1,r13 /* save r13 */
572 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
573 std r3,PACA_EXSLB+EX_R3(r13)
574 ld r12,PACALPPACA+LPPACASRR1(r13)
575 ld r3,PACALPPACA+LPPACASRR0(r13)
578 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
579 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
580 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
581 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
582 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
583 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
584 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
586 .globl system_call_iSeries
590 EXCEPTION_PROLOG_ISERIES_2
593 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
594 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
595 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
597 .globl system_reset_iSeries
598 system_reset_iSeries:
599 mfspr r13,SPRN_SPRG3 /* Get paca address */
602 mtmsrd r24 /* RI on */
603 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
604 cmpwi 0,r24,0 /* Are we processor 0? */
605 beq .__start_initialization_iSeries /* Start up the first processor */
607 li r5,CTRL_RUNLATCH /* Turn off the run light */
614 lbz r23,PACAPROCSTART(r13) /* Test if this processor
617 LOADADDR(r3,current_set)
618 sldi r28,r24,3 /* get current_set[cpu#] */
620 addi r1,r3,THREAD_SIZE
621 subi r1,r1,STACK_FRAME_OVERHEAD
624 beq iSeries_secondary_smp_loop /* Loop until told to go */
625 bne .__secondary_start /* Loop until told to go */
626 iSeries_secondary_smp_loop:
627 /* Let the Hypervisor know we are alive */
628 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
630 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
631 #else /* CONFIG_SMP */
632 /* Yield the processor. This is required for non-SMP kernels
633 which are running on multi-threaded machines. */
635 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
636 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
637 li r4,0 /* "yield timed" */
638 li r5,-1 /* "yield forever" */
639 #endif /* CONFIG_SMP */
640 li r0,-1 /* r0=-1 indicates a Hypervisor call */
641 sc /* Invoke the hypervisor via a system call */
642 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
643 b 1b /* If SMP not configured, secondaries
646 .globl decrementer_iSeries_masked
647 decrementer_iSeries_masked:
649 stb r11,PACALPPACA+LPPACADECRINT(r13)
650 lwz r12,PACADEFAULTDECR(r13)
654 .globl hardware_interrupt_iSeries_masked
655 hardware_interrupt_iSeries_masked:
656 mtcrf 0x80,r9 /* Restore regs */
657 ld r11,PACALPPACA+LPPACASRR0(r13)
658 ld r12,PACALPPACA+LPPACASRR1(r13)
661 ld r9,PACA_EXGEN+EX_R9(r13)
662 ld r10,PACA_EXGEN+EX_R10(r13)
663 ld r11,PACA_EXGEN+EX_R11(r13)
664 ld r12,PACA_EXGEN+EX_R12(r13)
665 ld r13,PACA_EXGEN+EX_R13(r13)
667 b . /* prevent speculative execution */
668 #endif /* CONFIG_PPC_ISERIES */
670 /*** Common interrupt handlers ***/
672 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
675 * Machine check is different because we use a different
676 * save area: PACA_EXMC instead of PACA_EXGEN.
679 .globl machine_check_common
680 machine_check_common:
681 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
684 addi r3,r1,STACK_FRAME_OVERHEAD
685 bl .machine_check_exception
688 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
689 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
690 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
691 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
692 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
693 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
694 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
695 #ifdef CONFIG_ALTIVEC
696 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
698 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
702 * Here we have detected that the kernel stack pointer is bad.
703 * R9 contains the saved CR, r13 points to the paca,
704 * r10 contains the (bad) kernel stack pointer,
705 * r11 and r12 contain the saved SRR0 and SRR1.
706 * We switch to using an emergency stack, save the registers there,
707 * and call kernel_bad_stack(), which panics.
710 ld r1,PACAEMERGSP(r13)
711 subi r1,r1,64+INT_FRAME_SIZE
732 addi r11,r1,INT_FRAME_SIZE
737 1: addi r3,r1,STACK_FRAME_OVERHEAD
742 * Return from an exception with minimal checks.
743 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
744 * If interrupts have been enabled, or anything has been
745 * done that might have changed the scheduling status of
746 * any task or sent any task a signal, you should use
747 * ret_from_except or ret_from_except_lite instead of this.
749 .globl fast_exception_return
750 fast_exception_return:
753 andi. r3,r12,MSR_RI /* check if RI is set */
767 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
775 b . /* prevent speculative execution */
779 1: addi r3,r1,STACK_FRAME_OVERHEAD
780 bl .unrecoverable_exception
784 * Here r13 points to the paca, r9 contains the saved CR,
785 * SRR0 and SRR1 are saved in r11 and r12,
786 * r9 - r13 are saved in paca->exgen.
789 .globl data_access_common
791 RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */
793 std r10,PACA_EXGEN+EX_DAR(r13)
795 stw r10,PACA_EXGEN+EX_DSISR(r13)
796 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
797 ld r3,PACA_EXGEN+EX_DAR(r13)
798 lwz r4,PACA_EXGEN+EX_DSISR(r13)
800 b .do_hash_page /* Try to handle as hpte fault */
803 .globl instruction_access_common
804 instruction_access_common:
805 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
809 b .do_hash_page /* Try to handle as hpte fault */
812 .globl hardware_interrupt_common
813 .globl hardware_interrupt_entry
814 hardware_interrupt_common:
815 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
816 hardware_interrupt_entry:
818 addi r3,r1,STACK_FRAME_OVERHEAD
820 b .ret_from_except_lite
823 .globl alignment_common
826 std r10,PACA_EXGEN+EX_DAR(r13)
828 stw r10,PACA_EXGEN+EX_DSISR(r13)
829 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
830 ld r3,PACA_EXGEN+EX_DAR(r13)
831 lwz r4,PACA_EXGEN+EX_DSISR(r13)
835 addi r3,r1,STACK_FRAME_OVERHEAD
837 bl .alignment_exception
841 .globl program_check_common
842 program_check_common:
843 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
845 addi r3,r1,STACK_FRAME_OVERHEAD
847 bl .program_check_exception
851 .globl fp_unavailable_common
852 fp_unavailable_common:
853 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
854 bne .load_up_fpu /* if from user, just load it up */
856 addi r3,r1,STACK_FRAME_OVERHEAD
858 bl .kernel_fp_unavailable_exception
862 .globl altivec_unavailable_common
863 altivec_unavailable_common:
864 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
865 #ifdef CONFIG_ALTIVEC
867 bne .load_up_altivec /* if from user, just load it up */
868 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
871 addi r3,r1,STACK_FRAME_OVERHEAD
873 bl .altivec_unavailable_exception
876 #ifdef CONFIG_ALTIVEC
878 * load_up_altivec(unused, unused, tsk)
879 * Disable VMX for the task which had it previously,
880 * and save its vector registers in its thread_struct.
881 * Enables the VMX for use in the kernel on return.
882 * On SMP we know the VMX is free, since we give it up every
883 * switch (ie, no lazy save of the vector registers).
884 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
886 _STATIC(load_up_altivec)
887 mfmsr r5 /* grab the current MSR */
889 mtmsrd r5 /* enable use of VMX now */
893 * For SMP, we don't do lazy VMX switching because it just gets too
894 * horrendously complex, especially when a task switches from one CPU
895 * to another. Instead we call giveup_altvec in switch_to.
896 * VRSAVE isn't dealt with here, that is done in the normal context
897 * switch code. Note that we could rely on vrsave value to eventually
898 * avoid saving all of the VREGs here...
901 ld r3,last_task_used_altivec@got(r2)
905 /* Save VMX state to last_task_used_altivec's THREAD struct */
911 /* Disable VMX for last_task_used_altivec */
913 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
916 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
918 #endif /* CONFIG_SMP */
919 /* Hack: if we get an altivec unavailable trap with VRSAVE
920 * set to all zeros, we assume this is a broken application
921 * that fails to set it properly, and thus we switch it to
930 /* enable use of VMX after return */
931 ld r4,PACACURRENT(r13)
932 addi r5,r4,THREAD /* Get THREAD */
933 oris r12,r12,MSR_VEC@h
937 stw r4,THREAD_USED_VR(r5)
942 /* Update last_task_used_math to 'current' */
943 subi r4,r5,THREAD /* Back to 'current' */
945 #endif /* CONFIG_SMP */
946 /* restore registers and return */
947 b fast_exception_return
948 #endif /* CONFIG_ALTIVEC */
954 _GLOBAL(do_hash_page)
958 andis. r0,r4,0xa450 /* weird error? */
959 bne- .handle_page_fault /* if not, try to insert a HPTE */
961 andis. r0,r4,0x0020 /* Is it a segment table fault? */
962 bne- .do_ste_alloc /* If so handle it */
963 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
966 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
967 * accessing a userspace segment (even from the kernel). We assume
968 * kernel addresses always have the high bit set.
970 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
971 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
972 orc r0,r12,r0 /* MSR_PR | ~high_bit */
973 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
974 ori r4,r4,1 /* add _PAGE_PRESENT */
975 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
978 * On iSeries, we soft-disable interrupts here, then
979 * hard-enable interrupts so that the hash_page code can spin on
980 * the hash_table_lock without problems on a shared processor.
985 * r3 contains the faulting address
986 * r4 contains the required access permissions
987 * r5 contains the trap number
989 * at return r3 = 0 for success
991 bl .hash_page /* build HPTE if possible */
992 cmpdi r3,0 /* see if hash_page succeeded */
994 #ifdef DO_SOFT_DISABLE
996 * If we had interrupts soft-enabled at the point where the
997 * DSI/ISI occurred, and an interrupt came in during hash_page,
999 * We jump to ret_from_except_lite rather than fast_exception_return
1000 * because ret_from_except_lite will check for and handle pending
1001 * interrupts if necessary.
1003 beq .ret_from_except_lite
1004 /* For a hash failure, we don't bother re-enabling interrupts */
1008 * hash_page couldn't handle it, set soft interrupt enable back
1009 * to what it was before the trap. Note that .local_irq_restore
1010 * handles any interrupts pending at this point.
1013 bl .local_irq_restore
1016 beq fast_exception_return /* Return from exception on success */
1017 ble- 12f /* Failure return from hash_page */
1022 /* Here we have a page fault that hash_page can't handle. */
1023 _GLOBAL(handle_page_fault)
1027 addi r3,r1,STACK_FRAME_OVERHEAD
1030 beq+ .ret_from_except_lite
1033 addi r3,r1,STACK_FRAME_OVERHEAD
1038 /* We have a page fault that hash_page could handle but HV refused
1042 addi r3,r1,STACK_FRAME_OVERHEAD
1047 /* here we have a segment miss */
1048 _GLOBAL(do_ste_alloc)
1049 bl .ste_allocate /* try to insert stab entry */
1051 beq+ fast_exception_return
1052 b .handle_page_fault
1055 * r13 points to the PACA, r9 contains the saved CR,
1056 * r11 and r12 contain the saved SRR0 and SRR1.
1057 * r9 - r13 are saved in paca->exslb.
1058 * We assume we aren't going to take any exceptions during this procedure.
1059 * We assume (DAR >> 60) == 0xc.
1062 _GLOBAL(do_stab_bolted)
1063 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1064 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1066 /* Hash to the primary group */
1067 ld r10,PACASTABVIRT(r13)
1070 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1072 /* Calculate VSID */
1073 /* This is a kernel address, so protovsid = ESID */
1074 ASM_VSID_SCRAMBLE(r11, r9)
1075 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1077 /* Search the primary group for a free entry */
1078 1: ld r11,0(r10) /* Test valid bit of the current ste */
1085 /* Stick for only searching the primary group for now. */
1086 /* At least for now, we use a very simple random castout scheme */
1087 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1089 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1092 /* r10 currently points to an ste one past the group of interest */
1093 /* make it point to the randomly selected entry */
1095 or r10,r10,r11 /* r10 is the entry to invalidate */
1097 isync /* mark the entry invalid */
1099 rldicl r11,r11,56,1 /* clear the valid bit */
1104 clrrdi r11,r11,28 /* Get the esid part of the ste */
1107 2: std r9,8(r10) /* Store the vsid part of the ste */
1110 mfspr r11,SPRN_DAR /* Get the new esid */
1111 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1112 ori r11,r11,0x90 /* Turn on valid and kp */
1113 std r11,0(r10) /* Put new entry back into the stab */
1117 /* All done -- return from exception. */
1118 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1119 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1121 andi. r10,r12,MSR_RI
1124 mtcrf 0x80,r9 /* restore CR */
1132 ld r9,PACA_EXSLB+EX_R9(r13)
1133 ld r10,PACA_EXSLB+EX_R10(r13)
1134 ld r11,PACA_EXSLB+EX_R11(r13)
1135 ld r12,PACA_EXSLB+EX_R12(r13)
1136 ld r13,PACA_EXSLB+EX_R13(r13)
1138 b . /* prevent speculative execution */
1141 * r13 points to the PACA, r9 contains the saved CR,
1142 * r11 and r12 contain the saved SRR0 and SRR1.
1143 * r3 has the faulting address
1144 * r9 - r13 are saved in paca->exslb.
1145 * r3 is saved in paca->slb_r3
1146 * We assume we aren't going to take any exceptions during this procedure.
1148 _GLOBAL(do_slb_miss)
1151 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1152 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1154 bl .slb_allocate /* handle it */
1156 /* All done -- return from exception. */
1158 ld r10,PACA_EXSLB+EX_LR(r13)
1159 ld r3,PACA_EXSLB+EX_R3(r13)
1160 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1161 #ifdef CONFIG_PPC_ISERIES
1162 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
1163 #endif /* CONFIG_PPC_ISERIES */
1167 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1173 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1176 #ifdef CONFIG_PPC_ISERIES
1179 #endif /* CONFIG_PPC_ISERIES */
1180 ld r9,PACA_EXSLB+EX_R9(r13)
1181 ld r10,PACA_EXSLB+EX_R10(r13)
1182 ld r11,PACA_EXSLB+EX_R11(r13)
1183 ld r12,PACA_EXSLB+EX_R12(r13)
1184 ld r13,PACA_EXSLB+EX_R13(r13)
1186 b . /* prevent speculative execution */
1189 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1192 1: addi r3,r1,STACK_FRAME_OVERHEAD
1193 bl .unrecoverable_exception
1197 * Space for CPU0's segment table.
1199 * On iSeries, the hypervisor must fill in at least one entry before
1200 * we get control (with relocate on). The address is give to the hv
1201 * as a page number (see xLparMap in lpardata.c), so this must be at a
1202 * fixed address (the linker can't compute (u64)&initial_stab >>
1205 . = STAB0_PHYS_ADDR /* 0x6000 */
1211 * Data area reserved for FWNMI option.
1212 * This address (0x7000) is fixed by the RPA.
1215 .globl fwnmi_data_area
1218 /* iSeries does not use the FWNMI stuff, so it is safe to put
1219 * this here, even if we later allow kernels that will boot on
1220 * both pSeries and iSeries */
1221 #ifdef CONFIG_PPC_ISERIES
1223 #include "lparmap.s"
1225 * This ".text" is here for old compilers that generate a trailing
1226 * .note section when compiling .c files to .s
1229 #endif /* CONFIG_PPC_ISERIES */
1234 * On pSeries, secondary processors spin in the following code.
1235 * At entry, r3 = this processor's number (physical cpu id)
1237 _GLOBAL(pSeries_secondary_smp_init)
1240 /* turn on 64-bit mode */
1244 /* Copy some CPU settings from CPU 0 */
1245 bl .__restore_cpu_setup
1247 /* Set up a paca value for this processor. Since we have the
1248 * physical cpu id in r24, we need to search the pacas to find
1249 * which logical id maps to our physical one.
1251 LOADADDR(r13, paca) /* Get base vaddr of paca array */
1252 li r5,0 /* logical cpu id */
1253 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1254 cmpw r6,r24 /* Compare to our id */
1256 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1261 mr r3,r24 /* not found, copy phys to r3 */
1262 b .kexec_wait /* next kernel might do better */
1264 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1265 /* From now on, r24 is expected to be logical cpuid */
1268 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1272 /* Create a temp kernel stack for use before relocation is on. */
1273 ld r1,PACAEMERGSP(r13)
1274 subi r1,r1,STACK_FRAME_OVERHEAD
1278 bne .__secondary_start
1280 b 3b /* Loop until told to go */
1282 #ifdef CONFIG_PPC_ISERIES
1283 _STATIC(__start_initialization_iSeries)
1284 /* Clear out the BSS */
1285 LOADADDR(r11,__bss_stop)
1286 LOADADDR(r8,__bss_start)
1287 sub r11,r11,r8 /* bss size */
1288 addi r11,r11,7 /* round up to an even double word */
1289 rldicl. r11,r11,61,3 /* shift right by 3 */
1293 mtctr r11 /* zero this many doublewords */
1297 LOADADDR(r1,init_thread_union)
1298 addi r1,r1,THREAD_SIZE
1300 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1302 LOADADDR(r3,cpu_specs)
1303 LOADADDR(r4,cur_cpu_spec)
1307 LOADADDR(r2,__toc_start)
1311 bl .iSeries_early_setup
1314 /* relocation is on at this point */
1316 b .start_here_common
1317 #endif /* CONFIG_PPC_ISERIES */
1319 #ifdef CONFIG_PPC_MULTIPLATFORM
1323 andi. r0,r3,MSR_IR|MSR_DR
1330 b . /* prevent speculative execution */
1334 * Here is our main kernel entry point. We support currently 2 kind of entries
1335 * depending on the value of r5.
1337 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1340 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1341 * DT block, r4 is a physical pointer to the kernel itself
1344 _GLOBAL(__start_initialization_multiplatform)
1346 * Are we booted from a PROM Of-type client-interface ?
1349 bne .__boot_from_prom /* yes -> prom */
1351 /* Save parameters */
1355 /* Make sure we are running in 64 bits mode */
1358 /* Setup some critical 970 SPRs before switching MMU off */
1359 bl .__970_cpu_preinit
1364 /* Switch off MMU if not already */
1365 LOADADDR(r4, .__after_prom_start - KERNELBASE)
1368 b .__after_prom_start
1370 _STATIC(__boot_from_prom)
1371 /* Save parameters */
1378 /* Make sure we are running in 64 bits mode */
1381 /* put a relocation offset into r3 */
1384 LOADADDR(r2,__toc_start)
1388 /* Relocate the TOC from a virt addr to a real addr */
1391 /* Restore parameters */
1398 /* Do all of the interaction with OF client interface */
1400 /* We never return */
1404 * At this point, r3 contains the physical address we are running at,
1405 * returned by prom_init()
1407 _STATIC(__after_prom_start)
1410 * We need to run with __start at physical address 0.
1411 * This will leave some code in the first 256B of
1412 * real memory, which are reserved for software use.
1413 * The remainder of the first page is loaded with the fixed
1414 * interrupt vectors. The next two pages are filled with
1415 * unknown exception placeholders.
1417 * Note: This process overwrites the OF exception vectors.
1418 * r26 == relocation offset
1423 SET_REG_TO_CONST(r27,KERNELBASE)
1425 li r3,0 /* target addr */
1427 // XXX FIXME: Use phys returned by OF (r30)
1428 add r4,r27,r26 /* source addr */
1429 /* current address of _start */
1430 /* i.e. where we are running */
1431 /* the source addr */
1433 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
1436 li r6,0x100 /* Start offset, the first 0x100 */
1437 /* bytes were copied earlier. */
1439 bl .copy_and_flush /* copy the first n bytes */
1440 /* this includes the code being */
1441 /* executed here. */
1443 LOADADDR(r0, 4f) /* Jump to the copy of this code */
1444 mtctr r0 /* that we just made/relocated */
1447 4: LOADADDR(r5,klimit)
1449 ld r5,0(r5) /* get the value of klimit */
1451 bl .copy_and_flush /* copy the rest */
1452 b .start_here_multiplatform
1454 #endif /* CONFIG_PPC_MULTIPLATFORM */
1457 * Copy routine used to copy the kernel to start at physical address 0
1458 * and flush and invalidate the caches as needed.
1459 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1460 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1462 * Note: this routine *only* clobbers r0, r6 and lr
1464 _GLOBAL(copy_and_flush)
1467 4: li r0,16 /* Use the least common */
1468 /* denominator cache line */
1469 /* size. This results in */
1470 /* extra cache line flushes */
1471 /* but operation is correct. */
1472 /* Can't get cache line size */
1473 /* from NACA as it is being */
1476 mtctr r0 /* put # words/line in ctr */
1477 3: addi r6,r6,8 /* copy a cache line */
1481 dcbst r6,r3 /* write it to memory */
1483 icbi r6,r3 /* flush the icache line */
1495 #ifdef CONFIG_PPC_PMAC
1497 * On PowerMac, secondary processors starts from the reset vector, which
1498 * is temporarily turned into a call to one of the functions below.
1503 .globl pmac_secondary_start_1
1504 pmac_secondary_start_1:
1506 b .pmac_secondary_start
1508 .globl pmac_secondary_start_2
1509 pmac_secondary_start_2:
1511 b .pmac_secondary_start
1513 .globl pmac_secondary_start_3
1514 pmac_secondary_start_3:
1516 b .pmac_secondary_start
1518 _GLOBAL(pmac_secondary_start)
1519 /* turn on 64-bit mode */
1523 /* Copy some CPU settings from CPU 0 */
1524 bl .__restore_cpu_setup
1526 /* pSeries do that early though I don't think we really need it */
1529 mtmsrd r3 /* RI on */
1531 /* Set up a paca value for this processor. */
1532 LOADADDR(r4, paca) /* Get base vaddr of paca array */
1533 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1534 add r13,r13,r4 /* for this processor. */
1535 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1537 /* Create a temp kernel stack for use before relocation is on. */
1538 ld r1,PACAEMERGSP(r13)
1539 subi r1,r1,STACK_FRAME_OVERHEAD
1541 b .__secondary_start
1543 #endif /* CONFIG_PPC_PMAC */
1546 * This function is called after the master CPU has released the
1547 * secondary processors. The execution environment is relocation off.
1548 * The paca for this processor has the following fields initialized at
1550 * 1. Processor number
1551 * 2. Segment table pointer (virtual address)
1552 * On entry the following are set:
1553 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1554 * r24 = cpu# (in Linux terms)
1555 * r13 = paca virtual address
1556 * SPRG3 = paca virtual address
1558 _GLOBAL(__secondary_start)
1560 HMT_MEDIUM /* Set thread priority to MEDIUM */
1564 stb r6,PACAPROCENABLED(r13)
1566 #ifndef CONFIG_PPC_ISERIES
1567 /* Initialize the page table pointer register. */
1569 ld r6,0(r6) /* get the value of _SDR1 */
1570 mtspr SPRN_SDR1,r6 /* set the htab location */
1572 /* Initialize the first segment table (or SLB) entry */
1573 ld r3,PACASTABVIRT(r13) /* get addr of segment table */
1576 /* Initialize the kernel stack. Just a repeat for iSeries. */
1577 LOADADDR(r3,current_set)
1578 sldi r28,r24,3 /* get current_set[cpu#] */
1580 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1581 std r1,PACAKSAVE(r13)
1583 ld r3,PACASTABREAL(r13) /* get raddr of segment table */
1584 ori r4,r3,1 /* turn on valid bit */
1586 #ifdef CONFIG_PPC_ISERIES
1587 li r0,-1 /* hypervisor call */
1589 sldi r3,r3,63 /* 0x8000000000000000 */
1590 ori r3,r3,4 /* 0x8000000000000004 */
1591 sc /* HvCall_setASR */
1594 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1596 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1597 andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
1598 beq 98f /* branch if result is 0 */
1601 cmpwi r3,0x37 /* SStar */
1603 cmpwi r3,0x36 /* IStar */
1605 cmpwi r3,0x34 /* Pulsar */
1607 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1608 HVSC /* Invoking hcall */
1610 98: /* !(rpa hypervisor) || !(star) */
1611 mtasr r4 /* set the stab location */
1617 /* enable MMU and jump to start_secondary */
1618 LOADADDR(r3,.start_secondary_prolog)
1619 SET_REG_TO_CONST(r4, MSR_KERNEL)
1620 #ifdef DO_SOFT_DISABLE
1626 b . /* prevent speculative execution */
1629 * Running with relocation on at this point. All we want to do is
1630 * zero the stack back-chain pointer before going into C code.
1632 _GLOBAL(start_secondary_prolog)
1634 std r3,0(r1) /* Zero the stack frame pointer */
1639 * This subroutine clobbers r11 and r12
1641 _GLOBAL(enable_64b_mode)
1642 mfmsr r11 /* grab the current MSR */
1644 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1647 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1653 #ifdef CONFIG_PPC_MULTIPLATFORM
1655 * This is where the main kernel code starts.
1657 _STATIC(start_here_multiplatform)
1658 /* get a new offset, now that the kernel has moved. */
1662 /* Clear out the BSS. It may have been done in prom_init,
1663 * already but that's irrelevant since prom_init will soon
1664 * be detached from the kernel completely. Besides, we need
1665 * to clear it now for kexec-style entry.
1667 LOADADDR(r11,__bss_stop)
1668 LOADADDR(r8,__bss_start)
1669 sub r11,r11,r8 /* bss size */
1670 addi r11,r11,7 /* round up to an even double word */
1671 rldicl. r11,r11,61,3 /* shift right by 3 */
1675 mtctr r11 /* zero this many doublewords */
1682 mtmsrd r6 /* RI on */
1685 /* Start up the second thread on cpu 0 */
1688 cmpwi r3,0x34 /* Pulsar */
1690 cmpwi r3,0x36 /* Icestar */
1692 cmpwi r3,0x37 /* SStar */
1694 b 91f /* HMT not supported */
1696 bl .hmt_start_secondary
1700 /* The following gets the stack and TOC set up with the regs */
1701 /* pointing to the real addr of the kernel stack. This is */
1702 /* all done to support the C function call below which sets */
1703 /* up the htab. This is done because we have relocated the */
1704 /* kernel but are still running in real mode. */
1706 LOADADDR(r3,init_thread_union)
1709 /* set up a stack pointer (physical address) */
1710 addi r1,r3,THREAD_SIZE
1712 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1714 /* set up the TOC (physical address) */
1715 LOADADDR(r2,__toc_start)
1720 LOADADDR(r3,cpu_specs)
1722 LOADADDR(r4,cur_cpu_spec)
1727 /* Save some low level config HIDs of CPU0 to be copied to
1728 * other CPUs later on, or used for suspend/resume
1730 bl .__save_cpu_setup
1733 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1734 * note that boot_cpuid can always be 0 nowadays since there is
1735 * nowhere it can be initialized differently before we reach this
1738 LOADADDR(r27, boot_cpuid)
1742 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1743 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1744 add r13,r13,r24 /* for this processor. */
1745 add r13,r13,r26 /* convert to physical addr */
1746 mtspr SPRN_SPRG3,r13 /* PPPBBB: Temp... -Peter */
1748 /* Do very early kernel initializations, including initial hash table,
1749 * stab and slb setup before we turn on relocation. */
1751 /* Restore parameters passed from prom_init/kexec */
1756 ld r3,PACASTABREAL(r13)
1757 ori r4,r3,1 /* turn on valid bit */
1758 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1760 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1761 andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
1762 beq 98f /* branch if result is 0 */
1765 cmpwi r3,0x37 /* SStar */
1767 cmpwi r3,0x36 /* IStar */
1769 cmpwi r3,0x34 /* Pulsar */
1771 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1772 HVSC /* Invoking hcall */
1774 98: /* !(rpa hypervisor) || !(star) */
1775 mtasr r4 /* set the stab location */
1777 /* Set SDR1 (hash table pointer) */
1778 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1780 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1781 /* Test if bit 0 is set (LPAR bit) */
1782 andi. r3,r3,PLATFORM_LPAR
1783 bne 98f /* branch if result is !0 */
1784 LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
1786 ld r6,0(r6) /* get the value of _SDR1 */
1787 mtspr SPRN_SDR1,r6 /* set the htab location */
1789 LOADADDR(r3,.start_here_common)
1790 SET_REG_TO_CONST(r4, MSR_KERNEL)
1794 b . /* prevent speculative execution */
1795 #endif /* CONFIG_PPC_MULTIPLATFORM */
1797 /* This is where all platforms converge execution */
1798 _STATIC(start_here_common)
1799 /* relocation is on at this point */
1801 /* The following code sets up the SP and TOC now that we are */
1802 /* running with translation enabled. */
1804 LOADADDR(r3,init_thread_union)
1806 /* set up the stack */
1807 addi r1,r3,THREAD_SIZE
1809 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1811 /* Apply the CPUs-specific fixups (nop out sections not relevant
1815 bl .do_cpu_ftr_fixups
1817 LOADADDR(r26, boot_cpuid)
1820 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1821 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1822 add r13,r13,r24 /* for this processor. */
1823 mtspr SPRN_SPRG3,r13
1825 /* ptr to current */
1826 LOADADDR(r4,init_task)
1827 std r4,PACACURRENT(r13)
1831 std r1,PACAKSAVE(r13)
1835 /* Load up the kernel context */
1837 #ifdef DO_SOFT_DISABLE
1839 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1841 ori r5,r5,MSR_EE /* Hard Enabled */
1849 LOADADDR(r5, hmt_thread_data)
1852 cmpwi r7,0x34 /* Pulsar */
1854 cmpwi r7,0x36 /* Icestar */
1856 cmpwi r7,0x37 /* SStar */
1859 90: mfspr r6,SPRN_PIR
1862 91: mfspr r6,SPRN_PIR
1866 bl .hmt_start_secondary
1869 __hmt_secondary_hold:
1870 LOADADDR(r5, hmt_thread_data)
1880 93: andi. r6,r6,0x3f
1894 b .pSeries_secondary_smp_init
1897 _GLOBAL(hmt_start_secondary)
1898 LOADADDR(r4,__hmt_secondary_hold)
1900 mtspr SPRN_NIADORM, r4
1901 mfspr r4, SPRN_MSRDORM
1904 mtspr SPRN_MSRDORM, r4
1913 mfspr r4, SPRN_CTRLF
1915 mtspr SPRN_CTRLT, r4
1919 #if defined(CONFIG_KEXEC) || defined(CONFIG_SMP)
1920 _GLOBAL(smp_release_cpus)
1921 /* All secondary cpus are spinning on a common
1922 * spinloop, release them all now so they can start
1923 * to spin on their individual paca spinloops.
1924 * For non SMP kernels, the secondary cpus never
1925 * get out of the common spinloop.
1926 * XXX This does nothing useful on iSeries, secondaries are
1927 * already waiting on their paca.
1930 LOADADDR(r5,__secondary_hold_spinloop)
1934 #endif /* CONFIG_SMP */
1938 * We put a few things here that have to be page-aligned.
1939 * This stuff goes at the beginning of the bss, which is page-aligned.
1945 .globl empty_zero_page
1949 .globl swapper_pg_dir
1954 * This space gets a copy of optional info passed to us by the bootstrap
1955 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1959 .space COMMAND_LINE_SIZE