2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
27 #include <linux/list.h>
28 #include <linux/syscalls.h>
29 #include <linux/irq.h>
30 #include <linux/vmalloc.h>
32 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
37 #include <asm/machdep.h>
38 #include <asm/ppc-pci.h>
39 #include <asm/firmware.h>
42 static DEFINE_SPINLOCK(hose_spinlock);
44 /* XXX kill that some day ... */
45 static int global_phb_number; /* Global phb counter */
47 /* ISA Memory physical address */
48 resource_size_t isa_mem_base;
50 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
51 unsigned int ppc_pci_flags = 0;
54 static struct dma_mapping_ops *pci_dma_ops;
56 void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_mapping_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
69 return dma_set_mask(&dev->dev, mask);
72 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
76 rc = dma_set_mask(&dev->dev, mask);
77 dev->dev.coherent_dma_mask = dev->dma_mask;
82 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
84 struct pci_controller *phb;
86 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
89 spin_lock(&hose_spinlock);
90 phb->global_number = global_phb_number++;
91 list_add_tail(&phb->list_node, &hose_list);
92 spin_unlock(&hose_spinlock);
94 phb->is_dynamic = mem_init_done;
97 int nid = of_node_to_nid(dev);
99 if (nid < 0 || !node_online(nid))
102 PHB_SET_NODE(phb, nid);
108 void pcibios_free_controller(struct pci_controller *phb)
110 spin_lock(&hose_spinlock);
111 list_del(&phb->list_node);
112 spin_unlock(&hose_spinlock);
118 int pcibios_vaddr_is_ioport(void __iomem *address)
121 struct pci_controller *hose;
124 spin_lock(&hose_spinlock);
125 list_for_each_entry(hose, &hose_list, list_node) {
127 size = hose->pci_io_size;
129 size = hose->io_resource.end - hose->io_resource.start + 1;
131 if (address >= hose->io_base_virt &&
132 address < (hose->io_base_virt + size)) {
137 spin_unlock(&hose_spinlock);
142 * Return the domain number for this bus.
144 int pci_domain_nr(struct pci_bus *bus)
146 struct pci_controller *hose = pci_bus_to_host(bus);
148 return hose->global_number;
150 EXPORT_SYMBOL(pci_domain_nr);
154 /* This routine is meant to be used early during boot, when the
155 * PCI bus numbers have not yet been assigned, and you need to
156 * issue PCI config cycles to an OF device.
157 * It could also be used to "fix" RTAS config cycles if you want
158 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
161 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
166 struct pci_controller *hose, *tmp;
167 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
168 if (hose->dn == node)
175 static ssize_t pci_show_devspec(struct device *dev,
176 struct device_attribute *attr, char *buf)
178 struct pci_dev *pdev;
179 struct device_node *np;
181 pdev = to_pci_dev (dev);
182 np = pci_device_to_OF_node(pdev);
183 if (np == NULL || np->full_name == NULL)
185 return sprintf(buf, "%s", np->full_name);
187 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
188 #endif /* CONFIG_PPC_OF */
190 /* Add sysfs properties */
191 int pcibios_add_platform_entries(struct pci_dev *pdev)
194 return device_create_file(&pdev->dev, &dev_attr_devspec);
197 #endif /* CONFIG_PPC_OF */
201 char __devinit *pcibios_setup(char *str)
206 void __devinit pcibios_setup_new_device(struct pci_dev *dev)
208 struct dev_archdata *sd = &dev->dev.archdata;
210 sd->of_node = pci_device_to_OF_node(dev);
212 pr_debug("PCI: device %s OF node: %s\n", pci_name(dev),
213 sd->of_node ? sd->of_node->full_name : "<none>");
215 sd->dma_ops = pci_dma_ops;
217 sd->dma_data = (void *)PCI_DRAM_OFFSET;
219 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
221 if (ppc_md.pci_dma_dev_setup)
222 ppc_md.pci_dma_dev_setup(dev);
224 EXPORT_SYMBOL(pcibios_setup_new_device);
227 * Reads the interrupt pin to determine if interrupt is use by card.
228 * If the interrupt is used, then gets the interrupt line from the
229 * openfirmware and sets it in the pci_dev and pci_config line.
231 int pci_read_irq_line(struct pci_dev *pci_dev)
236 /* The current device-tree that iSeries generates from the HV
237 * PCI informations doesn't contain proper interrupt routing,
238 * and all the fallback would do is print out crap, so we
239 * don't attempt to resolve the interrupts here at all, some
240 * iSeries specific fixup does it.
242 * In the long run, we will hopefully fix the generated device-tree
245 #ifdef CONFIG_PPC_ISERIES
246 if (firmware_has_feature(FW_FEATURE_ISERIES))
250 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
253 memset(&oirq, 0xff, sizeof(oirq));
255 /* Try to get a mapping from the device-tree */
256 if (of_irq_map_pci(pci_dev, &oirq)) {
259 /* If that fails, lets fallback to what is in the config
260 * space and map that through the default controller. We
261 * also set the type to level low since that's what PCI
262 * interrupts are. If your platform does differently, then
263 * either provide a proper interrupt tree or don't use this
266 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
270 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
271 line == 0xff || line == 0) {
274 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
277 virq = irq_create_mapping(NULL, line);
279 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
281 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
282 oirq.size, oirq.specifier[0], oirq.specifier[1],
283 oirq.controller->full_name);
285 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
289 pr_debug(" Failed to map !\n");
293 pr_debug(" Mapped to linux irq %d\n", virq);
299 EXPORT_SYMBOL(pci_read_irq_line);
302 * Platform support for /proc/bus/pci/X/Y mmap()s,
303 * modelled on the sparc64 implementation by Dave Miller.
308 * Adjust vm_pgoff of VMA such that it is the physical page offset
309 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
311 * Basically, the user finds the base address for his device which he wishes
312 * to mmap. They read the 32-bit value from the config space base register,
313 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
314 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
316 * Returns negative error code on failure, zero on success.
318 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
319 resource_size_t *offset,
320 enum pci_mmap_state mmap_state)
322 struct pci_controller *hose = pci_bus_to_host(dev->bus);
323 unsigned long io_offset = 0;
327 return NULL; /* should never happen */
329 /* If memory, add on the PCI bridge address offset */
330 if (mmap_state == pci_mmap_mem) {
331 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
332 *offset += hose->pci_mem_offset;
334 res_bit = IORESOURCE_MEM;
336 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
337 *offset += io_offset;
338 res_bit = IORESOURCE_IO;
342 * Check that the offset requested corresponds to one of the
343 * resources of the device.
345 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
346 struct resource *rp = &dev->resource[i];
347 int flags = rp->flags;
349 /* treat ROM as memory (should be already) */
350 if (i == PCI_ROM_RESOURCE)
351 flags |= IORESOURCE_MEM;
353 /* Active and same type? */
354 if ((flags & res_bit) == 0)
357 /* In the range of this resource? */
358 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
361 /* found it! construct the final physical address */
362 if (mmap_state == pci_mmap_io)
363 *offset += hose->io_base_phys - io_offset;
371 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
374 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
376 enum pci_mmap_state mmap_state,
379 unsigned long prot = pgprot_val(protection);
381 /* Write combine is always 0 on non-memory space mappings. On
382 * memory space, if the user didn't pass 1, we check for a
383 * "prefetchable" resource. This is a bit hackish, but we use
384 * this to workaround the inability of /sysfs to provide a write
387 if (mmap_state != pci_mmap_mem)
389 else if (write_combine == 0) {
390 if (rp->flags & IORESOURCE_PREFETCH)
394 /* XXX would be nice to have a way to ask for write-through */
395 prot |= _PAGE_NO_CACHE;
397 prot &= ~_PAGE_GUARDED;
399 prot |= _PAGE_GUARDED;
401 return __pgprot(prot);
405 * This one is used by /dev/mem and fbdev who have no clue about the
406 * PCI device, it tries to find the PCI device first and calls the
409 pgprot_t pci_phys_mem_access_prot(struct file *file,
414 struct pci_dev *pdev = NULL;
415 struct resource *found = NULL;
416 unsigned long prot = pgprot_val(protection);
417 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
420 if (page_is_ram(pfn))
421 return __pgprot(prot);
423 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
425 for_each_pci_dev(pdev) {
426 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
427 struct resource *rp = &pdev->resource[i];
428 int flags = rp->flags;
430 /* Active and same type? */
431 if ((flags & IORESOURCE_MEM) == 0)
433 /* In the range of this resource? */
434 if (offset < (rp->start & PAGE_MASK) ||
444 if (found->flags & IORESOURCE_PREFETCH)
445 prot &= ~_PAGE_GUARDED;
449 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
450 (unsigned long long)offset, prot);
452 return __pgprot(prot);
457 * Perform the actual remap of the pages for a PCI device mapping, as
458 * appropriate for this architecture. The region in the process to map
459 * is described by vm_start and vm_end members of VMA, the base physical
460 * address is found in vm_pgoff.
461 * The pci device structure is provided so that architectures may make mapping
462 * decisions on a per-device or per-bus basis.
464 * Returns a negative error code on failure, zero on success.
466 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
467 enum pci_mmap_state mmap_state, int write_combine)
469 resource_size_t offset =
470 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
474 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
478 vma->vm_pgoff = offset >> PAGE_SHIFT;
479 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
481 mmap_state, write_combine);
483 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
484 vma->vm_end - vma->vm_start, vma->vm_page_prot);
489 /* This provides legacy IO read access on a bus */
490 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
492 unsigned long offset;
493 struct pci_controller *hose = pci_bus_to_host(bus);
494 struct resource *rp = &hose->io_resource;
497 /* Check if port can be supported by that bus. We only check
498 * the ranges of the PHB though, not the bus itself as the rules
499 * for forwarding legacy cycles down bridges are not our problem
500 * here. So if the host bridge supports it, we do it.
502 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
505 if (!(rp->flags & IORESOURCE_IO))
507 if (offset < rp->start || (offset + size) > rp->end)
509 addr = hose->io_base_virt + port;
513 *((u8 *)val) = in_8(addr);
518 *((u16 *)val) = in_le16(addr);
523 *((u32 *)val) = in_le32(addr);
529 /* This provides legacy IO write access on a bus */
530 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
532 unsigned long offset;
533 struct pci_controller *hose = pci_bus_to_host(bus);
534 struct resource *rp = &hose->io_resource;
537 /* Check if port can be supported by that bus. We only check
538 * the ranges of the PHB though, not the bus itself as the rules
539 * for forwarding legacy cycles down bridges are not our problem
540 * here. So if the host bridge supports it, we do it.
542 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
545 if (!(rp->flags & IORESOURCE_IO))
547 if (offset < rp->start || (offset + size) > rp->end)
549 addr = hose->io_base_virt + port;
551 /* WARNING: The generic code is idiotic. It gets passed a pointer
552 * to what can be a 1, 2 or 4 byte quantity and always reads that
553 * as a u32, which means that we have to correct the location of
554 * the data read within those 32 bits for size 1 and 2
558 out_8(addr, val >> 24);
563 out_le16(addr, val >> 16);
574 /* This provides legacy IO or memory mmap access on a bus */
575 int pci_mmap_legacy_page_range(struct pci_bus *bus,
576 struct vm_area_struct *vma,
577 enum pci_mmap_state mmap_state)
579 struct pci_controller *hose = pci_bus_to_host(bus);
580 resource_size_t offset =
581 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
582 resource_size_t size = vma->vm_end - vma->vm_start;
585 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
586 pci_domain_nr(bus), bus->number,
587 mmap_state == pci_mmap_mem ? "MEM" : "IO",
588 (unsigned long long)offset,
589 (unsigned long long)(offset + size - 1));
591 if (mmap_state == pci_mmap_mem) {
592 if ((offset + size) > hose->isa_mem_size)
594 offset += hose->isa_mem_phys;
596 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
597 unsigned long roffset = offset + io_offset;
598 rp = &hose->io_resource;
599 if (!(rp->flags & IORESOURCE_IO))
601 if (roffset < rp->start || (roffset + size) > rp->end)
603 offset += hose->io_base_phys;
605 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
607 vma->vm_pgoff = offset >> PAGE_SHIFT;
608 vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot)
609 | _PAGE_NO_CACHE | _PAGE_GUARDED);
610 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
611 vma->vm_end - vma->vm_start,
615 void pci_resource_to_user(const struct pci_dev *dev, int bar,
616 const struct resource *rsrc,
617 resource_size_t *start, resource_size_t *end)
619 struct pci_controller *hose = pci_bus_to_host(dev->bus);
620 resource_size_t offset = 0;
625 if (rsrc->flags & IORESOURCE_IO)
626 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
628 /* We pass a fully fixed up address to userland for MMIO instead of
629 * a BAR value because X is lame and expects to be able to use that
630 * to pass to /dev/mem !
632 * That means that we'll have potentially 64 bits values where some
633 * userland apps only expect 32 (like X itself since it thinks only
634 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
637 * Hopefully, the sysfs insterface is immune to that gunk. Once X
638 * has been fixed (and the fix spread enough), we can re-enable the
639 * 2 lines below and pass down a BAR value to userland. In that case
640 * we'll also have to re-enable the matching code in
641 * __pci_mmap_make_offset().
646 else if (rsrc->flags & IORESOURCE_MEM)
647 offset = hose->pci_mem_offset;
650 *start = rsrc->start - offset;
651 *end = rsrc->end - offset;
655 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
656 * @hose: newly allocated pci_controller to be setup
657 * @dev: device node of the host bridge
658 * @primary: set if primary bus (32 bits only, soon to be deprecated)
660 * This function will parse the "ranges" property of a PCI host bridge device
661 * node and setup the resource mapping of a pci controller based on its
664 * Life would be boring if it wasn't for a few issues that we have to deal
667 * - We can only cope with one IO space range and up to 3 Memory space
668 * ranges. However, some machines (thanks Apple !) tend to split their
669 * space into lots of small contiguous ranges. So we have to coalesce.
671 * - We can only cope with all memory ranges having the same offset
672 * between CPU addresses and PCI addresses. Unfortunately, some bridges
673 * are setup for a large 1:1 mapping along with a small "window" which
674 * maps PCI address 0 to some arbitrary high address of the CPU space in
675 * order to give access to the ISA memory hole.
676 * The way out of here that I've chosen for now is to always set the
677 * offset based on the first resource found, then override it if we
678 * have a different offset and the previous was set by an ISA hole.
680 * - Some busses have IO space not starting at 0, which causes trouble with
681 * the way we do our IO resource renumbering. The code somewhat deals with
682 * it for 64 bits but I would expect problems on 32 bits.
684 * - Some 32 bits platforms such as 4xx can have physical space larger than
685 * 32 bits so we need to use 64 bits values for the parsing
687 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
688 struct device_node *dev,
693 int pna = of_n_addr_cells(dev);
695 int memno = 0, isa_hole = -1;
697 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
698 unsigned long long isa_mb = 0;
699 struct resource *res;
701 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
702 dev->full_name, primary ? "(primary)" : "");
704 /* Get ranges property */
705 ranges = of_get_property(dev, "ranges", &rlen);
710 while ((rlen -= np * 4) >= 0) {
711 /* Read next ranges element */
712 pci_space = ranges[0];
713 pci_addr = of_read_number(ranges + 1, 2);
714 cpu_addr = of_translate_address(dev, ranges + 3);
715 size = of_read_number(ranges + pna + 3, 2);
718 /* If we failed translation or got a zero-sized region
719 * (some FW try to feed us with non sensical zero sized regions
720 * such as power3 which look like some kind of attempt at exposing
721 * the VGA memory hole)
723 if (cpu_addr == OF_BAD_ADDR || size == 0)
726 /* Now consume following elements while they are contiguous */
727 for (; rlen >= np * sizeof(u32);
728 ranges += np, rlen -= np * 4) {
729 if (ranges[0] != pci_space)
731 pci_next = of_read_number(ranges + 1, 2);
732 cpu_next = of_translate_address(dev, ranges + 3);
733 if (pci_next != pci_addr + size ||
734 cpu_next != cpu_addr + size)
736 size += of_read_number(ranges + pna + 3, 2);
739 /* Act based on address space type */
741 switch ((pci_space >> 24) & 0x3) {
742 case 1: /* PCI IO space */
744 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
745 cpu_addr, cpu_addr + size - 1, pci_addr);
747 /* We support only one IO range */
748 if (hose->pci_io_size) {
750 " \\--> Skipped (too many) !\n");
754 /* On 32 bits, limit I/O space to 16MB */
755 if (size > 0x01000000)
758 /* 32 bits needs to map IOs here */
759 hose->io_base_virt = ioremap(cpu_addr, size);
761 /* Expect trouble if pci_addr is not 0 */
764 (unsigned long)hose->io_base_virt;
765 #endif /* CONFIG_PPC32 */
766 /* pci_io_size and io_base_phys always represent IO
767 * space starting at 0 so we factor in pci_addr
769 hose->pci_io_size = pci_addr + size;
770 hose->io_base_phys = cpu_addr - pci_addr;
773 res = &hose->io_resource;
774 res->flags = IORESOURCE_IO;
775 res->start = pci_addr;
777 case 2: /* PCI Memory space */
778 case 3: /* PCI 64 bits Memory space */
780 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
781 cpu_addr, cpu_addr + size - 1, pci_addr,
782 (pci_space & 0x40000000) ? "Prefetch" : "");
784 /* We support only 3 memory ranges */
787 " \\--> Skipped (too many) !\n");
790 /* Handles ISA memory hole space here */
794 if (primary || isa_mem_base == 0)
795 isa_mem_base = cpu_addr;
796 hose->isa_mem_phys = cpu_addr;
797 hose->isa_mem_size = size;
800 /* We get the PCI/Mem offset from the first range or
801 * the, current one if the offset came from an ISA
802 * hole. If they don't match, bugger.
805 (isa_hole >= 0 && pci_addr != 0 &&
806 hose->pci_mem_offset == isa_mb))
807 hose->pci_mem_offset = cpu_addr - pci_addr;
808 else if (pci_addr != 0 &&
809 hose->pci_mem_offset != cpu_addr - pci_addr) {
811 " \\--> Skipped (offset mismatch) !\n");
816 res = &hose->mem_resources[memno++];
817 res->flags = IORESOURCE_MEM;
818 if (pci_space & 0x40000000)
819 res->flags |= IORESOURCE_PREFETCH;
820 res->start = cpu_addr;
824 res->name = dev->full_name;
825 res->end = res->start + size - 1;
832 /* If there's an ISA hole and the pci_mem_offset is -not- matching
833 * the ISA hole offset, then we need to remove the ISA hole from
834 * the resource list for that brige
836 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
837 unsigned int next = isa_hole + 1;
838 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
840 memmove(&hose->mem_resources[isa_hole],
841 &hose->mem_resources[next],
842 sizeof(struct resource) * (memno - next));
843 hose->mem_resources[--memno].flags = 0;
847 /* Decide whether to display the domain number in /proc */
848 int pci_proc_domain(struct pci_bus *bus)
850 struct pci_controller *hose = pci_bus_to_host(bus);
852 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS))
854 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0)
855 return hose->global_number != 0;
859 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
860 struct resource *res)
862 resource_size_t offset = 0, mask = (resource_size_t)-1;
863 struct pci_controller *hose = pci_bus_to_host(dev->bus);
867 if (res->flags & IORESOURCE_IO) {
868 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
870 } else if (res->flags & IORESOURCE_MEM)
871 offset = hose->pci_mem_offset;
873 region->start = (res->start - offset) & mask;
874 region->end = (res->end - offset) & mask;
876 EXPORT_SYMBOL(pcibios_resource_to_bus);
878 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
879 struct pci_bus_region *region)
881 resource_size_t offset = 0, mask = (resource_size_t)-1;
882 struct pci_controller *hose = pci_bus_to_host(dev->bus);
886 if (res->flags & IORESOURCE_IO) {
887 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
889 } else if (res->flags & IORESOURCE_MEM)
890 offset = hose->pci_mem_offset;
891 res->start = (region->start + offset) & mask;
892 res->end = (region->end + offset) & mask;
894 EXPORT_SYMBOL(pcibios_bus_to_resource);
896 /* Fixup a bus resource into a linux resource */
897 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
899 struct pci_controller *hose = pci_bus_to_host(dev->bus);
900 resource_size_t offset = 0, mask = (resource_size_t)-1;
902 if (res->flags & IORESOURCE_IO) {
903 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
905 } else if (res->flags & IORESOURCE_MEM)
906 offset = hose->pci_mem_offset;
908 res->start = (res->start + offset) & mask;
909 res->end = (res->end + offset) & mask;
913 /* This header fixup will do the resource fixup for all devices as they are
914 * probed, but not for bridge ranges
916 static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
918 struct pci_controller *hose = pci_bus_to_host(dev->bus);
922 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
926 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
927 struct resource *res = dev->resource + i;
930 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
931 * consider 0 as an unassigned BAR value. It's technically
932 * a valid value, but linux doesn't like it... so when we can
933 * re-assign things, we do so, but if we can't, we keep it
934 * around and hope for the best...
936 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
937 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
939 (unsigned long long)res->start,
940 (unsigned long long)res->end,
941 (unsigned int)res->flags);
942 res->end -= res->start;
944 res->flags |= IORESOURCE_UNSET;
948 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
950 (unsigned long long)res->start,\
951 (unsigned long long)res->end,
952 (unsigned int)res->flags);
954 fixup_resource(res, dev);
956 pr_debug("PCI:%s %016llx-%016llx\n",
958 (unsigned long long)res->start,
959 (unsigned long long)res->end);
962 /* Call machine specific resource fixup */
963 if (ppc_md.pcibios_fixup_resources)
964 ppc_md.pcibios_fixup_resources(dev);
966 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
968 /* This function tries to figure out if a bridge resource has been initialized
969 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
970 * things go more smoothly when it gets it right. It should covers cases such
971 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
973 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
974 struct resource *res)
976 struct pci_controller *hose = pci_bus_to_host(bus);
977 struct pci_dev *dev = bus->self;
978 resource_size_t offset;
982 /* We don't do anything if PCI_PROBE_ONLY is set */
983 if (ppc_pci_flags & PPC_PCI_PROBE_ONLY)
986 /* Job is a bit different between memory and IO */
987 if (res->flags & IORESOURCE_MEM) {
988 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
989 * initialized by somebody
991 if (res->start != hose->pci_mem_offset)
994 /* The BAR is 0, let's check if memory decoding is enabled on
995 * the bridge. If not, we consider it unassigned
997 pci_read_config_word(dev, PCI_COMMAND, &command);
998 if ((command & PCI_COMMAND_MEMORY) == 0)
1001 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
1002 * resources covers that starting address (0 then it's good enough for
1005 for (i = 0; i < 3; i++) {
1006 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
1007 hose->mem_resources[i].start == hose->pci_mem_offset)
1011 /* Well, it starts at 0 and we know it will collide so we may as
1012 * well consider it as unassigned. That covers the Apple case.
1016 /* If the BAR is non-0, then we consider it assigned */
1017 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1018 if (((res->start - offset) & 0xfffffffful) != 0)
1021 /* Here, we are a bit different than memory as typically IO space
1022 * starting at low addresses -is- valid. What we do instead if that
1023 * we consider as unassigned anything that doesn't have IO enabled
1024 * in the PCI command register, and that's it.
1026 pci_read_config_word(dev, PCI_COMMAND, &command);
1027 if (command & PCI_COMMAND_IO)
1030 /* It's starting at 0 and IO is disabled in the bridge, consider
1037 /* Fixup resources of a PCI<->PCI bridge */
1038 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1040 struct resource *res;
1043 struct pci_dev *dev = bus->self;
1045 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1046 if ((res = bus->resource[i]) == NULL)
1050 if (i >= 3 && bus->self->transparent)
1053 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1055 (unsigned long long)res->start,\
1056 (unsigned long long)res->end,
1057 (unsigned int)res->flags);
1060 fixup_resource(res, dev);
1062 /* Try to detect uninitialized P2P bridge resources,
1063 * and clear them out so they get re-assigned later
1065 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1067 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1070 pr_debug("PCI:%s %016llx-%016llx\n",
1072 (unsigned long long)res->start,
1073 (unsigned long long)res->end);
1078 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1080 struct pci_dev *dev;
1082 pr_debug("PCI: Fixup bus %d (%s)\n",
1083 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1085 /* Setup DMA for all PCI devices on that bus */
1086 list_for_each_entry(dev, &bus->devices, bus_list)
1087 pcibios_setup_new_device(dev);
1089 /* Read default IRQs and fixup if necessary */
1090 list_for_each_entry(dev, &bus->devices, bus_list) {
1091 pci_read_irq_line(dev);
1092 if (ppc_md.pci_irq_fixup)
1093 ppc_md.pci_irq_fixup(dev);
1097 void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1099 /* Fix up the bus resources */
1100 if (bus->self != NULL)
1101 pcibios_fixup_bridge(bus);
1103 /* Platform specific bus fixups. This is currently only used
1104 * by fsl_pci and I'm hoping getting rid of it at some point
1106 if (ppc_md.pcibios_fixup_bus)
1107 ppc_md.pcibios_fixup_bus(bus);
1109 /* Setup bus DMA mappings */
1110 if (ppc_md.pci_dma_bus_setup)
1111 ppc_md.pci_dma_bus_setup(bus);
1114 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1116 /* When called from the generic PCI probe, read PCI<->PCI bridge
1117 * bases. This isn't called when generating the PCI tree from
1118 * the OF device-tree.
1120 if (bus->self != NULL)
1121 pci_read_bridge_bases(bus);
1123 /* Now fixup the bus bus */
1124 pcibios_setup_bus_self(bus);
1126 /* Now fixup devices on that bus */
1127 pcibios_setup_bus_devices(bus);
1129 EXPORT_SYMBOL(pcibios_fixup_bus);
1131 static int skip_isa_ioresource_align(struct pci_dev *dev)
1133 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
1134 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1140 * We need to avoid collisions with `mirrored' VGA ports
1141 * and other strange ISA hardware, so we always want the
1142 * addresses to be allocated in the 0x000-0x0ff region
1145 * Why? Because some silly external IO cards only decode
1146 * the low 10 bits of the IO address. The 0x00-0xff region
1147 * is reserved for motherboard devices that decode all 16
1148 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1149 * but we want to try to avoid allocating at 0x2900-0x2bff
1150 * which might have be mirrored at 0x0100-0x03ff..
1152 void pcibios_align_resource(void *data, struct resource *res,
1153 resource_size_t size, resource_size_t align)
1155 struct pci_dev *dev = data;
1157 if (res->flags & IORESOURCE_IO) {
1158 resource_size_t start = res->start;
1160 if (skip_isa_ioresource_align(dev))
1162 if (start & 0x300) {
1163 start = (start + 0x3ff) & ~0x3ff;
1168 EXPORT_SYMBOL(pcibios_align_resource);
1171 * Reparent resource children of pr that conflict with res
1172 * under res, and make res replace those children.
1174 static int __init reparent_resources(struct resource *parent,
1175 struct resource *res)
1177 struct resource *p, **pp;
1178 struct resource **firstpp = NULL;
1180 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1181 if (p->end < res->start)
1183 if (res->end < p->start)
1185 if (p->start < res->start || p->end > res->end)
1186 return -1; /* not completely contained */
1187 if (firstpp == NULL)
1190 if (firstpp == NULL)
1191 return -1; /* didn't find any conflicting entries? */
1192 res->parent = parent;
1193 res->child = *firstpp;
1197 for (p = res->child; p != NULL; p = p->sibling) {
1199 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1201 (unsigned long long)p->start,
1202 (unsigned long long)p->end, res->name);
1208 * Handle resources of PCI devices. If the world were perfect, we could
1209 * just allocate all the resource regions and do nothing more. It isn't.
1210 * On the other hand, we cannot just re-allocate all devices, as it would
1211 * require us to know lots of host bridge internals. So we attempt to
1212 * keep as much of the original configuration as possible, but tweak it
1213 * when it's found to be wrong.
1215 * Known BIOS problems we have to work around:
1216 * - I/O or memory regions not configured
1217 * - regions configured, but not enabled in the command register
1218 * - bogus I/O addresses above 64K used
1219 * - expansion ROMs left enabled (this may sound harmless, but given
1220 * the fact the PCI specs explicitly allow address decoders to be
1221 * shared between expansion ROMs and other resource regions, it's
1222 * at least dangerous)
1225 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1226 * This gives us fixed barriers on where we can allocate.
1227 * (2) Allocate resources for all enabled devices. If there is
1228 * a collision, just mark the resource as unallocated. Also
1229 * disable expansion ROMs during this step.
1230 * (3) Try to allocate resources for disabled devices. If the
1231 * resources were assigned correctly, everything goes well,
1232 * if they weren't, they won't disturb allocation of other
1234 * (4) Assign new addresses to resources which were either
1235 * not configured at all or misconfigured. If explicitly
1236 * requested by the user, configure expansion ROM address
1240 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1244 struct resource *res, *pr;
1246 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1247 pci_domain_nr(bus), bus->number);
1249 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1250 if ((res = bus->resource[i]) == NULL || !res->flags
1251 || res->start > res->end || res->parent)
1253 if (bus->parent == NULL)
1254 pr = (res->flags & IORESOURCE_IO) ?
1255 &ioport_resource : &iomem_resource;
1257 /* Don't bother with non-root busses when
1258 * re-assigning all resources. We clear the
1259 * resource flags as if they were colliding
1260 * and as such ensure proper re-allocation
1263 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)
1264 goto clear_resource;
1265 pr = pci_find_parent_resource(bus->self, res);
1267 /* this happens when the generic PCI
1268 * code (wrongly) decides that this
1269 * bridge is transparent -- paulus
1275 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1276 "[0x%x], parent %p (%s)\n",
1277 bus->self ? pci_name(bus->self) : "PHB",
1279 (unsigned long long)res->start,
1280 (unsigned long long)res->end,
1281 (unsigned int)res->flags,
1282 pr, (pr && pr->name) ? pr->name : "nil");
1284 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1285 if (request_resource(pr, res) == 0)
1288 * Must be a conflict with an existing entry.
1289 * Move that entry (or entries) under the
1290 * bridge resource and try again.
1292 if (reparent_resources(pr, res) == 0)
1295 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1296 "%d of PCI bridge %d, will remap\n", i, bus->number);
1301 list_for_each_entry(b, &bus->children, node)
1302 pcibios_allocate_bus_resources(b);
1305 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1307 struct resource *pr, *r = &dev->resource[idx];
1309 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1311 (unsigned long long)r->start,
1312 (unsigned long long)r->end,
1313 (unsigned int)r->flags);
1315 pr = pci_find_parent_resource(dev, r);
1316 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1317 request_resource(pr, r) < 0) {
1318 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1319 " of device %s, will remap\n", idx, pci_name(dev));
1321 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1323 (unsigned long long)pr->start,
1324 (unsigned long long)pr->end,
1325 (unsigned int)pr->flags);
1326 /* We'll assign a new address later */
1327 r->flags |= IORESOURCE_UNSET;
1333 static void __init pcibios_allocate_resources(int pass)
1335 struct pci_dev *dev = NULL;
1340 for_each_pci_dev(dev) {
1341 pci_read_config_word(dev, PCI_COMMAND, &command);
1342 for (idx = 0; idx < 6; idx++) {
1343 r = &dev->resource[idx];
1344 if (r->parent) /* Already allocated */
1346 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1347 continue; /* Not assigned at all */
1348 if (r->flags & IORESOURCE_IO)
1349 disabled = !(command & PCI_COMMAND_IO);
1351 disabled = !(command & PCI_COMMAND_MEMORY);
1352 if (pass == disabled)
1353 alloc_resource(dev, idx);
1357 r = &dev->resource[PCI_ROM_RESOURCE];
1358 if (r->flags & IORESOURCE_ROM_ENABLE) {
1359 /* Turn the ROM off, leave the resource region,
1360 * but keep it unregistered.
1363 pr_debug("PCI: Switching off ROM of %s\n",
1365 r->flags &= ~IORESOURCE_ROM_ENABLE;
1366 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1367 pci_write_config_dword(dev, dev->rom_base_reg,
1368 reg & ~PCI_ROM_ADDRESS_ENABLE);
1373 void __init pcibios_resource_survey(void)
1377 /* Allocate and assign resources. If we re-assign everything, then
1378 * we skip the allocate phase
1380 list_for_each_entry(b, &pci_root_buses, node)
1381 pcibios_allocate_bus_resources(b);
1383 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) {
1384 pcibios_allocate_resources(0);
1385 pcibios_allocate_resources(1);
1388 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1389 pr_debug("PCI: Assigning unassigned resouces...\n");
1390 pci_assign_unassigned_resources();
1393 /* Call machine dependent fixup */
1394 if (ppc_md.pcibios_fixup)
1395 ppc_md.pcibios_fixup();
1398 #ifdef CONFIG_HOTPLUG
1400 /* This is used by the pSeries hotplug driver to allocate resource
1401 * of newly plugged busses. We can try to consolidate with the
1402 * rest of the code later, for now, keep it as-is
1404 void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
1406 struct pci_dev *dev;
1407 struct pci_bus *child_bus;
1409 list_for_each_entry(dev, &bus->devices, bus_list) {
1412 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1413 struct resource *r = &dev->resource[i];
1415 if (r->parent || !r->start || !r->flags)
1417 pci_claim_resource(dev, i);
1421 list_for_each_entry(child_bus, &bus->children, node)
1422 pcibios_claim_one_bus(child_bus);
1424 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1425 #endif /* CONFIG_HOTPLUG */
1427 int pcibios_enable_device(struct pci_dev *dev, int mask)
1429 if (ppc_md.pcibios_enable_device_hook)
1430 if (ppc_md.pcibios_enable_device_hook(dev))
1433 return pci_enable_resources(dev, mask);
1436 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1438 struct pci_bus *bus = hose->bus;
1439 struct resource *res;
1442 /* Hookup PHB IO resource */
1443 bus->resource[0] = res = &hose->io_resource;
1446 printk(KERN_WARNING "PCI: I/O resource not set for host"
1447 " bridge %s (domain %d)\n",
1448 hose->dn->full_name, hose->global_number);
1450 /* Workaround for lack of IO resource only on 32-bit */
1451 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1452 res->end = res->start + IO_SPACE_LIMIT;
1453 res->flags = IORESOURCE_IO;
1454 #endif /* CONFIG_PPC32 */
1457 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1458 (unsigned long long)res->start,
1459 (unsigned long long)res->end,
1460 (unsigned long)res->flags);
1462 /* Hookup PHB Memory resources */
1463 for (i = 0; i < 3; ++i) {
1464 res = &hose->mem_resources[i];
1468 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1469 "host bridge %s (domain %d)\n",
1470 hose->dn->full_name, hose->global_number);
1472 /* Workaround for lack of MEM resource only on 32-bit */
1473 res->start = hose->pci_mem_offset;
1474 res->end = (resource_size_t)-1LL;
1475 res->flags = IORESOURCE_MEM;
1476 #endif /* CONFIG_PPC32 */
1478 bus->resource[i+1] = res;
1480 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1481 (unsigned long long)res->start,
1482 (unsigned long long)res->end,
1483 (unsigned long)res->flags);
1486 pr_debug("PCI: PHB MEM offset = %016llx\n",
1487 (unsigned long long)hose->pci_mem_offset);
1488 pr_debug("PCI: PHB IO offset = %08lx\n",
1489 (unsigned long)hose->io_base_virt - _IO_BASE);