2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras (paulus@samba.org)
14 * This file handles the architecture-dependent parts of hardware exceptions
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/a.out.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/prctl.h>
31 #include <linux/delay.h>
32 #include <linux/kprobes.h>
33 #include <linux/kexec.h>
34 #include <linux/backlight.h>
35 #include <linux/bug.h>
36 #include <linux/kdebug.h>
38 #include <asm/pgtable.h>
39 #include <asm/uaccess.h>
40 #include <asm/system.h>
42 #include <asm/machdep.h>
48 #ifdef CONFIG_PMAC_BACKLIGHT
49 #include <asm/backlight.h>
52 #include <asm/firmware.h>
53 #include <asm/processor.h>
55 #include <asm/kexec.h>
57 #ifdef CONFIG_DEBUGGER
58 int (*__debugger)(struct pt_regs *regs);
59 int (*__debugger_ipi)(struct pt_regs *regs);
60 int (*__debugger_bpt)(struct pt_regs *regs);
61 int (*__debugger_sstep)(struct pt_regs *regs);
62 int (*__debugger_iabr_match)(struct pt_regs *regs);
63 int (*__debugger_dabr_match)(struct pt_regs *regs);
64 int (*__debugger_fault_handler)(struct pt_regs *regs);
66 EXPORT_SYMBOL(__debugger);
67 EXPORT_SYMBOL(__debugger_ipi);
68 EXPORT_SYMBOL(__debugger_bpt);
69 EXPORT_SYMBOL(__debugger_sstep);
70 EXPORT_SYMBOL(__debugger_iabr_match);
71 EXPORT_SYMBOL(__debugger_dabr_match);
72 EXPORT_SYMBOL(__debugger_fault_handler);
76 * Trap & Exception support
79 #ifdef CONFIG_PMAC_BACKLIGHT
80 static void pmac_backlight_unblank(void)
82 mutex_lock(&pmac_backlight_mutex);
84 struct backlight_properties *props;
86 props = &pmac_backlight->props;
87 props->brightness = props->max_brightness;
88 props->power = FB_BLANK_UNBLANK;
89 backlight_update_status(pmac_backlight);
91 mutex_unlock(&pmac_backlight_mutex);
94 static inline void pmac_backlight_unblank(void) { }
97 int die(const char *str, struct pt_regs *regs, long err)
102 int lock_owner_depth;
104 .lock = __SPIN_LOCK_UNLOCKED(die.lock),
106 .lock_owner_depth = 0
108 static int die_counter;
116 if (die.lock_owner != raw_smp_processor_id()) {
118 spin_lock_irqsave(&die.lock, flags);
119 die.lock_owner = smp_processor_id();
120 die.lock_owner_depth = 0;
122 if (machine_is(powermac))
123 pmac_backlight_unblank();
125 local_save_flags(flags);
128 if (++die.lock_owner_depth < 3) {
129 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
130 #ifdef CONFIG_PREEMPT
134 printk("SMP NR_CPUS=%d ", NR_CPUS);
136 #ifdef CONFIG_DEBUG_PAGEALLOC
137 printk("DEBUG_PAGEALLOC ");
142 printk("%s\n", ppc_md.name ? ppc_md.name : "");
147 printk("Recursive die() failure, output suppressed\n");
152 add_taint(TAINT_DIE);
153 spin_unlock_irqrestore(&die.lock, flags);
155 if (kexec_should_crash(current) ||
156 kexec_sr_activated(smp_processor_id()))
158 crash_kexec_secondary(regs);
161 panic("Fatal exception in interrupt");
164 panic("Fatal exception");
172 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
176 if (!user_mode(regs)) {
177 if (die("Exception in kernel mode", regs, signr))
181 memset(&info, 0, sizeof(info));
182 info.si_signo = signr;
184 info.si_addr = (void __user *) addr;
185 force_sig_info(signr, &info, current);
188 * Init gets no signals that it doesn't have a handler for.
189 * That's all very well, but if it has caused a synchronous
190 * exception and we ignore the resulting signal, it will just
191 * generate the same exception over and over again and we get
192 * nowhere. Better to kill it and let the kernel panic.
194 if (is_init(current)) {
195 __sighandler_t handler;
197 spin_lock_irq(¤t->sighand->siglock);
198 handler = current->sighand->action[signr-1].sa.sa_handler;
199 spin_unlock_irq(¤t->sighand->siglock);
200 if (handler == SIG_DFL) {
201 /* init has generated a synchronous exception
202 and it doesn't have a handler for the signal */
203 printk(KERN_CRIT "init has generated signal %d "
204 "but has no handler for it\n", signr);
211 void system_reset_exception(struct pt_regs *regs)
213 /* See if any machine dependent calls */
214 if (ppc_md.system_reset_exception) {
215 if (ppc_md.system_reset_exception(regs))
220 cpu_set(smp_processor_id(), cpus_in_sr);
223 die("System Reset", regs, SIGABRT);
226 * Some CPUs when released from the debugger will execute this path.
227 * These CPUs entered the debugger via a soft-reset. If the CPU was
228 * hung before entering the debugger it will return to the hung
229 * state when exiting this function. This causes a problem in
230 * kdump since the hung CPU(s) will not respond to the IPI sent
231 * from kdump. To prevent the problem we call crash_kexec_secondary()
232 * here. If a kdump had not been initiated or we exit the debugger
233 * with the "exit and recover" command (x) crash_kexec_secondary()
234 * will return after 5ms and the CPU returns to its previous state.
236 crash_kexec_secondary(regs);
238 /* Must die if the interrupt is not recoverable */
239 if (!(regs->msr & MSR_RI))
240 panic("Unrecoverable System Reset");
242 /* What should we do here? We could issue a shutdown or hard reset. */
247 * I/O accesses can cause machine checks on powermacs.
248 * Check if the NIP corresponds to the address of a sync
249 * instruction for which there is an entry in the exception
251 * Note that the 601 only takes a machine check on TEA
252 * (transfer error ack) signal assertion, and does not
253 * set any of the top 16 bits of SRR1.
256 static inline int check_io_access(struct pt_regs *regs)
259 unsigned long msr = regs->msr;
260 const struct exception_table_entry *entry;
261 unsigned int *nip = (unsigned int *)regs->nip;
263 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
264 && (entry = search_exception_tables(regs->nip)) != NULL) {
266 * Check that it's a sync instruction, or somewhere
267 * in the twi; isync; nop sequence that inb/inw/inl uses.
268 * As the address is in the exception table
269 * we should be able to read the instr there.
270 * For the debug message, we look at the preceding
273 if (*nip == 0x60000000) /* nop */
275 else if (*nip == 0x4c00012c) /* isync */
277 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
282 rb = (*nip >> 11) & 0x1f;
283 printk(KERN_DEBUG "%s bad port %lx at %p\n",
284 (*nip & 0x100)? "OUT to": "IN from",
285 regs->gpr[rb] - _IO_BASE, nip);
287 regs->nip = entry->fixup;
291 #endif /* CONFIG_PPC32 */
295 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
296 /* On 4xx, the reason for the machine check or program exception
298 #define get_reason(regs) ((regs)->dsisr)
299 #ifndef CONFIG_FSL_BOOKE
300 #define get_mc_reason(regs) ((regs)->dsisr)
302 #define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK)
304 #define REASON_FP ESR_FP
305 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
306 #define REASON_PRIVILEGED ESR_PPR
307 #define REASON_TRAP ESR_PTR
309 /* single-step stuff */
310 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
311 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
314 /* On non-4xx, the reason for the machine check or program
315 exception is in the MSR. */
316 #define get_reason(regs) ((regs)->msr)
317 #define get_mc_reason(regs) ((regs)->msr)
318 #define REASON_FP 0x100000
319 #define REASON_ILLEGAL 0x80000
320 #define REASON_PRIVILEGED 0x40000
321 #define REASON_TRAP 0x20000
323 #define single_stepping(regs) ((regs)->msr & MSR_SE)
324 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
327 static int generic_machine_check_exception(struct pt_regs *regs)
329 unsigned long reason = get_mc_reason(regs);
331 #if defined(CONFIG_4xx) && !defined(CONFIG_440A)
332 if (reason & ESR_IMCP) {
333 printk("Instruction");
334 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
337 printk(" machine check in kernel mode.\n");
338 #elif defined(CONFIG_440A)
339 printk("Machine check in kernel mode.\n");
340 if (reason & ESR_IMCP){
341 printk("Instruction Synchronous Machine Check exception\n");
342 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
345 u32 mcsr = mfspr(SPRN_MCSR);
347 printk("Instruction Read PLB Error\n");
349 printk("Data Read PLB Error\n");
351 printk("Data Write PLB Error\n");
352 if (mcsr & MCSR_TLBP)
353 printk("TLB Parity Error\n");
354 if (mcsr & MCSR_ICP){
355 flush_instruction_cache();
356 printk("I-Cache Parity Error\n");
358 if (mcsr & MCSR_DCSP)
359 printk("D-Cache Search Parity Error\n");
360 if (mcsr & MCSR_DCFP)
361 printk("D-Cache Flush Parity Error\n");
362 if (mcsr & MCSR_IMPE)
363 printk("Machine Check exception is imprecise\n");
366 mtspr(SPRN_MCSR, mcsr);
368 #elif defined (CONFIG_E500)
369 printk("Machine check in kernel mode.\n");
370 printk("Caused by (from MCSR=%lx): ", reason);
372 if (reason & MCSR_MCP)
373 printk("Machine Check Signal\n");
374 if (reason & MCSR_ICPERR)
375 printk("Instruction Cache Parity Error\n");
376 if (reason & MCSR_DCP_PERR)
377 printk("Data Cache Push Parity Error\n");
378 if (reason & MCSR_DCPERR)
379 printk("Data Cache Parity Error\n");
380 if (reason & MCSR_BUS_IAERR)
381 printk("Bus - Instruction Address Error\n");
382 if (reason & MCSR_BUS_RAERR)
383 printk("Bus - Read Address Error\n");
384 if (reason & MCSR_BUS_WAERR)
385 printk("Bus - Write Address Error\n");
386 if (reason & MCSR_BUS_IBERR)
387 printk("Bus - Instruction Data Error\n");
388 if (reason & MCSR_BUS_RBERR)
389 printk("Bus - Read Data Bus Error\n");
390 if (reason & MCSR_BUS_WBERR)
391 printk("Bus - Read Data Bus Error\n");
392 if (reason & MCSR_BUS_IPERR)
393 printk("Bus - Instruction Parity Error\n");
394 if (reason & MCSR_BUS_RPERR)
395 printk("Bus - Read Parity Error\n");
396 #elif defined (CONFIG_E200)
397 printk("Machine check in kernel mode.\n");
398 printk("Caused by (from MCSR=%lx): ", reason);
400 if (reason & MCSR_MCP)
401 printk("Machine Check Signal\n");
402 if (reason & MCSR_CP_PERR)
403 printk("Cache Push Parity Error\n");
404 if (reason & MCSR_CPERR)
405 printk("Cache Parity Error\n");
406 if (reason & MCSR_EXCP_ERR)
407 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
408 if (reason & MCSR_BUS_IRERR)
409 printk("Bus - Read Bus Error on instruction fetch\n");
410 if (reason & MCSR_BUS_DRERR)
411 printk("Bus - Read Bus Error on data load\n");
412 if (reason & MCSR_BUS_WRERR)
413 printk("Bus - Write Bus Error on buffered store or cache line push\n");
414 #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
415 printk("Machine check in kernel mode.\n");
416 printk("Caused by (from SRR1=%lx): ", reason);
417 switch (reason & 0x601F0000) {
419 printk("Machine check signal\n");
421 case 0: /* for 601 */
423 case 0x140000: /* 7450 MSS error and TEA */
424 printk("Transfer error ack signal\n");
427 printk("Data parity error signal\n");
430 printk("Address parity error signal\n");
433 printk("L1 Data Cache error\n");
436 printk("L1 Instruction Cache error\n");
439 printk("L2 data cache parity error\n");
442 printk("Unknown values in msr\n");
444 #endif /* CONFIG_4xx */
449 void machine_check_exception(struct pt_regs *regs)
453 /* See if any machine dependent calls */
454 if (ppc_md.machine_check_exception)
455 recover = ppc_md.machine_check_exception(regs);
457 recover = generic_machine_check_exception(regs);
462 if (user_mode(regs)) {
464 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
468 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
469 /* the qspan pci read routines can cause machine checks -- Cort */
470 bad_page_fault(regs, regs->dar, SIGBUS);
474 if (debugger_fault_handler(regs)) {
479 if (check_io_access(regs))
482 if (debugger_fault_handler(regs))
484 die("Machine check", regs, SIGBUS);
486 /* Must die if the interrupt is not recoverable */
487 if (!(regs->msr & MSR_RI))
488 panic("Unrecoverable Machine check");
491 void SMIException(struct pt_regs *regs)
493 die("System Management Interrupt", regs, SIGABRT);
496 void unknown_exception(struct pt_regs *regs)
498 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
499 regs->nip, regs->msr, regs->trap);
501 _exception(SIGTRAP, regs, 0, 0);
504 void instruction_breakpoint_exception(struct pt_regs *regs)
506 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
507 5, SIGTRAP) == NOTIFY_STOP)
509 if (debugger_iabr_match(regs))
511 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
514 void RunModeException(struct pt_regs *regs)
516 _exception(SIGTRAP, regs, 0, 0);
519 void __kprobes single_step_exception(struct pt_regs *regs)
521 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
523 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
524 5, SIGTRAP) == NOTIFY_STOP)
526 if (debugger_sstep(regs))
529 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
533 * After we have successfully emulated an instruction, we have to
534 * check if the instruction was being single-stepped, and if so,
535 * pretend we got a single-step exception. This was pointed out
536 * by Kumar Gala. -- paulus
538 static void emulate_single_step(struct pt_regs *regs)
540 if (single_stepping(regs)) {
541 clear_single_step(regs);
542 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
546 static inline int __parse_fpscr(unsigned long fpscr)
550 /* Invalid operation */
551 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
555 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
559 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
563 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
567 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
573 static void parse_fpe(struct pt_regs *regs)
577 flush_fp_to_thread(current);
579 code = __parse_fpscr(current->thread.fpscr.val);
581 _exception(SIGFPE, regs, code, regs->nip);
585 * Illegal instruction emulation support. Originally written to
586 * provide the PVR to user applications using the mfspr rd, PVR.
587 * Return non-zero if we can't emulate, or -EFAULT if the associated
588 * memory access caused an access fault. Return zero on success.
590 * There are a couple of ways to do this, either "decode" the instruction
591 * or directly match lots of bits. In this case, matching lots of
592 * bits is faster and easier.
595 #define INST_MFSPR_PVR 0x7c1f42a6
596 #define INST_MFSPR_PVR_MASK 0xfc1fffff
598 #define INST_DCBA 0x7c0005ec
599 #define INST_DCBA_MASK 0xfc0007fe
601 #define INST_MCRXR 0x7c000400
602 #define INST_MCRXR_MASK 0xfc0007fe
604 #define INST_STRING 0x7c00042a
605 #define INST_STRING_MASK 0xfc0007fe
606 #define INST_STRING_GEN_MASK 0xfc00067e
607 #define INST_LSWI 0x7c0004aa
608 #define INST_LSWX 0x7c00042a
609 #define INST_STSWI 0x7c0005aa
610 #define INST_STSWX 0x7c00052a
612 #define INST_POPCNTB 0x7c0000f4
613 #define INST_POPCNTB_MASK 0xfc0007fe
615 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
617 u8 rT = (instword >> 21) & 0x1f;
618 u8 rA = (instword >> 16) & 0x1f;
619 u8 NB_RB = (instword >> 11) & 0x1f;
624 /* Early out if we are an invalid form of lswx */
625 if ((instword & INST_STRING_MASK) == INST_LSWX)
626 if ((rT == rA) || (rT == NB_RB))
629 EA = (rA == 0) ? 0 : regs->gpr[rA];
631 switch (instword & INST_STRING_MASK) {
635 num_bytes = regs->xer & 0x7f;
639 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
645 while (num_bytes != 0)
648 u32 shift = 8 * (3 - (pos & 0x3));
650 switch ((instword & INST_STRING_MASK)) {
653 if (get_user(val, (u8 __user *)EA))
655 /* first time updating this reg,
659 regs->gpr[rT] |= val << shift;
663 val = regs->gpr[rT] >> shift;
664 if (put_user(val, (u8 __user *)EA))
668 /* move EA to next address */
672 /* manage our position within the register */
683 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
688 ra = (instword >> 16) & 0x1f;
689 rs = (instword >> 21) & 0x1f;
692 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
693 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
694 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
700 static int emulate_instruction(struct pt_regs *regs)
705 if (!user_mode(regs) || (regs->msr & MSR_LE))
707 CHECK_FULL_REGS(regs);
709 if (get_user(instword, (u32 __user *)(regs->nip)))
712 /* Emulate the mfspr rD, PVR. */
713 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
714 rd = (instword >> 21) & 0x1f;
715 regs->gpr[rd] = mfspr(SPRN_PVR);
719 /* Emulating the dcba insn is just a no-op. */
720 if ((instword & INST_DCBA_MASK) == INST_DCBA)
723 /* Emulate the mcrxr insn. */
724 if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
725 int shift = (instword >> 21) & 0x1c;
726 unsigned long msk = 0xf0000000UL >> shift;
728 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
729 regs->xer &= ~0xf0000000UL;
733 /* Emulate load/store string insn. */
734 if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
735 return emulate_string_inst(regs, instword);
737 /* Emulate the popcntb (Population Count Bytes) instruction. */
738 if ((instword & INST_POPCNTB_MASK) == INST_POPCNTB) {
739 return emulate_popcntb_inst(regs, instword);
745 int is_valid_bugaddr(unsigned long addr)
747 return is_kernel_addr(addr);
750 void __kprobes program_check_exception(struct pt_regs *regs)
752 unsigned int reason = get_reason(regs);
753 extern int do_mathemu(struct pt_regs *regs);
755 /* We can now get here via a FP Unavailable exception if the core
756 * has no FPU, in that case the reason flags will be 0 */
758 if (reason & REASON_FP) {
759 /* IEEE FP exception */
763 if (reason & REASON_TRAP) {
765 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
768 if (debugger_bpt(regs))
771 if (!(regs->msr & MSR_PR) && /* not user-mode */
772 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
776 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
782 #ifdef CONFIG_MATH_EMULATION
783 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
784 * but there seems to be a hardware bug on the 405GP (RevD)
785 * that means ESR is sometimes set incorrectly - either to
786 * ESR_DST (!?) or 0. In the process of chasing this with the
787 * hardware people - not sure if it can happen on any illegal
788 * instruction or only on FP instructions, whether there is a
789 * pattern to occurences etc. -dgibson 31/Mar/2003 */
790 switch (do_mathemu(regs)) {
792 emulate_single_step(regs);
796 code = __parse_fpscr(current->thread.fpscr.val);
797 _exception(SIGFPE, regs, code, regs->nip);
801 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
804 /* fall through on any other errors */
805 #endif /* CONFIG_MATH_EMULATION */
807 /* Try to emulate it if we should. */
808 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
809 switch (emulate_instruction(regs)) {
812 emulate_single_step(regs);
815 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
820 if (reason & REASON_PRIVILEGED)
821 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
823 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
826 void alignment_exception(struct pt_regs *regs)
828 int sig, code, fixed = 0;
830 /* we don't implement logging of alignment exceptions */
831 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
832 fixed = fix_alignment(regs);
835 regs->nip += 4; /* skip over emulated instruction */
836 emulate_single_step(regs);
840 /* Operand address was bad */
841 if (fixed == -EFAULT) {
849 _exception(sig, regs, code, regs->dar);
851 bad_page_fault(regs, regs->dar, sig);
854 void StackOverflow(struct pt_regs *regs)
856 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
857 current, regs->gpr[1]);
860 panic("kernel stack overflow");
863 void nonrecoverable_exception(struct pt_regs *regs)
865 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
866 regs->nip, regs->msr);
868 die("nonrecoverable exception", regs, SIGKILL);
871 void trace_syscall(struct pt_regs *regs)
873 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
874 current, current->pid, regs->nip, regs->link, regs->gpr[0],
875 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
878 void kernel_fp_unavailable_exception(struct pt_regs *regs)
880 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
881 "%lx at %lx\n", regs->trap, regs->nip);
882 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
885 void altivec_unavailable_exception(struct pt_regs *regs)
887 if (user_mode(regs)) {
888 /* A user program has executed an altivec instruction,
889 but this kernel doesn't support altivec. */
890 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
894 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
895 "%lx at %lx\n", regs->trap, regs->nip);
896 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
899 void performance_monitor_exception(struct pt_regs *regs)
905 void SoftwareEmulation(struct pt_regs *regs)
907 extern int do_mathemu(struct pt_regs *);
908 extern int Soft_emulate_8xx(struct pt_regs *);
909 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
913 CHECK_FULL_REGS(regs);
915 if (!user_mode(regs)) {
917 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
920 #ifdef CONFIG_MATH_EMULATION
921 errcode = do_mathemu(regs);
925 emulate_single_step(regs);
929 code = __parse_fpscr(current->thread.fpscr.val);
930 _exception(SIGFPE, regs, code, regs->nip);
934 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
937 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
941 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
942 errcode = Soft_emulate_8xx(regs);
945 emulate_single_step(regs);
948 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
951 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
955 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
958 #endif /* CONFIG_8xx */
960 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
962 void DebugException(struct pt_regs *regs, unsigned long debug_status)
964 if (debug_status & DBSR_IC) { /* instruction completion */
965 regs->msr &= ~MSR_DE;
966 if (user_mode(regs)) {
967 current->thread.dbcr0 &= ~DBCR0_IC;
969 /* Disable instruction completion */
970 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
971 /* Clear the instruction completion event */
972 mtspr(SPRN_DBSR, DBSR_IC);
973 if (debugger_sstep(regs))
976 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
979 #endif /* CONFIG_4xx || CONFIG_BOOKE */
981 #if !defined(CONFIG_TAU_INT)
982 void TAUException(struct pt_regs *regs)
984 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
985 regs->nip, regs->msr, regs->trap, print_tainted());
987 #endif /* CONFIG_INT_TAU */
989 #ifdef CONFIG_ALTIVEC
990 void altivec_assist_exception(struct pt_regs *regs)
994 if (!user_mode(regs)) {
995 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
996 " at %lx\n", regs->nip);
997 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1000 flush_altivec_to_thread(current);
1002 err = emulate_altivec(regs);
1004 regs->nip += 4; /* skip emulated instruction */
1005 emulate_single_step(regs);
1009 if (err == -EFAULT) {
1010 /* got an error reading the instruction */
1011 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1013 /* didn't recognize the instruction */
1014 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1015 if (printk_ratelimit())
1016 printk(KERN_ERR "Unrecognized altivec instruction "
1017 "in %s at %lx\n", current->comm, regs->nip);
1018 current->thread.vscr.u[3] |= 0x10000;
1021 #endif /* CONFIG_ALTIVEC */
1023 #ifdef CONFIG_FSL_BOOKE
1024 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1025 unsigned long error_code)
1027 /* We treat cache locking instructions from the user
1028 * as priv ops, in the future we could try to do
1031 if (error_code & (ESR_DLK|ESR_ILK))
1032 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1035 #endif /* CONFIG_FSL_BOOKE */
1038 void SPEFloatingPointException(struct pt_regs *regs)
1040 unsigned long spefscr;
1044 spefscr = current->thread.spefscr;
1045 fpexc_mode = current->thread.fpexc_mode;
1047 /* Hardware does not neccessarily set sticky
1048 * underflow/overflow/invalid flags */
1049 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1051 spefscr |= SPEFSCR_FOVFS;
1053 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1055 spefscr |= SPEFSCR_FUNFS;
1057 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1059 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1061 spefscr |= SPEFSCR_FINVS;
1063 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1066 current->thread.spefscr = spefscr;
1068 _exception(SIGFPE, regs, code, regs->nip);
1074 * We enter here if we get an unrecoverable exception, that is, one
1075 * that happened at a point where the RI (recoverable interrupt) bit
1076 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1077 * we therefore lost state by taking this exception.
1079 void unrecoverable_exception(struct pt_regs *regs)
1081 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1082 regs->trap, regs->nip);
1083 die("Unrecoverable exception", regs, SIGABRT);
1086 #ifdef CONFIG_BOOKE_WDT
1088 * Default handler for a Watchdog exception,
1089 * spins until a reboot occurs
1091 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1093 /* Generic WatchdogHandler, implement your own */
1094 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1098 void WatchdogException(struct pt_regs *regs)
1100 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1101 WatchdogHandler(regs);
1106 * We enter here if we discover during exception entry that we are
1107 * running in supervisor mode with a userspace value in the stack pointer.
1109 void kernel_bad_stack(struct pt_regs *regs)
1111 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1112 regs->gpr[1], regs->nip);
1113 die("Bad kernel stack pointer", regs, SIGABRT);
1116 void __init trap_init(void)