2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
23 #include <linux/config.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
35 #include <asm/ppcdebug.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/abs_addr.h>
54 #include <asm/sections.h>
57 #define DBG(fmt...) udbg_printf(fmt)
63 * Note: pte --> Linux PTE
64 * HPTE --> PowerPC Hashed Page Table Entry
67 * htab_initialize is called with the MMU off (of course), but
68 * the kernel has been copied down to zero so it can directly
69 * reference global data. At this point it is very difficult
70 * to print debug info.
75 extern unsigned long dart_tablebase;
76 #endif /* CONFIG_U3_DART */
79 unsigned long htab_hash_mask;
86 static inline void loop_forever(void)
88 volatile unsigned long x = 1;
93 static inline void create_pte_mapping(unsigned long start, unsigned long end,
94 unsigned long mode, int large)
98 unsigned long tmp_mode;
103 vflags = HPTE_V_BOLTED | HPTE_V_LARGE;
106 vflags = HPTE_V_BOLTED;
109 for (addr = start; addr < end; addr += step) {
110 unsigned long vpn, hash, hpteg;
111 unsigned long vsid = get_kernel_vsid(addr);
112 unsigned long va = (vsid << 28) | (addr & 0xfffffff);
116 vpn = va >> HPAGE_SHIFT;
118 vpn = va >> PAGE_SHIFT;
123 /* Make non-kernel text non-executable */
124 if (!in_kernel_text(addr))
125 tmp_mode = mode | HW_NO_EXEC;
127 hash = hpt_hash(vpn, large);
129 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
131 #ifdef CONFIG_PPC_ISERIES
132 if (systemcfg->platform & PLATFORM_ISERIES_LPAR)
133 ret = iSeries_hpte_bolt_or_insert(hpteg, va,
134 virt_to_abs(addr) >> PAGE_SHIFT,
138 #ifdef CONFIG_PPC_PSERIES
139 if (systemcfg->platform & PLATFORM_LPAR)
140 ret = pSeries_lpar_hpte_insert(hpteg, va,
141 virt_to_abs(addr) >> PAGE_SHIFT,
145 #ifdef CONFIG_PPC_MULTIPLATFORM
146 ret = native_hpte_insert(hpteg, va,
147 virt_to_abs(addr) >> PAGE_SHIFT,
152 ppc64_terminate_msg(0x20, "create_pte_mapping");
158 static unsigned long get_hashtable_size(void)
160 unsigned long rnd_mem_size, pteg_count;
162 /* If hash size wasn't obtained in prom.c, we calculate it now based on
166 return 1UL << ppc64_pft_size;
168 /* round mem_size up to next power of 2 */
169 rnd_mem_size = 1UL << __ilog2(systemcfg->physicalMemorySize);
170 if (rnd_mem_size < systemcfg->physicalMemorySize)
174 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
176 return pteg_count << 7;
179 void __init htab_initialize(void)
181 unsigned long table, htab_size_bytes;
182 unsigned long pteg_count;
183 unsigned long mode_rw;
184 int i, use_largepages = 0;
185 unsigned long base = 0, size = 0;
186 extern unsigned long tce_alloc_start, tce_alloc_end;
188 DBG(" -> htab_initialize()\n");
191 * Calculate the required size of the htab. We want the number of
192 * PTEGs to equal one half the number of real pages.
194 htab_size_bytes = get_hashtable_size();
195 pteg_count = htab_size_bytes >> 7;
197 /* For debug, make the HTAB 1/8 as big as it normally would be. */
198 ifppcdebug(PPCDBG_HTABSIZE) {
200 htab_size_bytes = pteg_count << 7;
203 htab_hash_mask = pteg_count - 1;
205 if (systemcfg->platform & PLATFORM_LPAR) {
206 /* Using a hypervisor which owns the htab */
210 /* Find storage for the HPT. Must be contiguous in
211 * the absolute address space.
213 table = lmb_alloc(htab_size_bytes, htab_size_bytes);
215 DBG("Hash table allocated at %lx, size: %lx\n", table,
219 ppc64_terminate_msg(0x20, "hpt space");
222 htab_address = abs_to_virt(table);
224 /* htab absolute addr + encoded htabsize */
225 _SDR1 = table + __ilog2(pteg_count) - 11;
227 /* Initialize the HPT with no entries */
228 memset((void *)table, 0, htab_size_bytes);
231 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
233 /* On U3 based machines, we need to reserve the DART area and
234 * _NOT_ map it to avoid cache paradoxes as it's remapped non
237 if (cpu_has_feature(CPU_FTR_16M_PAGE))
240 /* create bolted the linear mapping in the hash table */
241 for (i=0; i < lmb.memory.cnt; i++) {
242 base = lmb.memory.region[i].base + KERNELBASE;
243 size = lmb.memory.region[i].size;
245 DBG("creating mapping for region: %lx : %lx\n", base, size);
247 #ifdef CONFIG_U3_DART
248 /* Do not map the DART space. Fortunately, it will be aligned
249 * in such a way that it will not cross two lmb regions and will
250 * fit within a single 16Mb page.
251 * The DART space is assumed to be a full 16Mb region even if we
252 * only use 2Mb of that space. We will use more of it later for
253 * AGP GART. We have to use a full 16Mb large page.
255 DBG("DART base: %lx\n", dart_tablebase);
257 if (dart_tablebase != 0 && dart_tablebase >= base
258 && dart_tablebase < (base + size)) {
259 if (base != dart_tablebase)
260 create_pte_mapping(base, dart_tablebase, mode_rw,
262 if ((base + size) > (dart_tablebase + 16*MB))
263 create_pte_mapping(dart_tablebase + 16*MB, base + size,
264 mode_rw, use_largepages);
267 #endif /* CONFIG_U3_DART */
268 create_pte_mapping(base, base + size, mode_rw, use_largepages);
272 * If we have a memory_limit and we've allocated TCEs then we need to
273 * explicitly map the TCE area at the top of RAM. We also cope with the
274 * case that the TCEs start below memory_limit.
275 * tce_alloc_start/end are 16MB aligned so the mapping should work
276 * for either 4K or 16MB pages.
278 if (tce_alloc_start) {
279 tce_alloc_start += KERNELBASE;
280 tce_alloc_end += KERNELBASE;
282 if (base + size >= tce_alloc_start)
283 tce_alloc_start = base + size + 1;
285 create_pte_mapping(tce_alloc_start, tce_alloc_end,
286 mode_rw, use_largepages);
289 DBG(" <- htab_initialize()\n");
295 * Called by asm hashtable.S for doing lazy icache flush
297 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
301 if (!pfn_valid(pte_pfn(pte)))
304 page = pte_page(pte);
307 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
309 __flush_dcache_icache(page_address(page));
310 set_bit(PG_arch_1, &page->flags);
319 * 1 - normal page fault
320 * -1 - critical hash insertion error
322 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
326 struct mm_struct *mm;
333 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
336 switch (REGION_ID(ea)) {
343 vsid = get_vsid(mm->context.id, ea);
345 case VMALLOC_REGION_ID:
347 vsid = get_kernel_vsid(ea);
350 case KERNEL_REGION_ID:
352 * Should never get here - entire 0xC0... region is bolted.
353 * Send the problem up to do_page_fault
358 * Send the problem up to do_page_fault
369 tmp = cpumask_of_cpu(smp_processor_id());
370 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
373 /* Is this a huge page ? */
374 if (unlikely(in_hugepage_area(mm->context, ea)))
375 ret = hash_huge_page(mm, access, ea, vsid, local);
377 ptep = find_linux_pte(pgdir, ea);
380 ret = __hash_page(ea, access, vsid, ptep, trap, local);
386 void flush_hash_page(unsigned long va, pte_t pte, int local)
388 unsigned long vpn, hash, secondary, slot;
389 unsigned long huge = pte_huge(pte);
392 vpn = va >> HPAGE_SHIFT;
394 vpn = va >> PAGE_SHIFT;
395 hash = hpt_hash(vpn, huge);
396 secondary = (pte_val(pte) & _PAGE_SECONDARY) >> 15;
399 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
400 slot += (pte_val(pte) & _PAGE_GROUP_IX) >> 12;
402 ppc_md.hpte_invalidate(slot, va, huge, local);
405 void flush_hash_range(unsigned long number, int local)
407 if (ppc_md.flush_hash_range) {
408 ppc_md.flush_hash_range(number, local);
411 struct ppc64_tlb_batch *batch =
412 &__get_cpu_var(ppc64_tlb_batch);
414 for (i = 0; i < number; i++)
415 flush_hash_page(batch->vaddr[i], batch->pte[i], local);
419 static inline void make_bl(unsigned int *insn_addr, void *func)
421 unsigned long funcp = *((unsigned long *)func);
422 int offset = funcp - (unsigned long)insn_addr;
424 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
425 flush_icache_range((unsigned long)insn_addr, 4+
426 (unsigned long)insn_addr);
430 * low_hash_fault is called when we the low level hash code failed
431 * to instert a PTE due to an hypervisor error
433 void low_hash_fault(struct pt_regs *regs, unsigned long address)
435 if (user_mode(regs)) {
438 info.si_signo = SIGBUS;
440 info.si_code = BUS_ADRERR;
441 info.si_addr = (void __user *)address;
442 force_sig_info(SIGBUS, &info, current);
445 bad_page_fault(regs, address, SIGBUS);
448 void __init htab_finish_init(void)
450 extern unsigned int *htab_call_hpte_insert1;
451 extern unsigned int *htab_call_hpte_insert2;
452 extern unsigned int *htab_call_hpte_remove;
453 extern unsigned int *htab_call_hpte_updatepp;
455 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
456 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
457 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
458 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);